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For Geode devices without a flatpanel aware BIOS, this enables the flatpanel power and data. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Acked-by: James Simmons <jsimmons@infradead.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
73 lines
2.2 KiB
C
73 lines
2.2 KiB
C
/*
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* Geode GX video device
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*
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* Copyright (C) 2006 Arcom Control Systems Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __VIDEO_GX_H__
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#define __VIDEO_GX_H__
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extern struct geode_vid_ops gx_vid_ops;
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/* GX Flatpanel control MSR */
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#define GX_VP_MSR_PAD_SELECT 0xC0002011
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#define GX_VP_PAD_SELECT_MASK 0x3FFFFFFF
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#define GX_VP_PAD_SELECT_TFT 0x1FFFFFFF
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/* Geode GX video processor registers */
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#define GX_DCFG 0x0008
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# define GX_DCFG_CRT_EN 0x00000001
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# define GX_DCFG_HSYNC_EN 0x00000002
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# define GX_DCFG_VSYNC_EN 0x00000004
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# define GX_DCFG_DAC_BL_EN 0x00000008
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# define GX_DCFG_FP_PWR_EN 0x00000040
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# define GX_DCFG_FP_DATA_EN 0x00000080
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# define GX_DCFG_CRT_HSYNC_POL 0x00000100
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# define GX_DCFG_CRT_VSYNC_POL 0x00000200
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# define GX_DCFG_CRT_SYNC_SKW_MASK 0x0001C000
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# define GX_DCFG_CRT_SYNC_SKW_DFLT 0x00010000
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# define GX_DCFG_VG_CK 0x00100000
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# define GX_DCFG_GV_GAM 0x00200000
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# define GX_DCFG_DAC_VREF 0x04000000
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/* Geode GX MISC video configuration */
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#define GX_MISC 0x50
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#define GX_MISC_GAM_EN 0x00000001
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#define GX_MISC_DAC_PWRDN 0x00000400
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#define GX_MISC_A_PWRDN 0x00000800
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/* Geode GX flat panel display control registers */
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#define GX_FP_PT1 0x0400
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#define GX_FP_PT1_VSIZE_MASK 0x7FF0000
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#define GX_FP_PT1_VSIZE_SHIFT 16
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#define GX_FP_PT2 0x408
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#define GX_FP_PT2_VSP (1 << 23)
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#define GX_FP_PT2_HSP (1 << 22)
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#define GX_FP_PM 0x410
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# define GX_FP_PM_P 0x01000000
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#define GX_FP_DFC 0x418
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/* Geode GX clock control MSRs */
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#define MSR_GLCP_SYS_RSTPLL 0x4c000014
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# define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (0x0000000000000002ull)
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# define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (0x0000000000000004ull)
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# define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (0x0000000000000008ull)
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#define MSR_GLCP_DOTPLL 0x4c000015
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# define MSR_GLCP_DOTPLL_DOTRESET (0x0000000000000001ull)
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# define MSR_GLCP_DOTPLL_BYPASS (0x0000000000008000ull)
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# define MSR_GLCP_DOTPLL_LOCK (0x0000000002000000ull)
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#endif /* !__VIDEO_GX_H__ */
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