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085ae41f66
There were three changes necessary in order to allow sparc64 to use setup-res.c: 1) Sparc64 roots the PCI I/O and MEM address space using parent resources contained in the PCI controller structure. I'm actually surprised no other platforms do this, especially ones like Alpha and PPC{,64}. These resources get linked into the iomem/ioport tree when PCI controllers are probed. So the hierarchy looks like this: iomem --| PCI controller 1 MEM space --| device 1 device 2 etc. PCI controller 2 MEM space --| ... ioport --| PCI controller 1 IO space --| ... PCI controller 2 IO space --| ... You get the idea. The drivers/pci/setup-res.c code allocates using plain iomem_space and ioport_space as the root, so that wouldn't work with the above setup. So I added a pcibios_select_root() that is used to handle this. It uses the PCI controller struct's io_space and mem_space on sparc64, and io{port,mem}_resource on every other platform to keep current behavior. 2) quirk_io_region() is buggy. It takes in raw BUS view addresses and tries to use them as a PCI resource. pci_claim_resource() expects the resource to be fully formed when it gets called. The sparc64 implementation would do the translation but that's absolutely wrong, because if the same resource gets released then re-claimed we'll adjust things twice. So I fixed up quirk_io_region() to do the proper pcibios_bus_to_resource() conversion before passing it on to pci_claim_resource(). 3) I was mistakedly __init'ing the function methods the PCI controller drivers provide on sparc64 to implement some parts of these routines. This was, of course, easy to fix. So we end up with the following, and that nasty SPARC64 makefile ifdef in drivers/pci/Makefile is finally zapped. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
297 lines
9.0 KiB
C
297 lines
9.0 KiB
C
#ifndef __ALPHA_PCI_H
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#define __ALPHA_PCI_H
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#ifdef __KERNEL__
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#include <linux/spinlock.h>
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#include <asm/scatterlist.h>
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#include <asm/machvec.h>
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/*
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* The following structure is used to manage multiple PCI busses.
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*/
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struct pci_dev;
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struct pci_bus;
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struct resource;
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struct pci_iommu_arena;
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struct page;
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/* A controller. Used to manage multiple PCI busses. */
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struct pci_controller {
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struct pci_controller *next;
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struct pci_bus *bus;
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struct resource *io_space;
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struct resource *mem_space;
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/* The following are for reporting to userland. The invariant is
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that if we report a BWX-capable dense memory, we do not report
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a sparse memory at all, even if it exists. */
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unsigned long sparse_mem_base;
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unsigned long dense_mem_base;
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unsigned long sparse_io_base;
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unsigned long dense_io_base;
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/* This one's for the kernel only. It's in KSEG somewhere. */
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unsigned long config_space_base;
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unsigned int index;
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/* For compatibility with current (as of July 2003) pciutils
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and XFree86. Eventually will be removed. */
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unsigned int need_domain_info;
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struct pci_iommu_arena *sg_pci;
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struct pci_iommu_arena *sg_isa;
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void *sysdata;
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};
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/* Override the logic in pci_scan_bus for skipping already-configured
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bus numbers. */
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#define pcibios_assign_all_busses() 1
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#define pcibios_scan_all_fns(a, b) 0
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#define PCIBIOS_MIN_IO alpha_mv.min_io_address
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#define PCIBIOS_MIN_MEM alpha_mv.min_mem_address
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extern void pcibios_set_master(struct pci_dev *dev);
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extern inline void pcibios_penalize_isa_irq(int irq, int active)
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{
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/* We don't do dynamic PCI IRQ allocation */
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}
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/* IOMMU controls. */
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/* The PCI address space does not equal the physical memory address space.
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The networking and block device layers use this boolean for bounce buffer
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decisions. */
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#define PCI_DMA_BUS_IS_PHYS 0
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/* Allocate and map kernel buffer using consistent mode DMA for PCI
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device. Returns non-NULL cpu-view pointer to the buffer if
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successful and sets *DMA_ADDRP to the pci side dma address as well,
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else DMA_ADDRP is undefined. */
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extern void *pci_alloc_consistent(struct pci_dev *, size_t, dma_addr_t *);
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/* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must
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be values that were returned from pci_alloc_consistent. SIZE must
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be the same as what as passed into pci_alloc_consistent.
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References to the memory and mappings associated with CPU_ADDR or
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DMA_ADDR past this call are illegal. */
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extern void pci_free_consistent(struct pci_dev *, size_t, void *, dma_addr_t);
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/* Map a single buffer of the indicate size for PCI DMA in streaming mode.
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The 32-bit PCI bus mastering address to use is returned. Once the device
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is given the dma address, the device owns this memory until either
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pci_unmap_single or pci_dma_sync_single_for_cpu is performed. */
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extern dma_addr_t pci_map_single(struct pci_dev *, void *, size_t, int);
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/* Likewise, but for a page instead of an address. */
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extern dma_addr_t pci_map_page(struct pci_dev *, struct page *,
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unsigned long, size_t, int);
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/* Test for pci_map_single or pci_map_page having generated an error. */
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static inline int
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pci_dma_mapping_error(dma_addr_t dma_addr)
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{
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return dma_addr == 0;
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}
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/* Unmap a single streaming mode DMA translation. The DMA_ADDR and
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SIZE must match what was provided for in a previous pci_map_single
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call. All other usages are undefined. After this call, reads by
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the cpu to the buffer are guaranteed to see whatever the device
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wrote there. */
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extern void pci_unmap_single(struct pci_dev *, dma_addr_t, size_t, int);
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extern void pci_unmap_page(struct pci_dev *, dma_addr_t, size_t, int);
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/* pci_unmap_{single,page} is not a nop, thus... */
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
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dma_addr_t ADDR_NAME;
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#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
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__u32 LEN_NAME;
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#define pci_unmap_addr(PTR, ADDR_NAME) \
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((PTR)->ADDR_NAME)
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#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
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(((PTR)->ADDR_NAME) = (VAL))
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#define pci_unmap_len(PTR, LEN_NAME) \
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((PTR)->LEN_NAME)
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
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(((PTR)->LEN_NAME) = (VAL))
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/* Map a set of buffers described by scatterlist in streaming mode for
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PCI DMA. This is the scatter-gather version of the above
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pci_map_single interface. Here the scatter gather list elements
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are each tagged with the appropriate PCI dma address and length.
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They are obtained via sg_dma_{address,length}(SG).
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NOTE: An implementation may be able to use a smaller number of DMA
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address/length pairs than there are SG table elements. (for
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example via virtual mapping capabilities) The routine returns the
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number of addr/length pairs actually used, at most nents.
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Device ownership issues as mentioned above for pci_map_single are
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the same here. */
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extern int pci_map_sg(struct pci_dev *, struct scatterlist *, int, int);
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/* Unmap a set of streaming mode DMA translations. Again, cpu read
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rules concerning calls here are the same as for pci_unmap_single()
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above. */
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extern void pci_unmap_sg(struct pci_dev *, struct scatterlist *, int, int);
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/* Make physical memory consistent for a single streaming mode DMA
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translation after a transfer and device currently has ownership
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of the buffer.
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If you perform a pci_map_single() but wish to interrogate the
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buffer using the cpu, yet do not wish to teardown the PCI dma
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mapping, you must call this function before doing so. At the next
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point you give the PCI dma address back to the card, you must first
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perform a pci_dma_sync_for_device, and then the device again owns
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the buffer. */
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static inline void
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pci_dma_sync_single_for_cpu(struct pci_dev *dev, dma_addr_t dma_addr,
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long size, int direction)
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{
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/* Nothing to do. */
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}
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static inline void
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pci_dma_sync_single_for_device(struct pci_dev *dev, dma_addr_t dma_addr,
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size_t size, int direction)
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{
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/* Nothing to do. */
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}
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/* Make physical memory consistent for a set of streaming mode DMA
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translations after a transfer. The same as pci_dma_sync_single_*
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but for a scatter-gather list, same rules and usage. */
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static inline void
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pci_dma_sync_sg_for_cpu(struct pci_dev *dev, struct scatterlist *sg,
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int nents, int direction)
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{
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/* Nothing to do. */
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}
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static inline void
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pci_dma_sync_sg_for_device(struct pci_dev *dev, struct scatterlist *sg,
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int nents, int direction)
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{
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/* Nothing to do. */
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}
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/* Return whether the given PCI device DMA address mask can
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be supported properly. For example, if your device can
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only drive the low 24-bits during PCI bus mastering, then
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you would pass 0x00ffffff as the mask to this function. */
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extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
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/* True if the machine supports DAC addressing, and DEV can
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make use of it given MASK. */
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extern int pci_dac_dma_supported(struct pci_dev *hwdev, u64 mask);
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/* Convert to/from DAC dma address and struct page. */
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extern dma64_addr_t pci_dac_page_to_dma(struct pci_dev *, struct page *,
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unsigned long, int);
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extern struct page *pci_dac_dma_to_page(struct pci_dev *, dma64_addr_t);
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extern unsigned long pci_dac_dma_to_offset(struct pci_dev *, dma64_addr_t);
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static inline void
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pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr,
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size_t len, int direction)
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{
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/* Nothing to do. */
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}
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static inline void
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pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr,
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size_t len, int direction)
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{
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/* Nothing to do. */
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}
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#ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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unsigned long cacheline_size;
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u8 byte;
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
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if (byte == 0)
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cacheline_size = 1024;
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else
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cacheline_size = (int) byte * 4;
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*strat = PCI_DMA_BURST_BOUNDARY;
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*strategy_parameter = cacheline_size;
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}
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#endif
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/* TODO: integrate with include/asm-generic/pci.h ? */
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static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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{
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return channel ? 15 : 14;
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}
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extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
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struct resource *);
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extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region);
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static inline struct resource *
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pcibios_select_root(struct pci_dev *pdev, struct resource *res)
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{
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struct resource *root = NULL;
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if (res->flags & IORESOURCE_IO)
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root = &ioport_resource;
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if (res->flags & IORESOURCE_MEM)
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root = &iomem_resource;
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return root;
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}
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#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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struct pci_controller *hose = bus->sysdata;
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return hose->need_domain_info;
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}
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static inline void
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pcibios_add_platform_entries(struct pci_dev *dev)
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{
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}
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struct pci_dev *alpha_gendev_to_pci(struct device *dev);
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#endif /* __KERNEL__ */
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/* Values for the `which' argument to sys_pciconfig_iobase. */
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#define IOBASE_HOSE 0
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#define IOBASE_SPARSE_MEM 1
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#define IOBASE_DENSE_MEM 2
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#define IOBASE_SPARSE_IO 3
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#define IOBASE_DENSE_IO 4
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#define IOBASE_ROOT_BUS 5
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#define IOBASE_FROM_HOSE 0x10000
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#endif /* __ALPHA_PCI_H */
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