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54672386cc
On TI chips (OHCI-Lynx and later), enable link enhancements features that TI recommends to be used. None of these are required for proper operation, but they are safe and nice to have. In theory, these bits should have been set by default, but in practice, some BIOS/EEPROM writers apparently do not read the datasheet, or get spooked by names like "unfair". Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
166 lines
7.2 KiB
C
166 lines
7.2 KiB
C
#ifndef _FIREWIRE_OHCI_H
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#define _FIREWIRE_OHCI_H
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/* OHCI register map */
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#define OHCI1394_Version 0x000
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#define OHCI1394_GUID_ROM 0x004
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#define OHCI1394_ATRetries 0x008
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#define OHCI1394_CSRData 0x00C
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#define OHCI1394_CSRCompareData 0x010
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#define OHCI1394_CSRControl 0x014
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#define OHCI1394_ConfigROMhdr 0x018
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#define OHCI1394_BusID 0x01C
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#define OHCI1394_BusOptions 0x020
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#define OHCI1394_GUIDHi 0x024
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#define OHCI1394_GUIDLo 0x028
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#define OHCI1394_ConfigROMmap 0x034
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#define OHCI1394_PostedWriteAddressLo 0x038
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#define OHCI1394_PostedWriteAddressHi 0x03C
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#define OHCI1394_VendorID 0x040
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#define OHCI1394_HCControlSet 0x050
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#define OHCI1394_HCControlClear 0x054
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#define OHCI1394_HCControl_BIBimageValid 0x80000000
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#define OHCI1394_HCControl_noByteSwapData 0x40000000
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#define OHCI1394_HCControl_programPhyEnable 0x00800000
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#define OHCI1394_HCControl_aPhyEnhanceEnable 0x00400000
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#define OHCI1394_HCControl_LPS 0x00080000
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#define OHCI1394_HCControl_postedWriteEnable 0x00040000
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#define OHCI1394_HCControl_linkEnable 0x00020000
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#define OHCI1394_HCControl_softReset 0x00010000
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#define OHCI1394_SelfIDBuffer 0x064
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#define OHCI1394_SelfIDCount 0x068
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#define OHCI1394_SelfIDCount_selfIDError 0x80000000
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#define OHCI1394_IRMultiChanMaskHiSet 0x070
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#define OHCI1394_IRMultiChanMaskHiClear 0x074
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#define OHCI1394_IRMultiChanMaskLoSet 0x078
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#define OHCI1394_IRMultiChanMaskLoClear 0x07C
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#define OHCI1394_IntEventSet 0x080
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#define OHCI1394_IntEventClear 0x084
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#define OHCI1394_IntMaskSet 0x088
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#define OHCI1394_IntMaskClear 0x08C
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#define OHCI1394_IsoXmitIntEventSet 0x090
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#define OHCI1394_IsoXmitIntEventClear 0x094
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#define OHCI1394_IsoXmitIntMaskSet 0x098
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#define OHCI1394_IsoXmitIntMaskClear 0x09C
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#define OHCI1394_IsoRecvIntEventSet 0x0A0
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#define OHCI1394_IsoRecvIntEventClear 0x0A4
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#define OHCI1394_IsoRecvIntMaskSet 0x0A8
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#define OHCI1394_IsoRecvIntMaskClear 0x0AC
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#define OHCI1394_InitialBandwidthAvailable 0x0B0
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#define OHCI1394_InitialChannelsAvailableHi 0x0B4
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#define OHCI1394_InitialChannelsAvailableLo 0x0B8
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#define OHCI1394_FairnessControl 0x0DC
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#define OHCI1394_LinkControlSet 0x0E0
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#define OHCI1394_LinkControlClear 0x0E4
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#define OHCI1394_LinkControl_rcvSelfID (1 << 9)
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#define OHCI1394_LinkControl_rcvPhyPkt (1 << 10)
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#define OHCI1394_LinkControl_cycleTimerEnable (1 << 20)
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#define OHCI1394_LinkControl_cycleMaster (1 << 21)
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#define OHCI1394_LinkControl_cycleSource (1 << 22)
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#define OHCI1394_NodeID 0x0E8
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#define OHCI1394_NodeID_idValid 0x80000000
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#define OHCI1394_NodeID_nodeNumber 0x0000003f
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#define OHCI1394_NodeID_busNumber 0x0000ffc0
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#define OHCI1394_PhyControl 0x0EC
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#define OHCI1394_PhyControl_Read(addr) (((addr) << 8) | 0x00008000)
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#define OHCI1394_PhyControl_ReadDone 0x80000000
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#define OHCI1394_PhyControl_ReadData(r) (((r) & 0x00ff0000) >> 16)
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#define OHCI1394_PhyControl_Write(addr, data) (((addr) << 8) | (data) | 0x00004000)
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#define OHCI1394_PhyControl_WritePending 0x00004000
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#define OHCI1394_IsochronousCycleTimer 0x0F0
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#define OHCI1394_AsReqFilterHiSet 0x100
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#define OHCI1394_AsReqFilterHiClear 0x104
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#define OHCI1394_AsReqFilterLoSet 0x108
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#define OHCI1394_AsReqFilterLoClear 0x10C
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#define OHCI1394_PhyReqFilterHiSet 0x110
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#define OHCI1394_PhyReqFilterHiClear 0x114
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#define OHCI1394_PhyReqFilterLoSet 0x118
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#define OHCI1394_PhyReqFilterLoClear 0x11C
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#define OHCI1394_PhyUpperBound 0x120
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#define OHCI1394_AsReqTrContextBase 0x180
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#define OHCI1394_AsReqTrContextControlSet 0x180
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#define OHCI1394_AsReqTrContextControlClear 0x184
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#define OHCI1394_AsReqTrCommandPtr 0x18C
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#define OHCI1394_AsRspTrContextBase 0x1A0
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#define OHCI1394_AsRspTrContextControlSet 0x1A0
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#define OHCI1394_AsRspTrContextControlClear 0x1A4
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#define OHCI1394_AsRspTrCommandPtr 0x1AC
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#define OHCI1394_AsReqRcvContextBase 0x1C0
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#define OHCI1394_AsReqRcvContextControlSet 0x1C0
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#define OHCI1394_AsReqRcvContextControlClear 0x1C4
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#define OHCI1394_AsReqRcvCommandPtr 0x1CC
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#define OHCI1394_AsRspRcvContextBase 0x1E0
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#define OHCI1394_AsRspRcvContextControlSet 0x1E0
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#define OHCI1394_AsRspRcvContextControlClear 0x1E4
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#define OHCI1394_AsRspRcvCommandPtr 0x1EC
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/* Isochronous transmit registers */
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#define OHCI1394_IsoXmitContextBase(n) (0x200 + 16 * (n))
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#define OHCI1394_IsoXmitContextControlSet(n) (0x200 + 16 * (n))
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#define OHCI1394_IsoXmitContextControlClear(n) (0x204 + 16 * (n))
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#define OHCI1394_IsoXmitCommandPtr(n) (0x20C + 16 * (n))
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/* Isochronous receive registers */
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#define OHCI1394_IsoRcvContextBase(n) (0x400 + 32 * (n))
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#define OHCI1394_IsoRcvContextControlSet(n) (0x400 + 32 * (n))
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#define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n))
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#define OHCI1394_IsoRcvCommandPtr(n) (0x40C + 32 * (n))
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#define OHCI1394_IsoRcvContextMatch(n) (0x410 + 32 * (n))
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/* Interrupts Mask/Events */
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#define OHCI1394_reqTxComplete 0x00000001
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#define OHCI1394_respTxComplete 0x00000002
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#define OHCI1394_ARRQ 0x00000004
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#define OHCI1394_ARRS 0x00000008
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#define OHCI1394_RQPkt 0x00000010
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#define OHCI1394_RSPkt 0x00000020
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#define OHCI1394_isochTx 0x00000040
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#define OHCI1394_isochRx 0x00000080
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#define OHCI1394_postedWriteErr 0x00000100
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#define OHCI1394_lockRespErr 0x00000200
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#define OHCI1394_selfIDComplete 0x00010000
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#define OHCI1394_busReset 0x00020000
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#define OHCI1394_regAccessFail 0x00040000
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#define OHCI1394_phy 0x00080000
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#define OHCI1394_cycleSynch 0x00100000
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#define OHCI1394_cycle64Seconds 0x00200000
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#define OHCI1394_cycleLost 0x00400000
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#define OHCI1394_cycleInconsistent 0x00800000
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#define OHCI1394_unrecoverableError 0x01000000
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#define OHCI1394_cycleTooLong 0x02000000
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#define OHCI1394_phyRegRcvd 0x04000000
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#define OHCI1394_masterIntEnable 0x80000000
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#define OHCI1394_evt_no_status 0x0
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#define OHCI1394_evt_long_packet 0x2
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#define OHCI1394_evt_missing_ack 0x3
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#define OHCI1394_evt_underrun 0x4
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#define OHCI1394_evt_overrun 0x5
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#define OHCI1394_evt_descriptor_read 0x6
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#define OHCI1394_evt_data_read 0x7
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#define OHCI1394_evt_data_write 0x8
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#define OHCI1394_evt_bus_reset 0x9
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#define OHCI1394_evt_timeout 0xa
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#define OHCI1394_evt_tcode_err 0xb
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#define OHCI1394_evt_reserved_b 0xc
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#define OHCI1394_evt_reserved_c 0xd
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#define OHCI1394_evt_unknown 0xe
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#define OHCI1394_evt_flushed 0xf
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#define OHCI1394_phy_tcode 0xe
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/* TI extensions */
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#define PCI_CFG_TI_LinkEnh 0xf4
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#define TI_LinkEnh_enab_accel 0x00000002
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#define TI_LinkEnh_enab_unfair 0x00000080
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#define TI_LinkEnh_atx_thresh_mask 0x00003000
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#define TI_LinkEnh_atx_thresh_1_7K 0x00001000
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#endif /* _FIREWIRE_OHCI_H */
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