Rafał Miłecki 04ad1fb264 ssb: update reject bit for Target State Low ... My 14e4:4315 is SSB_IDLOW_SSBREV_26: read32 0xfaafcff8 -> 0x600422d5 My 14e4:4328 is SSB_IDLOW_SSBREV_24: read32 0xfaafcff8 -> 0x400422c5 My 14e4:432b is SSB_IDLOW_SSBREV_26 again: read32 0xfaafcff8 -> 0x600422d5 For all of them wl driver is using 0x2 reject bit: write32(0xf98) <- 0x00010002 So it seems SSB 2.3 is the exception using another bit. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>		2011-04-26 15:50:29 -04:00
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ssb_driver_chipcommon.h	ssb: cc: clear GPIOPULL registers on init	2011-04-25 14:50:20 -04:00
ssb_driver_extif.h
ssb_driver_gige.h	SSB: Fix nvram_get on BCM47xx platform	2010-12-16 18:11:00 +00:00
ssb_driver_mips.h
ssb_driver_pci.h
ssb_embedded.h
ssb_regs.h	ssb: update reject bit for Target State Low	2011-04-26 15:50:29 -04:00
ssb.h	ssb: trivial: use u8 for chip_rev (it's mask is 0xF)	2011-04-04 16:20:06 -04:00