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e2e8bfdf61
Convert MicBias widgets to supply widget. On tlv320aic3x, Mic bias power on/off shares the same register bits with output mic bias voltage. So, when power on mic bias, we need reclaim it to voltage value. Provide a new platform data so that the micbias voltage can be sent according to board requirement. Now since tlv320aic3x codec driver is DT aware, update dt files and functions to handle this new "micbias-vg" platform data. Because of sharing of bits, when enabling the micbias, voltage also needs to be updated. So use SND_SOC_DAPM_POST_PMU & SND_SOC_DAPM_PRE_PMD macro to create an event to handle this. Since micbias is converted to supply widget, updated machine drivers as well. This change is runtime tested on da850-evm with audio loopback (arecord|aplay) for confirmation. Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
283 lines
8.2 KiB
C
283 lines
8.2 KiB
C
/*
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* ALSA SoC TLV320AIC3X codec driver
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*
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* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
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* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _AIC3X_H
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#define _AIC3X_H
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/* AIC3X register space */
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#define AIC3X_CACHEREGNUM 110
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/* Page select register */
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#define AIC3X_PAGE_SELECT 0
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/* Software reset register */
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#define AIC3X_RESET 1
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/* Codec Sample rate select register */
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#define AIC3X_SAMPLE_RATE_SEL_REG 2
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/* PLL progrramming register A */
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#define AIC3X_PLL_PROGA_REG 3
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/* PLL progrramming register B */
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#define AIC3X_PLL_PROGB_REG 4
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/* PLL progrramming register C */
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#define AIC3X_PLL_PROGC_REG 5
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/* PLL progrramming register D */
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#define AIC3X_PLL_PROGD_REG 6
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/* Codec datapath setup register */
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#define AIC3X_CODEC_DATAPATH_REG 7
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/* Audio serial data interface control register A */
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#define AIC3X_ASD_INTF_CTRLA 8
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/* Audio serial data interface control register B */
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#define AIC3X_ASD_INTF_CTRLB 9
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/* Audio serial data interface control register C */
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#define AIC3X_ASD_INTF_CTRLC 10
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/* Audio overflow status and PLL R value programming register */
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#define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
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/* Audio codec digital filter control register */
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#define AIC3X_CODEC_DFILT_CTRL 12
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/* Headset/button press detection register */
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#define AIC3X_HEADSET_DETECT_CTRL_A 13
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#define AIC3X_HEADSET_DETECT_CTRL_B 14
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/* ADC PGA Gain control registers */
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#define LADC_VOL 15
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#define RADC_VOL 16
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/* MIC3 control registers */
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#define MIC3LR_2_LADC_CTRL 17
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#define MIC3LR_2_RADC_CTRL 18
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/* Line1 Input control registers */
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#define LINE1L_2_LADC_CTRL 19
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#define LINE1R_2_LADC_CTRL 21
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#define LINE1R_2_RADC_CTRL 22
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#define LINE1L_2_RADC_CTRL 24
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/* Line2 Input control registers */
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#define LINE2L_2_LADC_CTRL 20
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#define LINE2R_2_RADC_CTRL 23
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/* MICBIAS Control Register */
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#define MICBIAS_CTRL 25
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/* AGC Control Registers A, B, C */
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#define LAGC_CTRL_A 26
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#define LAGC_CTRL_B 27
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#define LAGC_CTRL_C 28
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#define RAGC_CTRL_A 29
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#define RAGC_CTRL_B 30
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#define RAGC_CTRL_C 31
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/* DAC Power and Left High Power Output control registers */
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#define DAC_PWR 37
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#define HPLCOM_CFG 37
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/* Right High Power Output control registers */
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#define HPRCOM_CFG 38
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/* High Power Output Stage Control Register */
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#define HPOUT_SC 40
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/* DAC Output Switching control registers */
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#define DAC_LINE_MUX 41
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/* High Power Output Driver Pop Reduction registers */
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#define HPOUT_POP_REDUCTION 42
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/* DAC Digital control registers */
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#define LDAC_VOL 43
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#define RDAC_VOL 44
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/* Left High Power Output control registers */
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#define LINE2L_2_HPLOUT_VOL 45
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#define PGAL_2_HPLOUT_VOL 46
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#define DACL1_2_HPLOUT_VOL 47
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#define LINE2R_2_HPLOUT_VOL 48
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#define PGAR_2_HPLOUT_VOL 49
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#define DACR1_2_HPLOUT_VOL 50
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#define HPLOUT_CTRL 51
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/* Left High Power COM control registers */
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#define LINE2L_2_HPLCOM_VOL 52
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#define PGAL_2_HPLCOM_VOL 53
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#define DACL1_2_HPLCOM_VOL 54
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#define LINE2R_2_HPLCOM_VOL 55
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#define PGAR_2_HPLCOM_VOL 56
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#define DACR1_2_HPLCOM_VOL 57
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#define HPLCOM_CTRL 58
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/* Right High Power Output control registers */
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#define LINE2L_2_HPROUT_VOL 59
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#define PGAL_2_HPROUT_VOL 60
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#define DACL1_2_HPROUT_VOL 61
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#define LINE2R_2_HPROUT_VOL 62
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#define PGAR_2_HPROUT_VOL 63
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#define DACR1_2_HPROUT_VOL 64
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#define HPROUT_CTRL 65
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/* Right High Power COM control registers */
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#define LINE2L_2_HPRCOM_VOL 66
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#define PGAL_2_HPRCOM_VOL 67
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#define DACL1_2_HPRCOM_VOL 68
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#define LINE2R_2_HPRCOM_VOL 69
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#define PGAR_2_HPRCOM_VOL 70
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#define DACR1_2_HPRCOM_VOL 71
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#define HPRCOM_CTRL 72
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/* Mono Line Output Plus/Minus control registers */
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#define LINE2L_2_MONOLOPM_VOL 73
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#define PGAL_2_MONOLOPM_VOL 74
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#define DACL1_2_MONOLOPM_VOL 75
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#define LINE2R_2_MONOLOPM_VOL 76
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#define PGAR_2_MONOLOPM_VOL 77
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#define DACR1_2_MONOLOPM_VOL 78
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#define MONOLOPM_CTRL 79
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/* Class-D speaker driver on tlv320aic3007 */
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#define CLASSD_CTRL 73
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/* Left Line Output Plus/Minus control registers */
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#define LINE2L_2_LLOPM_VOL 80
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#define PGAL_2_LLOPM_VOL 81
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#define DACL1_2_LLOPM_VOL 82
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#define LINE2R_2_LLOPM_VOL 83
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#define PGAR_2_LLOPM_VOL 84
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#define DACR1_2_LLOPM_VOL 85
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#define LLOPM_CTRL 86
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/* Right Line Output Plus/Minus control registers */
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#define LINE2L_2_RLOPM_VOL 87
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#define PGAL_2_RLOPM_VOL 88
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#define DACL1_2_RLOPM_VOL 89
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#define LINE2R_2_RLOPM_VOL 90
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#define PGAR_2_RLOPM_VOL 91
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#define DACR1_2_RLOPM_VOL 92
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#define RLOPM_CTRL 93
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/* GPIO/IRQ registers */
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#define AIC3X_STICKY_IRQ_FLAGS_REG 96
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#define AIC3X_RT_IRQ_FLAGS_REG 97
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#define AIC3X_GPIO1_REG 98
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#define AIC3X_GPIO2_REG 99
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#define AIC3X_GPIOA_REG 100
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#define AIC3X_GPIOB_REG 101
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/* Clock generation control register */
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#define AIC3X_CLKGEN_CTRL_REG 102
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/* New AGC registers */
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#define LAGCN_ATTACK 103
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#define LAGCN_DECAY 104
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#define RAGCN_ATTACK 105
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#define RAGCN_DECAY 106
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/* New Programmable ADC Digital Path and I2C Bus Condition Register */
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#define NEW_ADC_DIGITALPATH 107
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/* Passive Analog Signal Bypass Selection During Powerdown Register */
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#define PASSIVE_BYPASS 108
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/* DAC Quiescent Current Adjustment Register */
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#define DAC_ICC_ADJ 109
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/* Page select register bits */
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#define PAGE0_SELECT 0
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#define PAGE1_SELECT 1
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/* Audio serial data interface control register A bits */
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#define BIT_CLK_MASTER 0x80
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#define WORD_CLK_MASTER 0x40
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/* Codec Datapath setup register 7 */
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#define FSREF_44100 (1 << 7)
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#define FSREF_48000 (0 << 7)
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#define DUAL_RATE_MODE ((1 << 5) | (1 << 6))
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#define LDAC2LCH (0x1 << 3)
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#define RDAC2RCH (0x1 << 1)
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#define LDAC2RCH (0x2 << 3)
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#define RDAC2LCH (0x2 << 1)
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#define LDAC2MONOMIX (0x3 << 3)
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#define RDAC2MONOMIX (0x3 << 1)
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/* PLL registers bitfields */
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#define PLLP_SHIFT 0
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#define PLLP_MASK 7
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#define PLLQ_SHIFT 3
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#define PLLR_SHIFT 0
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#define PLLJ_SHIFT 2
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#define PLLD_MSB_SHIFT 0
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#define PLLD_LSB_SHIFT 2
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/* Clock generation register bits */
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#define CODEC_CLKIN_PLLDIV 0
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#define CODEC_CLKIN_CLKDIV 1
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#define PLL_CLKIN_SHIFT 4
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#define MCLK_SOURCE 0x0
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#define PLL_CLKDIV_SHIFT 0
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#define PLLCLK_IN_MASK 0x30
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#define PLLCLK_IN_SHIFT 4
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#define CLKDIV_IN_MASK 0xc0
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#define CLKDIV_IN_SHIFT 6
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/* clock in source */
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#define CLKIN_MCLK 0
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#define CLKIN_GPIO2 1
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#define CLKIN_BCLK 2
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/* Software reset register bits */
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#define SOFT_RESET 0x80
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/* PLL progrramming register A bits */
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#define PLL_ENABLE 0x80
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/* Route bits */
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#define ROUTE_ON 0x80
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/* Mute bits */
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#define UNMUTE 0x08
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#define MUTE_ON 0x80
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/* Power bits */
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#define LADC_PWR_ON 0x04
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#define RADC_PWR_ON 0x04
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#define LDAC_PWR_ON 0x80
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#define RDAC_PWR_ON 0x40
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#define HPLOUT_PWR_ON 0x01
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#define HPROUT_PWR_ON 0x01
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#define HPLCOM_PWR_ON 0x01
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#define HPRCOM_PWR_ON 0x01
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#define MONOLOPM_PWR_ON 0x01
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#define LLOPM_PWR_ON 0x01
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#define RLOPM_PWR_ON 0x01
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#define INVERT_VOL(val) (0x7f - val)
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/* Default output volume (inverted) */
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#define DEFAULT_VOL INVERT_VOL(0x50)
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/* Default input volume */
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#define DEFAULT_GAIN 0x20
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/* MICBIAS Control Register */
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#define MICBIAS_LEVEL_SHIFT (6)
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#define MICBIAS_LEVEL_MASK (3 << 6)
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/* headset detection / button API */
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/* The AIC3x supports detection of stereo headsets (GND + left + right signal)
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* and cellular headsets (GND + speaker output + microphone input).
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* It is recommended to enable MIC bias for this function to work properly.
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* For more information, please refer to the datasheet. */
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enum {
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AIC3X_HEADSET_DETECT_OFF = 0,
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AIC3X_HEADSET_DETECT_STEREO = 1,
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AIC3X_HEADSET_DETECT_CELLULAR = 2,
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AIC3X_HEADSET_DETECT_BOTH = 3
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};
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enum {
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AIC3X_HEADSET_DEBOUNCE_16MS = 0,
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AIC3X_HEADSET_DEBOUNCE_32MS = 1,
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AIC3X_HEADSET_DEBOUNCE_64MS = 2,
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AIC3X_HEADSET_DEBOUNCE_128MS = 3,
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AIC3X_HEADSET_DEBOUNCE_256MS = 4,
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AIC3X_HEADSET_DEBOUNCE_512MS = 5
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};
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enum {
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AIC3X_BUTTON_DEBOUNCE_0MS = 0,
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AIC3X_BUTTON_DEBOUNCE_8MS = 1,
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AIC3X_BUTTON_DEBOUNCE_16MS = 2,
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AIC3X_BUTTON_DEBOUNCE_32MS = 3
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};
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#define AIC3X_HEADSET_DETECT_ENABLED 0x80
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#define AIC3X_HEADSET_DETECT_SHIFT 5
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#define AIC3X_HEADSET_DETECT_MASK 3
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#define AIC3X_HEADSET_DEBOUNCE_SHIFT 2
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#define AIC3X_HEADSET_DEBOUNCE_MASK 7
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#define AIC3X_BUTTON_DEBOUNCE_SHIFT 0
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#define AIC3X_BUTTON_DEBOUNCE_MASK 3
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#endif /* _AIC3X_H */
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