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73bcc942f4
The Arria10 SDRAM and ECC system differs significantly from the Cyclone5 and Arria5 SoCs. This patch adds support for the Arria10 SoC. 1) IRQ handler needs to support SHARED IRQ 2) Support sberr and dberr address reporting. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: ijc+devicetree@hellion.org.uk Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: m.chehab@samsung.com Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: tthayer.linux@gmail.com Link: http://lkml.kernel.org/r/1433428128-7292-4-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
202 lines
6.1 KiB
C
202 lines
6.1 KiB
C
/*
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*
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* Copyright (C) 2015 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _ALTERA_EDAC_H
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#define _ALTERA_EDAC_H
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#include <linux/edac.h>
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#include <linux/types.h>
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/* SDRAM Controller CtrlCfg Register */
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#define CV_CTLCFG_OFST 0x00
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/* SDRAM Controller CtrlCfg Register Bit Masks */
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#define CV_CTLCFG_ECC_EN 0x400
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#define CV_CTLCFG_ECC_CORR_EN 0x800
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#define CV_CTLCFG_GEN_SB_ERR 0x2000
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#define CV_CTLCFG_GEN_DB_ERR 0x4000
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#define CV_CTLCFG_ECC_AUTO_EN (CV_CTLCFG_ECC_EN | \
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CV_CTLCFG_ECC_CORR_EN)
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/* SDRAM Controller Address Width Register */
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#define CV_DRAMADDRW_OFST 0x2C
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/* SDRAM Controller Address Widths Field Register */
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#define DRAMADDRW_COLBIT_MASK 0x001F
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#define DRAMADDRW_COLBIT_SHIFT 0
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#define DRAMADDRW_ROWBIT_MASK 0x03E0
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#define DRAMADDRW_ROWBIT_SHIFT 5
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#define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
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#define CV_DRAMADDRW_BANKBIT_SHIFT 10
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#define CV_DRAMADDRW_CSBIT_MASK 0xE000
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#define CV_DRAMADDRW_CSBIT_SHIFT 13
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/* SDRAM Controller Interface Data Width Register */
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#define CV_DRAMIFWIDTH_OFST 0x30
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/* SDRAM Controller Interface Data Width Defines */
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#define CV_DRAMIFWIDTH_16B_ECC 24
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#define CV_DRAMIFWIDTH_32B_ECC 40
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/* SDRAM Controller DRAM Status Register */
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#define CV_DRAMSTS_OFST 0x38
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/* SDRAM Controller DRAM Status Register Bit Masks */
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#define CV_DRAMSTS_SBEERR 0x04
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#define CV_DRAMSTS_DBEERR 0x08
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#define CV_DRAMSTS_CORR_DROP 0x10
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/* SDRAM Controller DRAM IRQ Register */
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#define CV_DRAMINTR_OFST 0x3C
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/* SDRAM Controller DRAM IRQ Register Bit Masks */
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#define CV_DRAMINTR_INTREN 0x01
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#define CV_DRAMINTR_SBEMASK 0x02
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#define CV_DRAMINTR_DBEMASK 0x04
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#define CV_DRAMINTR_CORRDROPMASK 0x08
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#define CV_DRAMINTR_INTRCLR 0x10
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/* SDRAM Controller Single Bit Error Count Register */
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#define CV_SBECOUNT_OFST 0x40
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/* SDRAM Controller Double Bit Error Count Register */
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#define CV_DBECOUNT_OFST 0x44
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/* SDRAM Controller ECC Error Address Register */
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#define CV_ERRADDR_OFST 0x48
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/*-----------------------------------------*/
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/* SDRAM Controller EccCtrl Register */
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#define A10_ECCCTRL1_OFST 0x00
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/* SDRAM Controller EccCtrl Register Bit Masks */
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#define A10_ECCCTRL1_ECC_EN 0x001
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#define A10_ECCCTRL1_CNT_RST 0x010
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#define A10_ECCCTRL1_AWB_CNT_RST 0x100
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#define A10_ECC_CNT_RESET_MASK (A10_ECCCTRL1_CNT_RST | \
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A10_ECCCTRL1_AWB_CNT_RST)
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/* SDRAM Controller Address Width Register */
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#define CV_DRAMADDRW 0xFFC2502C
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#define A10_DRAMADDRW 0xFFCFA0A8
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/* SDRAM Controller Address Widths Field Register */
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#define DRAMADDRW_COLBIT_MASK 0x001F
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#define DRAMADDRW_COLBIT_SHIFT 0
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#define DRAMADDRW_ROWBIT_MASK 0x03E0
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#define DRAMADDRW_ROWBIT_SHIFT 5
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#define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
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#define CV_DRAMADDRW_BANKBIT_SHIFT 10
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#define CV_DRAMADDRW_CSBIT_MASK 0xE000
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#define CV_DRAMADDRW_CSBIT_SHIFT 13
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#define A10_DRAMADDRW_BANKBIT_MASK 0x3C00
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#define A10_DRAMADDRW_BANKBIT_SHIFT 10
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#define A10_DRAMADDRW_GRPBIT_MASK 0xC000
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#define A10_DRAMADDRW_GRPBIT_SHIFT 14
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#define A10_DRAMADDRW_CSBIT_MASK 0x70000
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#define A10_DRAMADDRW_CSBIT_SHIFT 16
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/* SDRAM Controller Interface Data Width Register */
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#define CV_DRAMIFWIDTH 0xFFC25030
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#define A10_DRAMIFWIDTH 0xFFCFB008
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/* SDRAM Controller Interface Data Width Defines */
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#define CV_DRAMIFWIDTH_16B_ECC 24
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#define CV_DRAMIFWIDTH_32B_ECC 40
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#define A10_DRAMIFWIDTH_16B 0x0
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#define A10_DRAMIFWIDTH_32B 0x1
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#define A10_DRAMIFWIDTH_64B 0x2
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/* SDRAM Controller DRAM IRQ Register */
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#define A10_ERRINTEN_OFST 0x10
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/* SDRAM Controller DRAM IRQ Register Bit Masks */
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#define A10_ERRINTEN_SERRINTEN 0x01
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#define A10_ERRINTEN_DERRINTEN 0x02
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#define A10_ECC_IRQ_EN_MASK (A10_ERRINTEN_SERRINTEN | \
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A10_ERRINTEN_DERRINTEN)
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/* SDRAM Interrupt Mode Register */
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#define A10_INTMODE_OFST 0x1C
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#define A10_INTMODE_SB_INT 1
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/* SDRAM Controller Error Status Register */
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#define A10_INTSTAT_OFST 0x20
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/* SDRAM Controller Error Status Register Bit Masks */
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#define A10_INTSTAT_SBEERR 0x01
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#define A10_INTSTAT_DBEERR 0x02
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/* SDRAM Controller ECC Error Address Register */
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#define A10_DERRADDR_OFST 0x2C
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#define A10_SERRADDR_OFST 0x30
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/* SDRAM Controller ECC Diagnostic Register */
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#define A10_DIAGINTTEST_OFST 0x24
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#define A10_DIAGINT_TSERRA_MASK 0x0001
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#define A10_DIAGINT_TDERRA_MASK 0x0100
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#define A10_SBERR_IRQ 34
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#define A10_DBERR_IRQ 32
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/* SDRAM Single Bit Error Count Compare Set Register */
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#define A10_SERRCNTREG_OFST 0x3C
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#define A10_SYMAN_INTMASK_CLR 0xFFD06098
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#define A10_INTMASK_CLR_OFST 0x10
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#define A10_DDR0_IRQ_MASK BIT(17)
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struct altr_sdram_prv_data {
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int ecc_ctrl_offset;
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int ecc_ctl_en_mask;
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int ecc_cecnt_offset;
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int ecc_uecnt_offset;
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int ecc_stat_offset;
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int ecc_stat_ce_mask;
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int ecc_stat_ue_mask;
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int ecc_saddr_offset;
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int ecc_daddr_offset;
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int ecc_irq_en_offset;
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int ecc_irq_en_mask;
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int ecc_irq_clr_offset;
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int ecc_irq_clr_mask;
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int ecc_cnt_rst_offset;
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int ecc_cnt_rst_mask;
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#ifdef CONFIG_EDAC_DEBUG
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struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr;
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int ecc_enable_mask;
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int ce_set_mask;
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int ue_set_mask;
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int ce_ue_trgr_offset;
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#endif
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};
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/* Altera SDRAM Memory Controller data */
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struct altr_sdram_mc_data {
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struct regmap *mc_vbase;
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int sb_irq;
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int db_irq;
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const struct altr_sdram_prv_data *data;
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};
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#endif /* #ifndef _ALTERA_EDAC_H */
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