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62cc67b9df
The current code soft-disables, and then goes to NAP mode which turns interrupts on. That means that if an interrupt occurs, we will hit the masked interrupt code path which isn't what we want, as it will return with EE off, which will either get us out of NAP mode, or fail to enter it (according to spec). Instead, let's just rely on the fact that it is safe to take decrementer interrupts on an offline CPU and leave interrupts enabled. We can also get rid of the special case in asm for power4_cpu_offline_powersave() and just use power4_idle(). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
56 lines
1.3 KiB
ArmAsm
56 lines
1.3 KiB
ArmAsm
/*
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* This file contains the power_save function for 970-family CPUs.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/threads.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#undef DEBUG
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.text
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_GLOBAL(power4_idle)
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BEGIN_FTR_SECTION
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blr
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END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)
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/* Now check if user or arch enabled NAP mode */
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LOAD_REG_ADDRBASE(r3,powersave_nap)
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lwz r4,ADDROFF(powersave_nap)(r3)
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cmpwi 0,r4,0
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beqlr
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/* Go to NAP now */
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mfmsr r7
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rldicl r0,r7,48,1
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rotldi r0,r0,16
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mtmsrd r0,1 /* hard-disable interrupts */
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li r0,1
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stb r0,PACASOFTIRQEN(r13) /* we'll hard-enable shortly */
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stb r0,PACAHARDIRQEN(r13)
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BEGIN_FTR_SECTION
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DSSALL
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sync
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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clrrdi r9,r1,THREAD_SHIFT /* current thread_info */
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ld r8,TI_LOCAL_FLAGS(r9) /* set napping bit */
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ori r8,r8,_TLF_NAPPING /* so when we take an exception */
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std r8,TI_LOCAL_FLAGS(r9) /* it will return to our caller */
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ori r7,r7,MSR_EE
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oris r7,r7,MSR_POW@h
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1: sync
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isync
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mtmsrd r7
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isync
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b 1b
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