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0403e38277
Some engines optimize operation by reading ahead in the descriptor chain such that descriptor2 may start execution before descriptor1 completes. If descriptor2 depends on the result from descriptor1 then a fence is required (on descriptor2) to disable this optimization. The async_tx api could implicitly identify dependencies via the 'depend_tx' parameter, but that would constrain cases where the dependency chain only specifies a completion order rather than a data dependency. So, provide an ASYNC_TX_FENCE to explicitly identify data dependencies. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
99 lines
2.9 KiB
C
99 lines
2.9 KiB
C
/*
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* copy offload engine support
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*
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* Copyright © 2006, Intel Corporation.
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*
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* Dan Williams <dan.j.williams@intel.com>
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*
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* with architecture considerations by:
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* Neil Brown <neilb@suse.de>
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* Jeff Garzik <jeff@garzik.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/highmem.h>
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#include <linux/mm.h>
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#include <linux/dma-mapping.h>
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#include <linux/async_tx.h>
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/**
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* async_memcpy - attempt to copy memory with a dma engine.
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* @dest: destination page
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* @src: src page
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* @dest_offset: offset into 'dest' to start transaction
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* @src_offset: offset into 'src' to start transaction
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* @len: length in bytes
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* @submit: submission / completion modifiers
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*
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* honored flags: ASYNC_TX_ACK
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*/
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struct dma_async_tx_descriptor *
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async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset,
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unsigned int src_offset, size_t len,
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struct async_submit_ctl *submit)
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{
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struct dma_chan *chan = async_tx_find_channel(submit, DMA_MEMCPY,
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&dest, 1, &src, 1, len);
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struct dma_device *device = chan ? chan->device : NULL;
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struct dma_async_tx_descriptor *tx = NULL;
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if (device) {
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dma_addr_t dma_dest, dma_src;
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unsigned long dma_prep_flags = 0;
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if (submit->cb_fn)
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dma_prep_flags |= DMA_PREP_INTERRUPT;
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if (submit->flags & ASYNC_TX_FENCE)
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dma_prep_flags |= DMA_PREP_FENCE;
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dma_dest = dma_map_page(device->dev, dest, dest_offset, len,
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DMA_FROM_DEVICE);
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dma_src = dma_map_page(device->dev, src, src_offset, len,
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DMA_TO_DEVICE);
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tx = device->device_prep_dma_memcpy(chan, dma_dest, dma_src,
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len, dma_prep_flags);
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}
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if (tx) {
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pr_debug("%s: (async) len: %zu\n", __func__, len);
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async_tx_submit(chan, tx, submit);
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} else {
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void *dest_buf, *src_buf;
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pr_debug("%s: (sync) len: %zu\n", __func__, len);
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/* wait for any prerequisite operations */
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async_tx_quiesce(&submit->depend_tx);
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dest_buf = kmap_atomic(dest, KM_USER0) + dest_offset;
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src_buf = kmap_atomic(src, KM_USER1) + src_offset;
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memcpy(dest_buf, src_buf, len);
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kunmap_atomic(dest_buf, KM_USER0);
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kunmap_atomic(src_buf, KM_USER1);
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async_tx_sync_epilog(submit);
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}
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return tx;
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}
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EXPORT_SYMBOL_GPL(async_memcpy);
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MODULE_AUTHOR("Intel Corporation");
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MODULE_DESCRIPTION("asynchronous memcpy api");
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MODULE_LICENSE("GPL");
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