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0311c76e47
The displayport-phy is fully enclosed in the general register files (GRF). Therefore as seen from the device-tree it shouldn't be a separate platform- device but instead a sub-device of the GRF - using the simply-mfd mechanism. The driver entered the kernel in the current merge-window, so we can still adapt the binding without needing a fallback, as the binding hasn't been released with a full kernel yet. While the edp phy is fully part of the GRF, it doesn't have any separate register set there, so doesn't get any register-area assigned. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
27 lines
666 B
Plaintext
27 lines
666 B
Plaintext
Rockchip specific extensions to the Analogix Display Port PHY
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Required properties:
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- compatible : should be one of the following supported values:
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- "rockchip.rk3288-dp-phy"
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- clocks: from common clock binding: handle to dp clock.
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of memory mapped region.
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- clock-names: from common clock binding:
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Required elements: "24m"
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- #phy-cells : from the generic PHY bindings, must be 0;
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Example:
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grf: syscon@ff770000 {
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compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
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...
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edp_phy: edp-phy {
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compatible = "rockchip,rk3288-dp-phy";
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clocks = <&cru SCLK_EDP_24M>;
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clock-names = "24m";
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#phy-cells = <0>;
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};
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};
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