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Signed-off-by: Anatol Pomozov <anatol.pomozov@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
257 lines
9.1 KiB
Plaintext
257 lines
9.1 KiB
Plaintext
==========================
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KERNEL ABIS FOR METAG ARCH
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==========================
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This document describes the Linux ABIs for the metag architecture, and has the
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following sections:
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(*) Outline of registers
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(*) Userland registers
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(*) Kernel registers
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(*) System call ABI
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(*) Calling conventions
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====================
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OUTLINE OF REGISTERS
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====================
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The main Meta core registers are arranged in units:
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UNIT Type DESCRIPTION GP EXT PRIV GLOBAL
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======= ======= =============== ======= ======= ======= =======
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CT Special Control unit
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D0 General Data unit 0 0-7 8-15 16-31 16-31
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D1 General Data unit 1 0-7 8-15 16-31 16-31
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A0 General Address unit 0 0-3 4-7 8-15 8-15
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A1 General Address unit 1 0-3 4-7 8-15 8-15
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PC Special PC unit 0 1
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PORT Special Ports
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TR Special Trigger unit 0-7
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TT Special Trace unit 0-5
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FX General FP unit 0-15
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GP registers form part of the main context.
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Extended context registers (EXT) may not be present on all hardware threads and
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can be context switched if support is enabled and the appropriate bits are set
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in e.g. the D0.8 register to indicate what extended state to preserve.
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Global registers are shared between threads and are privilege protected.
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See arch/metag/include/asm/metag_regs.h for definitions relating to core
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registers and the fields and bits they contain. See the TRMs for further details
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about special registers.
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Several special registers are preserved in the main context, these are the
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interesting ones:
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REG (ALIAS) PURPOSE
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======================= ===============================================
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CT.1 (TXMODE) Processor mode bits (particularly for DSP)
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CT.2 (TXSTATUS) Condition flags and LSM_STEP (MGET/MSET step)
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CT.3 (TXRPT) Branch repeat counter
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PC.0 (PC) Program counter
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Some of the general registers have special purposes in the ABI and therefore
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have aliases:
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D0 REG (ALIAS) PURPOSE D1 REG (ALIAS) PURPOSE
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=============== =============== =============== =======================
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D0.0 (D0Re0) 32bit result D1.0 (D1Re0) Top half of 64bit result
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D0.1 (D0Ar6) Argument 6 D1.1 (D1Ar5) Argument 5
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D0.2 (D0Ar4) Argument 4 D1.2 (D1Ar3) Argument 3
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D0.3 (D0Ar2) Argument 2 D1.3 (D1Ar1) Argument 1
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D0.4 (D0FrT) Frame temp D1.4 (D1RtP) Return pointer
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D0.5 Call preserved D1.5 Call preserved
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D0.6 Call preserved D1.6 Call preserved
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D0.7 Call preserved D1.7 Call preserved
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A0 REG (ALIAS) PURPOSE A1 REG (ALIAS) PURPOSE
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=============== =============== =============== =======================
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A0.0 (A0StP) Stack pointer A1.0 (A1GbP) Global base pointer
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A0.1 (A0FrP) Frame pointer A1.1 (A1LbP) Local base pointer
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A0.2 A1.2
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A0.3 A1.3
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==================
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USERLAND REGISTERS
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==================
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All the general purpose D0, D1, A0, A1 registers are preserved when entering the
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kernel (including asynchronous events such as interrupts and timer ticks) except
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the following which have special purposes in the ABI:
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REGISTERS WHEN STATUS PURPOSE
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=============== ======= =============== ===============================
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D0.8 DSP Preserved ECH, determines what extended
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DSP state to preserve.
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A0.0 (A0StP) ALWAYS Preserved Stack >= A0StP may be clobbered
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at any time by the creation of a
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signal frame.
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A1.0 (A1GbP) SMP Clobbered Used as temporary for loading
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kernel stack pointer and saving
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core context.
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A0.15 !SMP Protected Stores kernel stack pointer.
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A1.15 ALWAYS Protected Stores kernel base pointer.
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On UP A0.15 is used to store the kernel stack pointer for storing the userland
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context. A0.15 is global between hardware threads though which means it cannot
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be used on SMP for this purpose. Since no protected local registers are
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available A1GbP is reserved for use as a temporary to allow a percpu stack
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pointer to be loaded for storing the rest of the context.
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================
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KERNEL REGISTERS
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================
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When in the kernel the following registers have special purposes in the ABI:
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REGISTERS WHEN STATUS PURPOSE
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=============== ======= =============== ===============================
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A0.0 (A0StP) ALWAYS Preserved Stack >= A0StP may be clobbered
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at any time by the creation of
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an irq signal frame.
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A1.0 (A1GbP) ALWAYS Preserved Reserved (kernel base pointer).
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===============
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SYSTEM CALL ABI
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===============
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When a system call is made, the following registers are effective:
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REGISTERS CALL RETURN
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=============== ======================= ===============================
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D0.0 (D0Re0) Return value (or -errno)
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D1.0 (D1Re0) System call number Clobbered
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D0.1 (D0Ar6) Syscall arg #6 Preserved
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D1.1 (D1Ar5) Syscall arg #5 Preserved
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D0.2 (D0Ar4) Syscall arg #4 Preserved
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D1.2 (D1Ar3) Syscall arg #3 Preserved
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D0.3 (D0Ar2) Syscall arg #2 Preserved
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D1.3 (D1Ar1) Syscall arg #1 Preserved
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Due to the limited number of argument registers and some system calls with badly
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aligned 64-bit arguments, 64-bit values are always packed in consecutive
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arguments, even if this is contrary to the normal calling conventions (where the
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two halves would go in a matching pair of data registers).
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For example fadvise64_64 usually has the signature:
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long sys_fadvise64_64(i32 fd, i64 offs, i64 len, i32 advice);
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But for metag fadvise64_64 is wrapped so that the 64-bit arguments are packed:
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long sys_fadvise64_64_metag(i32 fd, i32 offs_lo,
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i32 offs_hi, i32 len_lo,
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i32 len_hi, i32 advice)
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So the arguments are packed in the registers like this:
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D0 REG (ALIAS) VALUE D1 REG (ALIAS) VALUE
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=============== =============== =============== =======================
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D0.1 (D0Ar6) advice D1.1 (D1Ar5) hi(len)
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D0.2 (D0Ar4) lo(len) D1.2 (D1Ar3) hi(offs)
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D0.3 (D0Ar2) lo(offs) D1.3 (D1Ar1) fd
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===================
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CALLING CONVENTIONS
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===================
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These calling conventions apply to both user and kernel code. The stack grows
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from low addresses to high addresses in the metag ABI. The stack pointer (A0StP)
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should always point to the next free address on the stack and should at all
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times be 64-bit aligned. The following registers are effective at the point of a
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call:
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REGISTERS CALL RETURN
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=============== ======================= ===============================
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D0.0 (D0Re0) 32bit return value
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D1.0 (D1Re0) Upper half of 64bit return value
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D0.1 (D0Ar6) 32bit argument #6 Clobbered
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D1.1 (D1Ar5) 32bit argument #5 Clobbered
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D0.2 (D0Ar4) 32bit argument #4 Clobbered
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D1.2 (D1Ar3) 32bit argument #3 Clobbered
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D0.3 (D0Ar2) 32bit argument #2 Clobbered
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D1.3 (D1Ar1) 32bit argument #1 Clobbered
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D0.4 (D0FrT) Clobbered
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D1.4 (D1RtP) Return pointer Clobbered
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D{0-1}.{5-7} Preserved
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A0.0 (A0StP) Stack pointer Preserved
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A1.0 (A0GbP) Preserved
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A0.1 (A0FrP) Frame pointer Preserved
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A1.1 (A0LbP) Preserved
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A{0-1},{2-3} Clobbered
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64-bit arguments are placed in matching pairs of registers (i.e. the same
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register number in both D0 and D1 units), with the least significant half in D0
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and the most significant half in D1, leaving a gap where necessary. Further
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arguments are stored on the stack in reverse order (earlier arguments at higher
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addresses):
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ADDRESS 0 1 2 3 4 5 6 7
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=============== ===== ===== ===== ===== ===== ===== ===== =====
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A0StP -->
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A0StP-0x08 32bit argument #8 32bit argument #7
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A0StP-0x10 32bit argument #10 32bit argument #9
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Function prologues tend to look a bit like this:
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/* If frame pointer in use, move it to frame temp register so it can be
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easily pushed onto stack */
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MOV D0FrT,A0FrP
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/* If frame pointer in use, set it to stack pointer */
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ADD A0FrP,A0StP,#0
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/* Preserve D0FrT, D1RtP, D{0-1}.{5-7} on stack, incrementing A0StP */
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MSETL [A0StP++],D0FrT,D0.5,D0.6,D0.7
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/* Allocate some stack space for local variables */
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ADD A0StP,A0StP,#0x10
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At this point the stack would look like this:
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ADDRESS 0 1 2 3 4 5 6 7
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=============== ===== ===== ===== ===== ===== ===== ===== =====
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A0StP -->
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A0StP-0x08
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A0StP-0x10
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A0StP-0x18 Old D0.7 Old D1.7
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A0StP-0x20 Old D0.6 Old D1.6
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A0StP-0x28 Old D0.5 Old D1.5
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A0FrP --> Old A0FrP (frame ptr) Old D1RtP (return ptr)
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A0FrP-0x08 32bit argument #8 32bit argument #7
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A0FrP-0x10 32bit argument #10 32bit argument #9
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Function epilogues tend to differ depending on the use of a frame pointer. An
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example of a frame pointer epilogue:
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/* Restore D0FrT, D1RtP, D{0-1}.{5-7} from stack, incrementing A0FrP */
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MGETL D0FrT,D0.5,D0.6,D0.7,[A0FrP++]
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/* Restore stack pointer to where frame pointer was before increment */
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SUB A0StP,A0FrP,#0x20
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/* Restore frame pointer from frame temp */
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MOV A0FrP,D0FrT
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/* Return to caller via restored return pointer */
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MOV PC,D1RtP
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If the function hasn't touched the frame pointer, MGETL cannot be safely used
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with A0StP as it always increments and that would expose the stack to clobbering
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by interrupts (kernel) or signals (user). Therefore it's common to see the MGETL
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split into separate GETL instructions:
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/* Restore D0FrT, D1RtP, D{0-1}.{5-7} from stack */
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GETL D0FrT,D1RtP,[A0StP+#-0x30]
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GETL D0.5,D1.5,[A0StP+#-0x28]
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GETL D0.6,D1.6,[A0StP+#-0x20]
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GETL D0.7,D1.7,[A0StP+#-0x18]
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/* Restore stack pointer */
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SUB A0StP,A0StP,#0x30
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/* Return to caller via restored return pointer */
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MOV PC,D1RtP
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