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On some Qualcomm Technologies Inc. SoCs like SC7180, there exists a hardware errata where the APSS (Application Processor SubSystem)/CPU watchdog counter is stopped when the trace unit power up ETM register is set (TRCPDCR.PU = 1). Since the ETMs share the same power domain as that of respective CPU cores, they are powered on when the CPU core is powered on. So we can skip powering up of trace unit after checking for this errata via new property called "qcom,skip-power-up". Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org> Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20200716175746.3338735-4-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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| .. | ||
| coresight-catu.c | ||
| coresight-catu.h | ||
| coresight-cpu-debug.c | ||
| coresight-cti-platform.c | ||
| coresight-cti-sysfs.c | ||
| coresight-cti.c | ||
| coresight-cti.h | ||
| coresight-etb10.c | ||
| coresight-etm3x-sysfs.c | ||
| coresight-etm3x.c | ||
| coresight-etm4x-sysfs.c | ||
| coresight-etm4x.c | ||
| coresight-etm4x.h | ||
| coresight-etm-cp14.c | ||
| coresight-etm-perf.c | ||
| coresight-etm-perf.h | ||
| coresight-etm.h | ||
| coresight-funnel.c | ||
| coresight-platform.c | ||
| coresight-priv.h | ||
| coresight-replicator.c | ||
| coresight-stm.c | ||
| coresight-sysfs.c | ||
| coresight-tmc-etf.c | ||
| coresight-tmc-etr.c | ||
| coresight-tmc.c | ||
| coresight-tmc.h | ||
| coresight-tpiu.c | ||
| coresight.c | ||
| Kconfig | ||
| Makefile | ||