mirror of
https://github.com/edk2-porting/linux-next.git
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41a524abff
This adds dpm support for KB/KV asics. This includes: - dynamic engine clock scaling - dynamic voltage scaling - power containment - shader power scaling Set radeon.dpm=1 to enable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
301 lines
8.7 KiB
C
301 lines
8.7 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU7_FUSION_H
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#define SMU7_FUSION_H
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#include "smu7.h"
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#pragma pack(push, 1)
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#define SMU7_DTE_ITERATIONS 5
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#define SMU7_DTE_SOURCES 5
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#define SMU7_DTE_SINKS 3
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#define SMU7_NUM_CPU_TES 2
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#define SMU7_NUM_GPU_TES 1
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#define SMU7_NUM_NON_TES 2
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// All 'soft registers' should be uint32_t.
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struct SMU7_SoftRegisters
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{
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uint32_t RefClockFrequency;
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uint32_t PmTimerP;
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uint32_t FeatureEnables;
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uint32_t HandshakeDisables;
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uint8_t DisplayPhy1Config;
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uint8_t DisplayPhy2Config;
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uint8_t DisplayPhy3Config;
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uint8_t DisplayPhy4Config;
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uint8_t DisplayPhy5Config;
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uint8_t DisplayPhy6Config;
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uint8_t DisplayPhy7Config;
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uint8_t DisplayPhy8Config;
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uint32_t AverageGraphicsA;
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uint32_t AverageMemoryA;
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uint32_t AverageGioA;
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uint8_t SClkDpmEnabledLevels;
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uint8_t MClkDpmEnabledLevels;
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uint8_t LClkDpmEnabledLevels;
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uint8_t PCIeDpmEnabledLevels;
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uint8_t UVDDpmEnabledLevels;
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uint8_t SAMUDpmEnabledLevels;
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uint8_t ACPDpmEnabledLevels;
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uint8_t VCEDpmEnabledLevels;
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uint32_t DRAM_LOG_ADDR_H;
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uint32_t DRAM_LOG_ADDR_L;
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uint32_t DRAM_LOG_PHY_ADDR_H;
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uint32_t DRAM_LOG_PHY_ADDR_L;
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uint32_t DRAM_LOG_BUFF_SIZE;
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uint32_t UlvEnterC;
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uint32_t UlvTime;
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uint32_t Reserved[3];
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};
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typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
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struct SMU7_Fusion_GraphicsLevel
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{
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uint32_t MinVddNb;
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uint32_t SclkFrequency;
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uint8_t Vid;
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uint8_t VidOffset;
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uint16_t AT;
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uint8_t PowerThrottle;
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uint8_t GnbSlow;
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uint8_t ForceNbPs1;
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uint8_t SclkDid;
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uint8_t DisplayWatermark;
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uint8_t EnabledForActivity;
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uint8_t EnabledForThrottle;
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uint8_t UpH;
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uint8_t DownH;
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uint8_t VoltageDownH;
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uint8_t DeepSleepDivId;
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uint8_t ClkBypassCntl;
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uint32_t reserved;
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};
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typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel;
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struct SMU7_Fusion_GIOLevel
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{
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uint8_t EnabledForActivity;
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uint8_t LclkDid;
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uint8_t Vid;
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uint8_t VoltageDownH;
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uint32_t MinVddNb;
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uint16_t ResidencyCounter;
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uint8_t UpH;
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uint8_t DownH;
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uint32_t LclkFrequency;
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uint8_t ActivityLevel;
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uint8_t EnabledForThrottle;
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uint8_t ClkBypassCntl;
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uint8_t padding;
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};
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typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel;
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// UVD VCLK/DCLK state (level) definition.
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struct SMU7_Fusion_UvdLevel
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{
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uint32_t VclkFrequency;
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uint32_t DclkFrequency;
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uint16_t MinVddNb;
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uint8_t VclkDivider;
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uint8_t DclkDivider;
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uint8_t VClkBypassCntl;
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uint8_t DClkBypassCntl;
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uint8_t padding[2];
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};
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typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel;
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// Clocks for other external blocks (VCE, ACP, SAMU).
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struct SMU7_Fusion_ExtClkLevel
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{
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uint32_t Frequency;
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uint16_t MinVoltage;
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uint8_t Divider;
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uint8_t ClkBypassCntl;
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uint32_t Reserved;
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};
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typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel;
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struct SMU7_Fusion_ACPILevel
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{
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uint32_t Flags;
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uint32_t MinVddNb;
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uint32_t SclkFrequency;
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uint8_t SclkDid;
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uint8_t GnbSlow;
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uint8_t ForceNbPs1;
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uint8_t DisplayWatermark;
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uint8_t DeepSleepDivId;
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uint8_t padding[3];
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};
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typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel;
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struct SMU7_Fusion_NbDpm
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{
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uint8_t DpmXNbPsHi;
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uint8_t DpmXNbPsLo;
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uint8_t Dpm0PgNbPsHi;
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uint8_t Dpm0PgNbPsLo;
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uint8_t EnablePsi1;
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uint8_t SkipDPM0;
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uint8_t SkipPG;
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uint8_t Hysteresis;
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uint8_t EnableDpmPstatePoll;
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uint8_t padding[3];
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};
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typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm;
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struct SMU7_Fusion_StateInfo
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{
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uint32_t SclkFrequency;
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uint32_t LclkFrequency;
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uint32_t VclkFrequency;
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uint32_t DclkFrequency;
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uint32_t SamclkFrequency;
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uint32_t AclkFrequency;
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uint32_t EclkFrequency;
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uint8_t DisplayWatermark;
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uint8_t McArbIndex;
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int8_t SclkIndex;
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int8_t MclkIndex;
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};
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typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo;
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struct SMU7_Fusion_DpmTable
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{
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uint32_t SystemFlags;
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SMU7_PIDController GraphicsPIDController;
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SMU7_PIDController GioPIDController;
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uint8_t GraphicsDpmLevelCount;
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uint8_t GIOLevelCount;
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uint8_t UvdLevelCount;
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uint8_t VceLevelCount;
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uint8_t AcpLevelCount;
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uint8_t SamuLevelCount;
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uint16_t FpsHighT;
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SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE];
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SMU7_Fusion_ACPILevel ACPILevel;
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SMU7_Fusion_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD];
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SMU7_Fusion_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE];
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SMU7_Fusion_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP];
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SMU7_Fusion_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU];
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uint8_t UvdBootLevel;
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uint8_t VceBootLevel;
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uint8_t AcpBootLevel;
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uint8_t SamuBootLevel;
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uint8_t UVDInterval;
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uint8_t VCEInterval;
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uint8_t ACPInterval;
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uint8_t SAMUInterval;
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uint8_t GraphicsBootLevel;
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uint8_t GraphicsInterval;
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uint8_t GraphicsThermThrottleEnable;
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uint8_t GraphicsVoltageChangeEnable;
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uint8_t GraphicsClkSlowEnable;
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uint8_t GraphicsClkSlowDivider;
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uint16_t FpsLowT;
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uint32_t DisplayCac;
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uint32_t LowSclkInterruptT;
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uint32_t DRAM_LOG_ADDR_H;
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uint32_t DRAM_LOG_ADDR_L;
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uint32_t DRAM_LOG_PHY_ADDR_H;
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uint32_t DRAM_LOG_PHY_ADDR_L;
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uint32_t DRAM_LOG_BUFF_SIZE;
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};
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struct SMU7_Fusion_GIODpmTable
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{
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SMU7_Fusion_GIOLevel GIOLevel [SMU7_MAX_LEVELS_GIO];
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SMU7_PIDController GioPIDController;
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uint32_t GIOLevelCount;
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uint8_t Enable;
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uint8_t GIOVoltageChangeEnable;
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uint8_t GIOBootLevel;
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uint8_t padding;
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uint8_t padding1[2];
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uint8_t TargetState;
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uint8_t CurrenttState;
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uint8_t ThrottleOnHtc;
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uint8_t ThermThrottleStatus;
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uint8_t ThermThrottleTempSelect;
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uint8_t ThermThrottleEnable;
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uint16_t TemperatureLimitHigh;
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uint16_t TemperatureLimitLow;
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};
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typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable;
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typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable;
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#pragma pack(pop)
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#endif
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