mirror of
https://github.com/edk2-porting/linux-next.git
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66229b2005
This adds dpm support for rv7xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: reduce stack usage v3: fix 64 bit div v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
509 lines
16 KiB
C
509 lines
16 KiB
C
/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include "drmP.h"
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#include "radeon.h"
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#include "rv730d.h"
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#include "r600_dpm.h"
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#include "rv770_dpm.h"
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#include "atom.h"
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#define MC_CG_ARB_FREQ_F0 0x0a
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#define MC_CG_ARB_FREQ_F1 0x0b
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#define MC_CG_ARB_FREQ_F2 0x0c
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#define MC_CG_ARB_FREQ_F3 0x0d
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struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
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struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
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int rv730_populate_sclk_value(struct radeon_device *rdev,
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u32 engine_clock,
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RV770_SMC_SCLK_VALUE *sclk)
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{
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struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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struct atom_clock_dividers dividers;
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u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
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u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
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u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
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u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum;
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u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2;
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u64 tmp;
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u32 reference_clock = rdev->clock.spll.reference_freq;
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u32 reference_divider, post_divider;
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u32 fbdiv;
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int ret;
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ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
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engine_clock, false, ÷rs);
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if (ret)
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return ret;
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reference_divider = 1 + dividers.ref_div;
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if (dividers.enable_post_div)
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post_divider = ((dividers.post_div >> 4) & 0xf) +
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(dividers.post_div & 0xf) + 2;
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else
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post_divider = 1;
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tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
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do_div(tmp, reference_clock);
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fbdiv = (u32) tmp;
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/* set up registers */
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if (dividers.enable_post_div)
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spll_func_cntl |= SPLL_DIVEN;
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else
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spll_func_cntl &= ~SPLL_DIVEN;
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spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK);
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spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
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spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
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spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);
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spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
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spll_func_cntl_2 |= SCLK_MUX_SEL(2);
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spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
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spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
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spll_func_cntl_3 |= SPLL_DITHEN;
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if (pi->sclk_ss) {
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struct radeon_atom_ss ss;
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u32 vco_freq = engine_clock * post_divider;
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if (radeon_atombios_get_asic_ss_info(rdev, &ss,
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ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
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u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
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u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
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cg_spll_spread_spectrum &= ~CLK_S_MASK;
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cg_spll_spread_spectrum |= CLK_S(clk_s);
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cg_spll_spread_spectrum |= SSEN;
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cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
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cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
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}
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}
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sclk->sclk_value = cpu_to_be32(engine_clock);
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sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
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sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
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sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
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sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum);
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sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2);
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return 0;
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}
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int rv730_populate_mclk_value(struct radeon_device *rdev,
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u32 engine_clock, u32 memory_clock,
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LPRV7XX_SMC_MCLK_VALUE mclk)
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{
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struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl;
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u32 dll_cntl = pi->clk_regs.rv730.dll_cntl;
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u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;
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u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;
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u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;
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u32 mpll_ss = pi->clk_regs.rv730.mpll_ss;
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u32 mpll_ss2 = pi->clk_regs.rv730.mpll_ss2;
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struct atom_clock_dividers dividers;
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u32 post_divider, reference_divider;
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int ret;
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ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
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memory_clock, false, ÷rs);
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if (ret)
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return ret;
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reference_divider = dividers.ref_div + 1;
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if (dividers.enable_post_div)
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post_divider = ((dividers.post_div >> 4) & 0xf) +
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(dividers.post_div & 0xf) + 2;
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else
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post_divider = 1;
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/* setup the registers */
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if (dividers.enable_post_div)
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mpll_func_cntl |= MPLL_DIVEN;
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else
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mpll_func_cntl &= ~MPLL_DIVEN;
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mpll_func_cntl &= ~(MPLL_REF_DIV_MASK | MPLL_HILEN_MASK | MPLL_LOLEN_MASK);
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mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div);
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mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf);
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mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf);
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mpll_func_cntl_3 &= ~MPLL_FB_DIV_MASK;
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mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div);
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if (dividers.enable_dithen)
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mpll_func_cntl_3 |= MPLL_DITHEN;
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else
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mpll_func_cntl_3 &= ~MPLL_DITHEN;
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if (pi->mclk_ss) {
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struct radeon_atom_ss ss;
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u32 vco_freq = memory_clock * post_divider;
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if (radeon_atombios_get_asic_ss_info(rdev, &ss,
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ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
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u32 reference_clock = rdev->clock.mpll.reference_freq;
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u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
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u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000);
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mpll_ss &= ~CLK_S_MASK;
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mpll_ss |= CLK_S(clk_s);
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mpll_ss |= SSEN;
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mpll_ss2 &= ~CLK_V_MASK;
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mpll_ss |= CLK_V(clk_v);
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}
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}
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mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
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mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
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mclk->mclk730.mclk_value = cpu_to_be32(memory_clock);
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mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
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mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
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mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
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mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss);
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mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
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return 0;
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}
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void rv730_read_clock_registers(struct radeon_device *rdev)
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{
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struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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pi->clk_regs.rv730.cg_spll_func_cntl =
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RREG32(CG_SPLL_FUNC_CNTL);
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pi->clk_regs.rv730.cg_spll_func_cntl_2 =
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RREG32(CG_SPLL_FUNC_CNTL_2);
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pi->clk_regs.rv730.cg_spll_func_cntl_3 =
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RREG32(CG_SPLL_FUNC_CNTL_3);
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pi->clk_regs.rv730.cg_spll_spread_spectrum =
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RREG32(CG_SPLL_SPREAD_SPECTRUM);
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pi->clk_regs.rv730.cg_spll_spread_spectrum_2 =
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RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
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pi->clk_regs.rv730.mclk_pwrmgt_cntl =
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RREG32(TCI_MCLK_PWRMGT_CNTL);
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pi->clk_regs.rv730.dll_cntl =
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RREG32(TCI_DLL_CNTL);
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pi->clk_regs.rv730.mpll_func_cntl =
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RREG32(CG_MPLL_FUNC_CNTL);
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pi->clk_regs.rv730.mpll_func_cntl2 =
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RREG32(CG_MPLL_FUNC_CNTL_2);
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pi->clk_regs.rv730.mpll_func_cntl3 =
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RREG32(CG_MPLL_FUNC_CNTL_3);
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pi->clk_regs.rv730.mpll_ss =
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RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM);
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pi->clk_regs.rv730.mpll_ss2 =
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RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2);
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}
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int rv730_populate_smc_acpi_state(struct radeon_device *rdev,
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RV770_SMC_STATETABLE *table)
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{
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struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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u32 mpll_func_cntl = 0;
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u32 mpll_func_cntl_2 = 0 ;
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u32 mpll_func_cntl_3 = 0;
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u32 mclk_pwrmgt_cntl;
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u32 dll_cntl;
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u32 spll_func_cntl;
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u32 spll_func_cntl_2;
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u32 spll_func_cntl_3;
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table->ACPIState = table->initialState;
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table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
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if (pi->acpi_vddc) {
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rv770_populate_vddc_value(rdev, pi->acpi_vddc,
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&table->ACPIState.levels[0].vddc);
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table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ?
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pi->acpi_pcie_gen2 : 0;
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table->ACPIState.levels[0].gen2XSP =
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pi->acpi_pcie_gen2;
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} else {
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rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,
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&table->ACPIState.levels[0].vddc);
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table->ACPIState.levels[0].gen2PCIE = 0;
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}
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mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;
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mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;
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mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;
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mpll_func_cntl |= MPLL_RESET | MPLL_BYPASS_EN;
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mpll_func_cntl &= ~MPLL_SLEEP;
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mpll_func_cntl_2 &= ~MCLK_MUX_SEL_MASK;
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mpll_func_cntl_2 |= MCLK_MUX_SEL(1);
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mclk_pwrmgt_cntl = (MRDCKA_RESET |
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MRDCKB_RESET |
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MRDCKC_RESET |
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MRDCKD_RESET |
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MRDCKE_RESET |
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MRDCKF_RESET |
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MRDCKG_RESET |
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MRDCKH_RESET |
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MRDCKA_SLEEP |
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MRDCKB_SLEEP |
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MRDCKC_SLEEP |
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MRDCKD_SLEEP |
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MRDCKE_SLEEP |
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MRDCKF_SLEEP |
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MRDCKG_SLEEP |
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MRDCKH_SLEEP);
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dll_cntl = 0xff000000;
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spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
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spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
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spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
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spll_func_cntl |= SPLL_RESET | SPLL_BYPASS_EN;
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spll_func_cntl &= ~SPLL_SLEEP;
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spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
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spll_func_cntl_2 |= SCLK_MUX_SEL(4);
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table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
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table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
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table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
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table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
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table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
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table->ACPIState.levels[0].mclk.mclk730.mclk_value = 0;
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table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
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table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
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table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
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table->ACPIState.levels[0].sclk.sclk_value = 0;
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rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
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table->ACPIState.levels[1] = table->ACPIState.levels[0];
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table->ACPIState.levels[2] = table->ACPIState.levels[0];
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return 0;
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}
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int rv730_populate_smc_initial_state(struct radeon_device *rdev,
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struct radeon_ps *radeon_state,
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RV770_SMC_STATETABLE *table)
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{
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struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state);
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struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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u32 a_t;
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table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL =
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cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl);
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table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 =
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cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl2);
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table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 =
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cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl3);
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table->initialState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL =
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cpu_to_be32(pi->clk_regs.rv730.mclk_pwrmgt_cntl);
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table->initialState.levels[0].mclk.mclk730.vDLL_CNTL =
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cpu_to_be32(pi->clk_regs.rv730.dll_cntl);
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table->initialState.levels[0].mclk.mclk730.vMPLL_SS =
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cpu_to_be32(pi->clk_regs.rv730.mpll_ss);
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table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 =
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cpu_to_be32(pi->clk_regs.rv730.mpll_ss2);
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table->initialState.levels[0].mclk.mclk730.mclk_value =
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cpu_to_be32(initial_state->low.mclk);
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table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
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cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl);
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table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
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cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_2);
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table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
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cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_3);
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table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
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cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum);
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table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
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cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum_2);
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table->initialState.levels[0].sclk.sclk_value =
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cpu_to_be32(initial_state->low.sclk);
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table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
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table->initialState.levels[0].seqValue =
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rv770_get_seq_value(rdev, &initial_state->low);
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rv770_populate_vddc_value(rdev,
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initial_state->low.vddc,
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&table->initialState.levels[0].vddc);
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rv770_populate_initial_mvdd_value(rdev,
|
|
&table->initialState.levels[0].mvdd);
|
|
|
|
a_t = CG_R(0xffff) | CG_L(0);
|
|
|
|
table->initialState.levels[0].aT = cpu_to_be32(a_t);
|
|
|
|
table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
|
|
|
|
if (pi->boot_in_gen2)
|
|
table->initialState.levels[0].gen2PCIE = 1;
|
|
else
|
|
table->initialState.levels[0].gen2PCIE = 0;
|
|
if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
|
|
table->initialState.levels[0].gen2XSP = 1;
|
|
else
|
|
table->initialState.levels[0].gen2XSP = 0;
|
|
|
|
table->initialState.levels[1] = table->initialState.levels[0];
|
|
table->initialState.levels[2] = table->initialState.levels[0];
|
|
|
|
table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void rv730_program_memory_timing_parameters(struct radeon_device *rdev,
|
|
struct radeon_ps *radeon_state)
|
|
{
|
|
struct rv7xx_ps *state = rv770_get_ps(radeon_state);
|
|
u32 arb_refresh_rate = 0;
|
|
u32 dram_timing = 0;
|
|
u32 dram_timing2 = 0;
|
|
u32 old_dram_timing = 0;
|
|
u32 old_dram_timing2 = 0;
|
|
|
|
arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) &
|
|
~(POWERMODE1_MASK | POWERMODE2_MASK | POWERMODE3_MASK);
|
|
arb_refresh_rate |=
|
|
(POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) |
|
|
POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) |
|
|
POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk)));
|
|
WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate);
|
|
|
|
/* save the boot dram timings */
|
|
old_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
|
|
old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
|
|
|
|
radeon_atom_set_engine_dram_timings(rdev,
|
|
state->high.sclk,
|
|
state->high.mclk);
|
|
|
|
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
|
|
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
|
|
|
|
WREG32(MC_ARB_DRAM_TIMING_3, dram_timing);
|
|
WREG32(MC_ARB_DRAM_TIMING2_3, dram_timing2);
|
|
|
|
radeon_atom_set_engine_dram_timings(rdev,
|
|
state->medium.sclk,
|
|
state->medium.mclk);
|
|
|
|
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
|
|
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
|
|
|
|
WREG32(MC_ARB_DRAM_TIMING_2, dram_timing);
|
|
WREG32(MC_ARB_DRAM_TIMING2_2, dram_timing2);
|
|
|
|
radeon_atom_set_engine_dram_timings(rdev,
|
|
state->low.sclk,
|
|
state->low.mclk);
|
|
|
|
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
|
|
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
|
|
|
|
WREG32(MC_ARB_DRAM_TIMING_1, dram_timing);
|
|
WREG32(MC_ARB_DRAM_TIMING2_1, dram_timing2);
|
|
|
|
/* restore the boot dram timings */
|
|
WREG32(MC_ARB_DRAM_TIMING, old_dram_timing);
|
|
WREG32(MC_ARB_DRAM_TIMING2, old_dram_timing2);
|
|
|
|
}
|
|
|
|
void rv730_start_dpm(struct radeon_device *rdev)
|
|
{
|
|
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
|
|
|
|
WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
|
|
|
|
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
|
|
}
|
|
|
|
void rv730_stop_dpm(struct radeon_device *rdev)
|
|
{
|
|
PPSMC_Result result;
|
|
|
|
result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
|
|
|
|
if (result != PPSMC_Result_OK)
|
|
DRM_ERROR("Could not force DPM to low\n");
|
|
|
|
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
|
|
|
|
WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
|
|
|
|
WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
|
|
}
|
|
|
|
void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt)
|
|
{
|
|
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
|
|
u32 i = use_dcodt ? 0 : 1;
|
|
u32 mc4_io_pad_cntl;
|
|
|
|
mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
|
|
mc4_io_pad_cntl &= 0xFFFFFF00;
|
|
mc4_io_pad_cntl |= pi->odt_value_0[i];
|
|
WREG32(MC4_IO_DQ_PAD_CNTL_D0_I0, mc4_io_pad_cntl);
|
|
WREG32(MC4_IO_DQ_PAD_CNTL_D0_I1, mc4_io_pad_cntl);
|
|
|
|
mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
|
|
mc4_io_pad_cntl &= 0xFFFFFF00;
|
|
mc4_io_pad_cntl |= pi->odt_value_1[i];
|
|
WREG32(MC4_IO_QS_PAD_CNTL_D0_I0, mc4_io_pad_cntl);
|
|
WREG32(MC4_IO_QS_PAD_CNTL_D0_I1, mc4_io_pad_cntl);
|
|
}
|
|
|
|
void rv730_get_odt_values(struct radeon_device *rdev)
|
|
{
|
|
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
|
|
u32 mc4_io_pad_cntl;
|
|
|
|
pi->odt_value_0[0] = (u8)0;
|
|
pi->odt_value_1[0] = (u8)0x80;
|
|
|
|
mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
|
|
pi->odt_value_0[1] = (u8)(mc4_io_pad_cntl & 0xff);
|
|
|
|
mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
|
|
pi->odt_value_1[1] = (u8)(mc4_io_pad_cntl & 0xff);
|
|
}
|