mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-16 09:13:55 +08:00
021f653791
The Generic Interrupt Controller (version 3) offers services that are similar to GICv2, with a number of additional features: - Affinity routing based on the CPU MPIDR (ARE) - System register for the CPU interfaces (SRE) - Support for more that 8 CPUs - Locality-specific Peripheral Interrupts (LPIs) - Interrupt Translation Services (ITS) This patch adds preliminary support for GICv3 with ARE and SRE, non-secure mode only. It relies on higher exception levels to grant ARE and SRE access. Support for LPI and ITS will be added at a later time. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Zi Shen Lim <zlim@broadcom.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Tirumalesh Chalamarla <tchalamarla@cavium.com> Reviewed-by: Yun Wu <wuyun.wu@huawei.com> Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com> Tested-by: Tirumalesh Chalamarla<tchalamarla@cavium.com> Tested-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Acked-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lkml.kernel.org/r/1404140510-5382-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
34 lines
1.4 KiB
Makefile
34 lines
1.4 KiB
Makefile
obj-$(CONFIG_IRQCHIP) += irqchip.o
|
|
|
|
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
|
|
obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
|
|
obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
|
|
obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
|
|
obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
|
|
obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
|
|
obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
|
|
obj-$(CONFIG_METAG) += irq-metag-ext.o
|
|
obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
|
|
obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o
|
|
obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
|
|
obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
|
|
obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
|
|
obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
|
|
obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
|
|
obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
|
|
obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
|
|
obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
|
|
obj-$(CONFIG_ARM_VIC) += irq-vic.o
|
|
obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o
|
|
obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
|
|
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
|
|
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
|
|
obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
|
|
obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o
|
|
obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o
|
|
obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
|
|
obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
|
|
obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
|
|
obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
|
|
obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
|