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019b17b3ff
At the moment everything assumes a full linear mapping of the various exception stacks. Adding guard pages to the cpu entry area mapping of the exception stacks will break that assumption. As a preparatory step convert both the real storage and the effective mapping in the cpu entry area from character arrays to structures. To ensure that both arrays have the same ordering and the same size of the individual stacks fill the members with a macro. The guard size is the only difference between the two resulting structures. For now both have guard size 0 until the preparation of all usage sites is done. Provide a couple of helper macros which are used in the following conversions. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Sean Christopherson <sean.j.christopherson@intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: "Chang S. Bae" <chang.seok.bae@intel.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Dominik Brodowski <linux@dominikbrodowski.net> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: x86-ml <x86@kernel.org> Link: https://lkml.kernel.org/r/20190414160144.506807893@linutronix.de
122 lines
3.3 KiB
C
122 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef _ASM_X86_CPU_ENTRY_AREA_H
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#define _ASM_X86_CPU_ENTRY_AREA_H
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#include <linux/percpu-defs.h>
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#include <asm/processor.h>
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#include <asm/intel_ds.h>
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#ifdef CONFIG_X86_64
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/* Macro to enforce the same ordering and stack sizes */
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#define ESTACKS_MEMBERS(guardsize) \
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char DF_stack_guard[guardsize]; \
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char DF_stack[EXCEPTION_STKSZ]; \
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char NMI_stack_guard[guardsize]; \
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char NMI_stack[EXCEPTION_STKSZ]; \
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char DB_stack_guard[guardsize]; \
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char DB_stack[DEBUG_STKSZ]; \
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char MCE_stack_guard[guardsize]; \
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char MCE_stack[EXCEPTION_STKSZ]; \
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char IST_top_guard[guardsize]; \
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/* The exception stacks' physical storage. No guard pages required */
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struct exception_stacks {
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ESTACKS_MEMBERS(0)
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};
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/*
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* The effective cpu entry area mapping with guard pages. Guard size is
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* zero until the code which makes assumptions about linear mappings is
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* cleaned up.
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*/
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struct cea_exception_stacks {
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ESTACKS_MEMBERS(0)
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};
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#define CEA_ESTACK_SIZE(st) \
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sizeof(((struct cea_exception_stacks *)0)->st## _stack)
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#define CEA_ESTACK_BOT(ceastp, st) \
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((unsigned long)&(ceastp)->st## _stack)
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#define CEA_ESTACK_TOP(ceastp, st) \
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(CEA_ESTACK_BOT(ceastp, st) + CEA_ESTACK_SIZE(st))
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#define CEA_ESTACK_OFFS(st) \
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offsetof(struct cea_exception_stacks, st## _stack)
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#define CEA_ESTACK_PAGES \
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(sizeof(struct cea_exception_stacks) / PAGE_SIZE)
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#endif
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/*
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* cpu_entry_area is a percpu region that contains things needed by the CPU
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* and early entry/exit code. Real types aren't used for all fields here
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* to avoid circular header dependencies.
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*
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* Every field is a virtual alias of some other allocated backing store.
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* There is no direct allocation of a struct cpu_entry_area.
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*/
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struct cpu_entry_area {
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char gdt[PAGE_SIZE];
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/*
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* The GDT is just below entry_stack and thus serves (on x86_64) as
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* a a read-only guard page.
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*/
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struct entry_stack_page entry_stack_page;
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/*
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* On x86_64, the TSS is mapped RO. On x86_32, it's mapped RW because
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* we need task switches to work, and task switches write to the TSS.
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*/
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struct tss_struct tss;
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#ifdef CONFIG_X86_64
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/*
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* Exception stacks used for IST entries with guard pages.
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*/
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struct cea_exception_stacks estacks;
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#endif
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#ifdef CONFIG_CPU_SUP_INTEL
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/*
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* Per CPU debug store for Intel performance monitoring. Wastes a
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* full page at the moment.
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*/
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struct debug_store cpu_debug_store;
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/*
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* The actual PEBS/BTS buffers must be mapped to user space
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* Reserve enough fixmap PTEs.
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*/
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struct debug_store_buffers cpu_debug_buffers;
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#endif
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};
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#define CPU_ENTRY_AREA_SIZE (sizeof(struct cpu_entry_area))
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#define CPU_ENTRY_AREA_TOT_SIZE (CPU_ENTRY_AREA_SIZE * NR_CPUS)
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DECLARE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
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extern void setup_cpu_entry_areas(void);
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extern void cea_set_pte(void *cea_vaddr, phys_addr_t pa, pgprot_t flags);
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#define CPU_ENTRY_AREA_RO_IDT CPU_ENTRY_AREA_BASE
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#define CPU_ENTRY_AREA_PER_CPU (CPU_ENTRY_AREA_RO_IDT + PAGE_SIZE)
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#define CPU_ENTRY_AREA_RO_IDT_VADDR ((void *)CPU_ENTRY_AREA_RO_IDT)
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#define CPU_ENTRY_AREA_MAP_SIZE \
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(CPU_ENTRY_AREA_PER_CPU + CPU_ENTRY_AREA_TOT_SIZE - CPU_ENTRY_AREA_BASE)
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extern struct cpu_entry_area *get_cpu_entry_area(int cpu);
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static inline struct entry_stack *cpu_entry_stack(int cpu)
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{
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return &get_cpu_entry_area(cpu)->entry_stack_page.stack;
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}
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#endif
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