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Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
82 lines
1.7 KiB
C
82 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*/
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#ifndef __QCOM_CLK_PLL_H__
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#define __QCOM_CLK_PLL_H__
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#include <linux/clk-provider.h>
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#include "clk-regmap.h"
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/**
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* struct pll_freq_tbl - PLL frequency table
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* @l: L value
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* @m: M value
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* @n: N value
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* @ibits: internal values
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*/
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struct pll_freq_tbl {
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unsigned long freq;
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u16 l;
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u16 m;
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u16 n;
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u32 ibits;
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};
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/**
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* struct clk_pll - phase locked loop (PLL)
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* @l_reg: L register
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* @m_reg: M register
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* @n_reg: N register
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* @config_reg: config register
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* @mode_reg: mode register
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* @status_reg: status register
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* @status_bit: ANDed with @status_reg to determine if PLL is enabled
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* @freq_tbl: PLL frequency table
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* @hw: handle between common and hardware-specific interfaces
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*/
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struct clk_pll {
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u32 l_reg;
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u32 m_reg;
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u32 n_reg;
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u32 config_reg;
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u32 mode_reg;
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u32 status_reg;
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u8 status_bit;
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u8 post_div_width;
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u8 post_div_shift;
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const struct pll_freq_tbl *freq_tbl;
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struct clk_regmap clkr;
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};
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extern const struct clk_ops clk_pll_ops;
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extern const struct clk_ops clk_pll_vote_ops;
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extern const struct clk_ops clk_pll_sr2_ops;
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#define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr)
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struct pll_config {
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u16 l;
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u32 m;
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u32 n;
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u32 vco_val;
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u32 vco_mask;
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u32 pre_div_val;
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u32 pre_div_mask;
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u32 post_div_val;
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u32 post_div_mask;
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u32 mn_ena_mask;
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u32 main_output_mask;
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u32 aux_output_mask;
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};
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void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
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const struct pll_config *config, bool fsm_mode);
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void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
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const struct pll_config *config, bool fsm_mode);
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#endif
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