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5d375199ea
When a guest has a PCI pass-through device with an interrupt, it will direct the interrupt to a particular guest VCPU. In fact the physical interrupt might arrive on any CPU, and then get delivered to the target VCPU in the emulated XICS (guest interrupt controller), and eventually delivered to the target VCPU. Now that we have code to handle device interrupts in real mode without exiting to the host kernel, there is an advantage to having the device interrupt arrive on the same sub(core) as the target VCPU is running on. In this situation, the interrupt can be delivered to the target VCPU without any exit to the host kernel (using a hypervisor doorbell interrupt between threads if necessary). This patch aims to get passed-through device interrupts arriving on the correct core by setting the interrupt server in the real hardware XICS for the interrupt to the first thread in the (sub)core where its target VCPU is running. We do this in the real-mode H_EOI code because the H_EOI handler already needs to look at the emulated ICS state for the interrupt (whereas the H_XIRR handler doesn't), and we know we are running in the target VCPU context at that point. We set the server CPU in hardware using an OPAL call, regardless of what the IRQ affinity mask for the interrupt says, and without updating the affinity mask. This amounts to saying that when an interrupt is passed through to a guest, as a matter of policy we allow the guest's affinity for the interrupt to override the host's. This is inspired by an earlier patch from Suresh Warrier, although none of this code came from that earlier patch. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
148 lines
3.5 KiB
C
148 lines
3.5 KiB
C
/*
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* Copyright 2012 Michael Ellerman, IBM Corporation.
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* Copyright 2012 Benjamin Herrenschmidt, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*/
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#ifndef _KVM_PPC_BOOK3S_XICS_H
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#define _KVM_PPC_BOOK3S_XICS_H
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/*
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* We use a two-level tree to store interrupt source information.
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* There are up to 1024 ICS nodes, each of which can represent
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* 1024 sources.
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*/
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#define KVMPPC_XICS_MAX_ICS_ID 1023
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#define KVMPPC_XICS_ICS_SHIFT 10
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#define KVMPPC_XICS_IRQ_PER_ICS (1 << KVMPPC_XICS_ICS_SHIFT)
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#define KVMPPC_XICS_SRC_MASK (KVMPPC_XICS_IRQ_PER_ICS - 1)
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/*
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* Interrupt source numbers below this are reserved, for example
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* 0 is "no interrupt", and 2 is used for IPIs.
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*/
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#define KVMPPC_XICS_FIRST_IRQ 16
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#define KVMPPC_XICS_NR_IRQS ((KVMPPC_XICS_MAX_ICS_ID + 1) * \
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KVMPPC_XICS_IRQ_PER_ICS)
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/* Priority value to use for disabling an interrupt */
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#define MASKED 0xff
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/* State for one irq source */
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struct ics_irq_state {
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u32 number;
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u32 server;
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u8 priority;
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u8 saved_priority;
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u8 resend;
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u8 masked_pending;
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u8 lsi; /* level-sensitive interrupt */
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u8 asserted; /* Only for LSI */
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u8 exists;
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int intr_cpu;
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u32 host_irq;
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};
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/* Atomic ICP state, updated with a single compare & swap */
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union kvmppc_icp_state {
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unsigned long raw;
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struct {
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u8 out_ee:1;
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u8 need_resend:1;
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u8 cppr;
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u8 mfrr;
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u8 pending_pri;
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u32 xisr;
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};
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};
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/* One bit per ICS */
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#define ICP_RESEND_MAP_SIZE (KVMPPC_XICS_MAX_ICS_ID / BITS_PER_LONG + 1)
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struct kvmppc_icp {
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struct kvm_vcpu *vcpu;
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unsigned long server_num;
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union kvmppc_icp_state state;
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unsigned long resend_map[ICP_RESEND_MAP_SIZE];
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/* Real mode might find something too hard, here's the action
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* it might request from virtual mode
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*/
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#define XICS_RM_KICK_VCPU 0x1
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#define XICS_RM_CHECK_RESEND 0x2
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#define XICS_RM_REJECT 0x4
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#define XICS_RM_NOTIFY_EOI 0x8
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u32 rm_action;
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struct kvm_vcpu *rm_kick_target;
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struct kvmppc_icp *rm_resend_icp;
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u32 rm_reject;
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u32 rm_eoied_irq;
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/* Counters for each reason we exited real mode */
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unsigned long n_rm_kick_vcpu;
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unsigned long n_rm_check_resend;
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unsigned long n_rm_reject;
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unsigned long n_rm_notify_eoi;
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/* Counters for handling ICP processing in real mode */
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unsigned long n_check_resend;
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unsigned long n_reject;
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/* Debug stuff for real mode */
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union kvmppc_icp_state rm_dbgstate;
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struct kvm_vcpu *rm_dbgtgt;
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};
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struct kvmppc_ics {
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arch_spinlock_t lock;
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u16 icsid;
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struct ics_irq_state irq_state[KVMPPC_XICS_IRQ_PER_ICS];
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};
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struct kvmppc_xics {
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struct kvm *kvm;
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struct kvm_device *dev;
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struct dentry *dentry;
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u32 max_icsid;
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bool real_mode;
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bool real_mode_dbg;
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u32 err_noics;
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u32 err_noicp;
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struct kvmppc_ics *ics[KVMPPC_XICS_MAX_ICS_ID + 1];
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};
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static inline struct kvmppc_icp *kvmppc_xics_find_server(struct kvm *kvm,
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u32 nr)
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{
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struct kvm_vcpu *vcpu = NULL;
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int i;
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kvm_for_each_vcpu(i, vcpu, kvm) {
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if (vcpu->arch.icp && nr == vcpu->arch.icp->server_num)
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return vcpu->arch.icp;
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}
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return NULL;
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}
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static inline struct kvmppc_ics *kvmppc_xics_find_ics(struct kvmppc_xics *xics,
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u32 irq, u16 *source)
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{
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u32 icsid = irq >> KVMPPC_XICS_ICS_SHIFT;
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u16 src = irq & KVMPPC_XICS_SRC_MASK;
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struct kvmppc_ics *ics;
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if (source)
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*source = src;
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if (icsid > KVMPPC_XICS_MAX_ICS_ID)
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return NULL;
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ics = xics->ics[icsid];
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if (!ics)
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return NULL;
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return ics;
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}
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#endif /* _KVM_PPC_BOOK3S_XICS_H */
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