Jerome Brunet 007e6e5c5f clk: meson: mpll: add rw operation ... This patch adds new callbacks to the meson-mpll driver to control and set the pll rate. For this, we also need to add the enable bit and sdm enable bit. The corresponding parameters are added to mpll data structure. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-6-jbrunet@baylibre.com		2017-03-27 12:30:18 -07:00
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clk-cpu.c	clk: meson8b: clean up cpu clocks	2016-06-22 18:02:35 -07:00
clk-mpll.c	clk: meson: mpll: add rw operation	2017-03-27 12:30:18 -07:00
clk-pll.c	clk: meson: fractional pll support	2016-06-22 18:05:47 -07:00
clkc.h	clk: meson: mpll: add rw operation	2017-03-27 12:30:18 -07:00
gxbb-aoclk.c	clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe()	2016-08-24 00:55:13 -07:00
gxbb.c	clk: meson: mpll: add rw operation	2017-03-27 12:30:18 -07:00
gxbb.h	clk: gxbb: fix CLKID_ETH defined twice	2017-01-27 10:56:57 -08:00
Kconfig	clk: gxbb: add AmLogic GXBB clk controller driver	2016-06-22 18:07:31 -07:00
Makefile	clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention	2016-09-01 17:31:44 -07:00
meson8b.c	clk: meson8b: put dividers and muxes in tables	2017-03-27 12:30:01 -07:00
meson8b.h	meson: clk: Add support for clock gates	2016-09-01 17:43:12 -07:00