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aab547ce0d
This adds the Gigabit Ethernet driver for the SSB Gigabit Ethernet core. This driver actually is a frontend to the Tigon3 driver. So the real work is done by tg3. This device is used in the Linksys WRT350N. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
131 lines
5.3 KiB
C
131 lines
5.3 KiB
C
#ifndef LINUX_SSB_PCICORE_H_
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#define LINUX_SSB_PCICORE_H_
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#include <linux/types.h>
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struct pci_dev;
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#ifdef CONFIG_SSB_DRIVER_PCICORE
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/* PCI core registers. */
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#define SSB_PCICORE_CTL 0x0000 /* PCI Control */
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#define SSB_PCICORE_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
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#define SSB_PCICORE_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
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#define SSB_PCICORE_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
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#define SSB_PCICORE_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
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#define SSB_PCICORE_ARBCTL 0x0010 /* PCI Arbiter Control */
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#define SSB_PCICORE_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
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#define SSB_PCICORE_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
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#define SSB_PCICORE_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */
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#define SSB_PCICORE_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
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#define SSB_PCICORE_ARBCTL_PARKID_4710 0x00000002 /* 4710 */
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#define SSB_PCICORE_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */
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#define SSB_PCICORE_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */
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#define SSB_PCICORE_ISTAT 0x0020 /* Interrupt status */
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#define SSB_PCICORE_ISTAT_INTA 0x00000001 /* PCI INTA# */
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#define SSB_PCICORE_ISTAT_INTB 0x00000002 /* PCI INTB# */
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#define SSB_PCICORE_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
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#define SSB_PCICORE_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
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#define SSB_PCICORE_ISTAT_PME 0x00000010 /* PCI PME# */
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#define SSB_PCICORE_IMASK 0x0024 /* Interrupt mask */
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#define SSB_PCICORE_IMASK_INTA 0x00000001 /* PCI INTA# */
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#define SSB_PCICORE_IMASK_INTB 0x00000002 /* PCI INTB# */
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#define SSB_PCICORE_IMASK_SERR 0x00000004 /* PCI SERR# */
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#define SSB_PCICORE_IMASK_PERR 0x00000008 /* PCI PERR# */
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#define SSB_PCICORE_IMASK_PME 0x00000010 /* PCI PME# */
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#define SSB_PCICORE_MBOX 0x0028 /* Backplane to PCI Mailbox */
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#define SSB_PCICORE_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */
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#define SSB_PCICORE_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */
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#define SSB_PCICORE_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */
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#define SSB_PCICORE_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */
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#define SSB_PCICORE_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */
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#define SSB_PCICORE_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */
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#define SSB_PCICORE_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */
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#define SSB_PCICORE_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */
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#define SSB_PCICORE_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */
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#define SSB_PCICORE_BCAST_ADDR_MASK 0x000000FF
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#define SSB_PCICORE_BCAST_DATA 0x0054 /* Backplane Broadcast Data */
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#define SSB_PCICORE_GPIO_IN 0x0060 /* rev >= 2 only */
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#define SSB_PCICORE_GPIO_OUT 0x0064 /* rev >= 2 only */
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#define SSB_PCICORE_GPIO_ENABLE 0x0068 /* rev >= 2 only */
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#define SSB_PCICORE_GPIO_CTL 0x006C /* rev >= 2 only */
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#define SSB_PCICORE_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */
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#define SSB_PCICORE_SBTOPCI0_MASK 0xFC000000
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#define SSB_PCICORE_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */
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#define SSB_PCICORE_SBTOPCI1_MASK 0xFC000000
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#define SSB_PCICORE_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
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#define SSB_PCICORE_SBTOPCI2_MASK 0xC0000000
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#define SSB_PCICORE_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
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#define SSB_PCICORE_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
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#define SSB_PCICORE_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
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#define SSB_PCICORE_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
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#define SSB_PCICORE_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
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/* SBtoPCIx */
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#define SSB_PCICORE_SBTOPCI_MEM 0x00000000
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#define SSB_PCICORE_SBTOPCI_IO 0x00000001
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#define SSB_PCICORE_SBTOPCI_CFG0 0x00000002
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#define SSB_PCICORE_SBTOPCI_CFG1 0x00000003
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#define SSB_PCICORE_SBTOPCI_PREF 0x00000004 /* Prefetch enable */
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#define SSB_PCICORE_SBTOPCI_BURST 0x00000008 /* Burst enable */
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#define SSB_PCICORE_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */
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#define SSB_PCICORE_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */
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#define SSB_PCICORE_SBTOPCI_RC_READ 0x00000000 /* Memory read */
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#define SSB_PCICORE_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
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#define SSB_PCICORE_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
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/* PCIcore specific boardflags */
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#define SSB_PCICORE_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
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struct ssb_pcicore {
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struct ssb_device *dev;
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u8 setup_done:1;
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u8 hostmode:1;
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u8 cardbusmode:1;
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};
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extern void ssb_pcicore_init(struct ssb_pcicore *pc);
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/* Enable IRQ routing for a specific device */
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extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
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struct ssb_device *dev);
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int ssb_pcicore_plat_dev_init(struct pci_dev *d);
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int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
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#else /* CONFIG_SSB_DRIVER_PCICORE */
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struct ssb_pcicore {
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};
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static inline
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void ssb_pcicore_init(struct ssb_pcicore *pc)
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{
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}
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static inline
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int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
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struct ssb_device *dev)
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{
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return 0;
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}
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static inline
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int ssb_pcicore_plat_dev_init(struct pci_dev *d)
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{
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return -ENODEV;
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}
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static inline
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int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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return -ENODEV;
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}
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#endif /* CONFIG_SSB_DRIVER_PCICORE */
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#endif /* LINUX_SSB_PCICORE_H_ */
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