renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-28 23:23:55 +08:00
Code
000590a5e2
linux-next/drivers/clk/rockchip
History
Heiko Stuebner 000590a5e2 Revert "clk: rockchip: use module_platform_driver_probe" 
This reverts commit 1da80da028.

Reading recent discussions [0] [1], I realized this change introduces
a number of problems:

- only converting to module_platform_driver creates the issue
  with the existing __init and __initdata attributes.

  When the driver would've been built as a module, all the missing
  clock-definitions (all are initdata) should've turned up as error
  in testing suggesting that the change wasn't at all

- a clock driver is a very core component of soc bringup and making
  this able to be built as a module solely for enabling the soc vendor
  to add out of tree changes for Android implementations is not in our
  interest and also everything except a ramdisk won't probe without a
  clock controller.

  This is especially true when the changes aren't really tested and
  are merely added to move the mainline driver "out of the way".

[0] https://lwn.net/Articles/872209/
[1] https://lore.kernel.org/all/163529604399.15791.378104318036812951@swboyd.mtv.corp.google.com/

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20211027132616.1039814-2-heiko@sntech.de
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-11-02 17:59:00 -07:00
..
clk-cpu.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-ddr.c clk: rockchip: Export rockchip_clk_register_ddrclk() 2020-09-22 15:16:37 +02:00
clk-half-divider.c clk: rockchip: Demote non-conformant kernel-doc header in half-divider 2021-01-26 00:24:05 +01:00
clk-inverter.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-mmc-phase.c clk: rockchip: fix mmc get phase 2020-03-06 12:06:01 -08:00
clk-muxgrf.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 2019-06-05 17:36:37 +02:00
clk-pll.c clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types 2021-07-29 11:22:29 +02:00
clk-px30.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3036.c clk: rockchip: Add support for hclk_sfc on rk3036 2021-07-16 00:33:42 +02:00
clk-rk3128.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3188.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3228.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3288.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3308.c clk: rockchip: make rk3308 ddrphy4x clock critical 2021-07-29 12:43:11 +02:00
clk-rk3328.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3368.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3399.c Revert "clk: rockchip: use module_platform_driver_probe" 2021-11-02 17:59:00 -07:00
clk-rk3568.c Revert "clk: rockchip: use module_platform_driver_probe" 2021-11-02 17:59:00 -07:00
clk-rv1108.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk.c clk: fractional-divider: Export approximation algorithm to the CCF users 2021-08-12 12:41:47 -07:00
clk.h clk: rockchip: Optimize PLL table memory usage 2021-05-11 12:22:29 +02:00
Kconfig clk: rockchip: drop parenthesis from ARM || COMPILE_TEST depends 2021-03-21 11:13:30 +01:00
Makefile clk: rockchip: add clock controller for rk3568 2021-03-21 11:10:59 +01:00
softrst.c clk: rockchip: Export rockchip_register_softrst() 2020-09-22 15:16:38 +02:00