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4db8e6d20c
In addition to consolidating the or1k-pic with other interrupt controllers, this makes OpenRISC less tied to its on-cpu interrupt controller. All or1k-pic specific parts are moved out of irq.c and into drivers/irqchip/irq-or1k-pic.c In that transition, the functionality have been divided into three chip variants. One that handles level triggered interrupts, one that handles edge triggered interrupts and one that handles the interrupt controller that is present in the or1200 OpenRISC cpu implementation. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Link: https://lkml.kernel.org/r/1401136302-27654-1-git-send-email-stefan.kristiansson@saunalahti.fi Acked-by: Jonas Bonn <jonas@southpole.se> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
24 lines
797 B
Plaintext
24 lines
797 B
Plaintext
OpenRISC 1000 Programmable Interrupt Controller
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Required properties:
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- compatible : should be "opencores,or1k-pic-level" for variants with
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level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
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edge triggered interrupt lines or "opencores,or1200-pic" for machines
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with the non-spec compliant or1200 type implementation.
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"opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
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but this is only for backwards compatibility.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value shall be 1.
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Example:
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intc: interrupt-controller {
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compatible = "opencores,or1k-pic-level";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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