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c0ca726208
Add the initialization of the generic irq chip for the BCM7271 L2 interrupt controller. This controller only supports level interrupts and uses the "brcm,bcm7271-l2-intc" compatibility string. Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Doug Berger <opendmb@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
31 lines
1.0 KiB
Plaintext
31 lines
1.0 KiB
Plaintext
Broadcom Generic Level 2 Interrupt Controller
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Required properties:
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- compatible: should be "brcm,l2-intc" for latched interrupt controllers
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should be "brcm,bcm7271-l2-intc" for level interrupt controllers
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- reg: specifies the base physical address and size of the registers
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. Should be 1.
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- interrupt-parent: specifies the phandle to the parent interrupt controller
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this controller is cacaded from
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- interrupts: specifies the interrupt line in the interrupt-parent irq space
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to be used for cascading
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Optional properties:
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- brcm,irq-can-wake: If present, this means the L2 controller can be used as a
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wakeup source for system suspend/resume.
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Example:
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hif_intr2_intc: interrupt-controller@f0441000 {
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compatible = "brcm,l2-intc";
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reg = <0xf0441000 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&intc>;
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interrupts = <0x0 0x20 0x0>;
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};
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