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Commit Graph

7 Commits

Author SHA1 Message Date
Huang Shijie
9545b2ed68 ARM: imx6q: clk: add the eim_slow clock
Add the eim_slow clock, since the weim needs it.

Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17 15:45:12 +08:00
Philipp Zabel
2df1d026ed ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1
Query silicon revision to determine clock tree and add post
dividers for newer revisions.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12 19:28:12 +08:00
Peter Chen
a5120e89e7 ARM i.MX6: change mxs usbphy clock usage
This mxs usbphy is only needs to be on after system boots
up, and software never needs to control it anymore.
Meanwhile, usbphy's parent needs to be notified if usb
is suspend or not. So we design below mxs usbphy usage:

- usbphy1_gate and usbphy2_gate:
Their parents are dummy clock, we only needs to enable
it after system boots up.
- usbphy1 and usbphy2
Usage reserved bit for this clock, in that case, the refcount
will be updated, but without hardware changing.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-10 23:25:45 +08:00
Fabio Estevam
7425057294 clk: imx: Remove 'clock-output-names' from the examples
'clock-output-names' is not used in any of the dts/dtsi files for i.mx.

Remove it from the examples, so that the example and the real usage in the
dtsi files can match.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-01-04 13:16:00 +08:00
Sascha Hauer
7a04092c73 ARM i.MX6: Fix ethernet PLL clocks
In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz
and has different outputs. Only the enet reference clock is implemented. This
patch changes the PLL so that it outputs 500MHz and adds the additional outputs
as dividers. This now matches the datasheet which says:

> This PLL synthesizes a low jitter clock from 24 MHz reference clock.
> The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are:
>  • Ref_PCIe = 125 MHz
>  • Ref_SATA = 100 MHz
>  • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
2012-11-22 15:32:33 +01:00
Sascha Hauer
13861701a8 ARM i.MX6: rename PLLs according to datasheet
In recent reference manuals the PLLs were renumbered. PLL8 now is
PLL6 and vice versa. Change the code according to the reference
manual to avoid confusion.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
2012-11-22 15:32:24 +01:00
Shawn Guo
0e87e0436c ARM: imx6q: replace clk_register_clkdev with clock DT lookup
It really becomes an maintenance issue that every time a device needs
to look up (clk_get) a clock we have to patch kernel clock file to call
clk_register_clkdev for that clock.

Since clock DT support which is meant to resolve clock lookup in device
tree is in place, the patch moves imx6q client devices' clock lookup
over to device tree, so that any new lookup to be added at later time
can just get done in DT instead of kernel.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-09-11 19:16:14 +08:00