Patch from Pavel Pisa
This is another approach to SDHC deficiency workaround.
It seems, that previous solution based on 16 bytes (FIFO length size)
read is still timing sensitive on genirq and fully preemptive kernels.
The new solution is backuped by M9328 UM statement, that only 512 byte
block are working properly and by 2.4.26 FreeScale's SDHC code.
Jay Monkman reports significant improvement on code based
on this driver after applying this change on MX21 as well.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The MMC specification allows non-power of two block sizes. As such,
we should not pass the log2 block size to host drivers, but instead
pass the byte size.
However, ARM MMCI can only work with log2 block size, so continue to
pass both the log2 block size and byte block size. This means that
for the moment, the byte block size must remain a power of two, but
this is the first stage of removing this restriction for other hosts.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Patch from Pavel Pisa
There has been problems that for some paths that clock are not stopped
during new command programming and initiation. Result is issuing
of incorrect command to the card. Some other problems are cleaned too.
Noisy report of known ERRATUM #4 has been suppressed.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than having every driver duplicate the set_ios debugging,
provide a single version in mmc.c which can be expanded as we
add additional functionality.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Always send a stop command at the end of a data transfer. If we avoid
sending the stop command, some cards remain in data transfer mode, and
refuse to accept further read/write commands.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Patch from Pavel Pisa
The clock starting imxmci_start_clock() function contains hardware
issue workaround, which repeats start attempt, if SDHC does not react on
the first trial. But the second start attempt can be taken even, if the
first succeed and test code misses time limited clock running phase
due to delay caused by schedule to other task or some another device
interrupt. This change enables to detect such situation.
The performance is not issue, because usually at full clock rate
only about six loops in delay cycle are needed.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Patch from Pavel Pisa
This patch adds support of i.MX/MX1 SD/MMC controller.
It has been significantly redesigned from the original Sascha Hauer's
version to support scatter-gather DMA, to conform to latest Pierre Ossman's
and Russell King's MMC-SD Linux 2.6.x infrastructure.
The handling of all events has been moved to the softirq context
and is designed with no busy-looping in mind. Unfortunately
some controller bugs has to be overcome by limited looping
about 2-20 usec but these are observed only for initial card
recognition phase.
There are still some missing/missed IRQs problems under heavy load.
Help of somebody with access to the full SDHC design information
is probably necessary.
Regenerated against 2.6.16-git-060402 to solve clash with other patches.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
