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Commit Graph

10 Commits

Author SHA1 Message Date
Steffen Trumtrar
5e21828034 ARM: zynq: Hang iomapped slcr address on device_node
For later usage by zynq clk driver.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-10 11:21:06 +01:00
Michal Simek
016f4dcae8 ARM: zynq: Split slcr in two parts
Split the slcr into an early part for unlocking and cpu starting
and a later syscon driver.
Also add "syscon" compatible property for slcr.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-10 11:20:54 +01:00
Steffen Trumtrar
6f69c7f21c ARM: zynq: Move clock_init from slcr to common
Preparation step for next changes.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-02-05 15:57:00 +01:00
Soren Brinkmann
3db9e86029 arm: zynq: slcr: Use read-modify-write for register writes
zynq_slcr_cpu_start/stop() ignored the current register state when
writing to a register. Fixing this by implementing proper
read-modify-write.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-07-26 14:14:41 +02:00
Soren Brinkmann
b5f177ff30 arm: zynq: slcr: Clean up #defines
Use a common naming scheme for register offset #defines:
Some of those used a '_OFFSET' suffix to distinguish them from others.
This scheme is used for all register offsets now.

Separate the register offset #defines from others and sort them in
increasing order.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-07-26 14:14:39 +02:00
Soren Brinkmann
c323f2a188 arm: zynq: slcr: Remove redundant header #includes
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-07-26 14:14:38 +02:00
Soren Brinkmann
30e1e28598 arm: zynq: Migrate platform to clock controller
Migrate the Zynq platform and its drivers to use the new clock
controller driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: linux-serial@vger.kernel.org
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
2013-05-27 09:21:22 +02:00
Michal Simek
aa7eb2bb4e arm: zynq: Add smp support
Zynq is dual core Cortex A9 which starts always
at zero. Using simple trampoline ensure long jump
to secondary_startup code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
2013-04-04 09:24:00 +02:00
Michal Simek
96790f0a28 arm: zynq: Add support for system reset
Do system reset via slcr registers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-04-04 09:22:29 +02:00
Michal Simek
64b889b39e arm: zynq: Move slcr initialization to separate file
Create separate slcr driver instead of polluting common code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-04-04 09:22:29 +02:00