it ready to move to drivers/irqchip. Note that this series
does not yet move the interrupt code to drivers, that will
be posted separately as a follow-up series.
Note that this branch has a dependency to patches both
in fixes-v3.18-not-urgent and soc-for-v3.18 and is based on
a merge. Without doing the merge, off-idle would not work
properly for git bisect.
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Merge tag 'intc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
Merge "omap intc changes for v3.18 merge window" from Tony Lindgren:
Interrupt code related clean-up for omap2 and 3 to make
it ready to move to drivers/irqchip. Note that this series
does not yet move the interrupt code to drivers, that will
be posted separately as a follow-up series.
Note that this branch has a dependency to patches both
in fixes-v3.18-not-urgent and soc-for-v3.18 and is based on
a merge. Without doing the merge, off-idle would not work
properly for git bisect.
* tag 'intc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (325 commits)
arm: omap: intc: switch over to linear irq domain
arm: omap: irq: get rid of ifdef hack
arm: omap: irq: introduce omap_nr_pending
arm: omap: irq: remove nr_irqs argument
arm: omap: irq: remove unnecessary header
arm: omap: irq: drop omap2_intc_handle_irq()
arm: omap: irq: drop omap3_intc_handle_irq()
arm: omap: irq: call set_handle_irq() from .init_irq
arm: omap: irq: move some more code around
arm: boot: dts: omap2/3/am33xx: drop ti,intc-size
arm: omap: irq: drop ti,intc-size support
arm: boot: dts: am33xx/omap3: fix intc compatible flag
arm: omap: irq: use compatible flag to figure out number of IRQ lines
arm: omap: irq: add specific compatibles for omap3 and am33xx devices
arm: omap: irq: drop .handle_irq and .init_irq fields
arm: omap: irq: use IRQCHIP_DECLARE macro
arm: omap: irq: call set_handle_irq() from intc_of_init
arm: omap: irq: make intc_of_init static
arm: omap: irq: reorganize code a little bit
arm: omap: irq: always define omap3 support
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- move of the PIT (basic timer) from mach-at91 to its proper location:
drivers/clocksource
- big cleanup of this driver along the way
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Merge tag 'at91-drivers2' of git://github.com/at91linux/linux-at91 into next/drivers
Merge " Second drivers series for AT91/3.18" from Nicolas Ferre:
- move of the PIT (basic timer) from mach-at91 to its proper location:
drivers/clocksource
- big cleanup of this driver along the way
* tag 'at91-drivers2' of git://github.com/at91linux/linux-at91:
ARM: at91: PIT: Move the driver to drivers/clocksource
ARM: at91: Give the PIT irq as an argument of at91sam926x_pit_init
ARM: at91: Convert the boards to the init_time callback
ARM: at91: soc: Add init_time callback
ARM: at91: PIT: (Almost) remove the global variables
ARM: at91: PIT: use request_irq instead of setup_irq
ARM: at91: PIT: Use pr_fmt
ARM: at91: PIT: Use consistent exit path in probe
ARM: at91: dt: Remove init_time definitions
ARM: at91: PIT: Rework probe functions
ARM: at91: PIT: Use of_have_populated_dt instead of CONFIG_OF
ARM: at91: PIT: Use DIV_ROUND_CLOSEST to compute the cycles
ARM: at91: generic.h: Add include safe guards
ARM: at91: PIT: Follow the general coding rules
Signed-off-by: Olof Johansson <olof@lixom.net>
Now that we don't depend on anyting in the mach-at91 directory, we can just
move the driver to where it belongs.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Conflicts:
arch/arm/mach-at91/Kconfig
arch/arm/mach-at91/Makefile
This allows to remove the dependency of the timer driver on mach/hardware.h and
having an hardcoded interrupt number in the driver itself.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
now that we don't need to support legacy board-files,
we can completely switch over to a linear irq domain
and make use of irq_alloc_domain_generic_chips() to
allocate all generic irq chips for us.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
we don't need the ifdef if we have omap_nr_pending
telling us how many pending registers we have
on current platform. This solves a possible
problem where we could try to handle bogus
interrupts on OMAP2 and OMAP3 if using single
zImage kernel, because we would end up reading
the following pending FIQ register.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
that variable will tell us how many INTC_PENDING_IRQn
registers we have. It'll be used on a following patch
to cleanup omap_intc_handle_irq() a bit.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
we can set our global omap_nr_irqs early on
and drop the extra argument to omap_init_irq().
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
that was just a no-op wrapper around omap_intc_handle_irq
anyway.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
now that we're calling set_handle_irq() from
init_irq(), we can safely drop all callers to
omap3_intc_handle_irq() and its definition.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
the idea is that board-files won't need to set
.handle_irq on their machine_descs, which lets
us drop a little more pointless code.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We want .init_irq to call set_irq_handle() for
legacy platforms. Note that this code will also
be dropped once omap2/3 devices are completely
moved to DT.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
we are now infering number of IRQ lines based
on correct compatible flag, which renders this
binding completely useless.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
we don't need that anymore since specific
devices are passing correct compatible flags.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
that way, our intc driver can figure out how
many IRQ lines INTC has.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
so far, only am33xx has 128 lines, all other devices
have only 96.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
with this, we can use a compatible flag to figure
out how many irq lines are wired up, no need for
our TI-specific ti,intc-size binding.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
now we can safely drop those fields from our machine_desc.
While at that, also drop the now unused omap_intc_of_init()
definition.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
IRQCHIP_DECLARE macro is used to declare the same
of_device_id structure for irqchips, it's just
a helper. No functional changes.
Note that we're temporarily including irqchip.h
with its full path, until we move this driver
to drivers/irqchip/.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
this will let us drop .handle_irq and .init_irq fields
from our generic machine_descs.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
nobody uses that function outside of this file,
so we don't need to expose it.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
remove ifdef around omap3 INTC support. This
will make it easier to reuse code for PM.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
omap_intc_handle_irq now had an unnecessary
base_addr argument. Let's remove it and fix
all callers.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
an almost blind conversion from readl_relaxed
to our newly introduced intc_readl().
While at that, also remove some hardcoded
register addresses.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
this will cache number of irqs. Also in preparation
for removal of irq_banks array.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We have a single bank in that array, this patch
is in preparation to remove that array. It just
shifts everything to a new set of functions
for register IO while also removing old ones.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This is in preparation for removing the pointless
irq_banks array.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
of_device_ids (i.e. compatible strings and the respective data) are not
supposed to change at runtime. All functions working with of_device_ids
provided by <linux/of.h> work with const of_device_ids. So mark the
non-const function parameters and structs for OMAP2+ as const, too.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The definition
static const char *omap3_boards_compat[] __initconst = {
defines a changable array of constant strings. That is you must not do:
*omap3_boards_compat[0] = 'f';
but
omap3_boards_compat[0] = "another string";
is fine. So the annotation __initconst is wrong and yields a compiler
error when other really const variables are added with __initconst.
As the struct machine_desc member dt_compat is declared as
const char *const *dt_compat;
making the arrays const is the better alternative over changing all
annotations to __initdata.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Merge tag 'socfpga_driver_for_v3.18' of git://git.rocketboards.org/linux-socfpga-next into next/drivers
Pull "SOCFPGA driver update for v3.18" from Dinh Nguyen:
This is the EDAC driver for EDAC. Boris had given me permission to
take this patch together with it's DTS component. The DTS portion was in the
previous pull request.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'socfpga_driver_for_v3.18' of git://git.rocketboards.org/linux-socfpga-next:
edac: altera: Add Altera SDRAM EDAC support
Provide OMAP3, 4 and OMAP5 with interrupt number for PRM
And for DRA7, provide crossbar number for prm interrupt.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OPP is now a normal kernel library selected by its users rather than a
feature that architectures need to enable so ARCH_HAS_OPP serves no
function any more - remove the selects.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With consolidated code, now we can add the required hooks for
DRA7 to enable power management.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: minor modifications]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With consolidated code, now we can add the required hooks for
OMAP5 to enable power management.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor rebase updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR
and instead attempt a CPU RET and side effect, MPU RET in suspend.
NOTE: the hardware was originally designed to be capable of achieving
deep power states such as OFF and OSWR, however due to various issues
and risks, deepest valid state was determined to be CSWR - hence we use
the errata framework to handle this case.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug
logic. On OMAP5, DRA7, we do not need this in place yet, also,
currently the CPU startup pointer is located in omap4_cpu_pm_info
instead of cpu_pm_ops.
So, isolate the function to hotplug_restart pointer in cpu_pm_ops
where it should have belonged, initalize them as per valid startup
pointers for OMAP4430/60 as in current logic, however provide
dummy_cpu_resume to be the startup location as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: split this out of original code and isolate it]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Get rid of all assumptions about always having a sar base on *all*
OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at
this point for OMAP5 either.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: Split and optimize]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
In addition to the standard power-management technique, the OMAP5 / DRA7
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.
It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU. Only "Fast-mode" is supported on the
OMAP5 and DRA7 family of processors.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor consolidation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.
0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together.
Broken! Fortunately, we do not support this anymore.
0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode
independently.
This is one time settings thanks to always ON domain.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor conflict resolutions, consolidation for DRA7]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
With EMIF clock-domain put under hardware supervised control, memory
corruption and untraceable crashes are observed on OMAP5. Further
investigation revealed that there is a weakness in the PRCM on this
specific dynamic depedency.
The recommendation is to set MPUSS static dependency towards EMIF
clock-domain to avoid issues. This recommendation holds good for DRA7
family of devices as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: conflict resolution, dra7]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same
context offset as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: for DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: rebase, split/merge etc..]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
