The current code was ignoring the end of update for all overlay planes,
caring only for the primary plane update in case of pageflip.
This change adds a change to start to check for pending updates for all
planes through exynos_plane->pending_fb. At the start of plane update the
pending_fb is set with the fb to be shown on the screen. Then only when to
fb is already presented in the screen we set pending_fb to NULL to
signal that the update was finished.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
fixup! drm/exynos: check for pending fb before finish update
Only set/clear the update bit in the CRTC's .atomic_begin()/flush()
so all planes are really committed at the same time.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
From: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
.prepare_plane() and .cleanup_plane() allows to perform extra operations
before and after the update of planes. For FIMD for example this will
be used to enable disable the shadow protection bit.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Unify handling of finished plane update to prepare for a following patch
that will check for the START and START_S regs to really make sure that
the plane was updated.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
struct drm_crtc already stores the enabled state of the crtc
thus we don't need to replicate enabled in exynos_drm_crtc.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
The latter is a default version of <asm/mman.h> and not for driver use.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Saving the current UVD state on suspend and restoring it on resume
just doesn't work reliable. Just close cleanup all sessions on suspend.
Ported from radeon commit "12e49feadff6d7b7ebbe852b36943a71524d8d34".
v2: rebased
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
This way the scheduler doesn't wait in it's work thread any more.
v2: fix race conditions
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Since BIOS RC 1.4 it would enable CDCLK PLL during BIOS S3 resume, then
driver needs to set CDCLK to avoid display corruption if DPLL0 enabled.
References: https://bugs.freedesktop.org/show_bug.cgi?id=91697
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Cooper Chiou <cooper.chiou@intel.com>
Reviewed-by: Wei Shun Chang <wei.shun.chang@intel.com>
Tested-by: Gary Wang <gary.c.wang@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Gavin Hindman <gavin.hindman@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Xiong Y Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Gary Wang <gary.c.wang@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Rather large pull request this time around, due to the long-pending
cleanup of the kernel driver being here. There's a stupidly large
number of commits for that, as I wanted to have the series be
bisectable at a fairly fine-grained level. That said, a very large
portion of the churn in the rework was automated, and a very large
number of boards from right across the whole range we support have
been tested. I'm fairly confident there shouldn't be (too many)
issues from this.
Beyond correcting some not-so-great design decisions and making the
code a lot easier to work with, there's not much exciting (lower
memory usage, GPU VM should be a lot faster, etc) to be gained by the
end-user as a result of the cleanup, it mostly lays the groundwork for
future improvements.
A big thanks goes to Alexandre Courbot for testing/debugging the GK20A
codepaths for me :)
Highlights:
- A heap of perfmon work, providing a more useful userspace interface
and specifying counters for a bunch of boards
- Support for GT200 reclocking + other misc pm improvements
- Initial patches towards supporting GM20B (Tegra X1)
- Maxwell DisplayPort fixes
- Cleanup of the kernel driver
- The usual collection of random fixes
* 'linux-4.3' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (312 commits)
drm/nouveau: bump driver version for release
drm/nouveau/tegra: merge platform setup from nouveau drm
drm/nouveau/pci: merge agp handling from nouveau drm
drm/nouveau/device: remove pci/platform_device from common struct
drm/nouveau/device: import pciid list and integrate quirks with it
drm/nouveau/device: cleaner abstraction for device resource functions
drm/nouveau/mc: move device irq handling to platform-specific code
drm/nouveau/mc/gf100-: handle second interrupt tree
drm/nouveau/mc: abstract interface to master intr registers
drm/nouveau/pci: new subdev
drm/nouveau/object: merge with handle
drm/nouveau/core: remove the remainder of the previous style
drm/nouveau/mpeg: convert to new-style nvkm_engine
drm/nouveau/sw: convert to new-style nvkm_engine
drm/nouveau/pm: convert to new-style nvkm_engine
drm/nouveau/gr: convert to new-style nvkm_engine
drm/nouveau/fifo: convert to new-style nvkm_engine
drm/nouveau/disp: convert to new-style nvkm_engine
drm/nouveau/dma: convert to new-style nvkm_engine
drm/nouveau/cipher: convert to new-style nvkm_engine
...
The copyright header in nvkm/engine/device/platform.c has been replaced
with the NVIDIA one from drm/nouveau_platform.c, as most of the actual
code is now theirs.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Doesn't fix any known issue, but best be safe in case control is handed
to us from firmware with these left enabled.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This ensures we have a valid mask of disabled engines before we start
trying to execute fini()/init() on the subdevs, potentially touching
devices that don't exist.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
