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Commit Graph

69 Commits

Author SHA1 Message Date
Nicolin Chen
4390e62260 ARM: imx6: Derive spdif clock from pll3_pfd3_454m
SPDIF can derive a TX clock for playback from one of its clock sources --
spdif root clock to match its supporting sample rates. So this patch set
the spdif root clock's parent to pll3_pfd3_454m since the pll3_pfd3_454m
can approximately meet its sample rate requirement.

Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-31 09:36:34 +08:00
Anson Huang
8202a3ce9c ARM: imx: clk: correct arm clock usecount
ARM clock is sourcing from pll1_sw, and pll1_sw can be either from
pll1_sys or step, so we should enable arm clock during clock
initialization instead of pll1_sys, otherwise, arm clock's usecount
would be incorrect and PLL1 will never be disabled even it is not
used.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-31 09:36:21 +08:00
Lothar Waßmann
ec9de6cd95 ARM: imx6q: add missing sentinel to divider table
The clk_enet_ref_table[] is missing a final empty entry as end of list
marker. Also make the existing markers more obvious.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-11-11 22:58:44 +08:00
Jiada Wang
9b3d423707 ARM: i.MX6q: fix the wrong parent of can_root clock
instead of pll3_usb_otg the parent of can_root clock
should be pll3_60m.

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-11-11 22:58:42 +08:00
Shawn Guo
9e8147bb5e ARM: imx6q: move low-power code out of clock driver
The LPM (Low Power Mode) code that currently sits in imx6q clock driver
will be reused by imx6sl.  Let's move it into pm-imx6q.c, so that we
can keep clock driver SoC specific and reuse pm-imx6q.c on imx6sl.

In order to avoid adding another ioremap for CCM block,
imx6q_pm_set_ccm_base() is created to let clock driver set up ccm_base
for pm code.

During the move, the unused CCGR macros get removed.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-10-21 09:39:24 +08:00
Sean Cross
74b8031307 ARM: imx6q: clock and Kconfig update for PCIe support
Update imx6q clock initialization and Kconfig for PCIe support.

Signed-off-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-10-21 09:15:08 +08:00
Sean Cross
bf22172158 ARM: imx: Add LVDS general-purpose clocks to i.MX6Q
The i.MX6 has two general-purpose LVDS clocks that can be driven
from a variety of sources.  This patch adds a mux and a gate for
both of these clocks.

Signed-off-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-10-21 09:15:07 +08:00
Shawn Guo
3f75978b37 ARM: imx6q: use common soc revision helpers
It calls imx_set_soc_revision() to set up soc revision in
imx6q_init_revision(), and replaces all the occurrences of
imx6q_revision() with common helper imx_get_soc_revision().

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-10-21 09:12:51 +08:00
Nicolin Chen
64990a4314 ARM: imx6q: Add pll4_audio_div to clock tree
There's a pll4_audio_div clock, an extra divider for pll4, missing
in current clock tree, thus add it.

Signed-off-by: Nicolin Chen <b42378@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-10-21 09:11:02 +08:00
Shawn Guo
a94f8ecb2f ARM: imx6q: remove board specific CLKO setup
The CLKO is widely used by imx6q board designs to clock audio codec.
Since most codecs accept 24 MHz frequency, let's initially set up CLKO
with OSC24M (cko <-- cko2 <-- osc).  Then those board specific CLKO
setup for audio codec can be removed.

The board dts files also need an update on cko reference in codec node.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22 23:29:34 +08:00
Shawn Guo
97245139a0 ARM: imx6q: add vdoa gate clock
Add the missing vdoa gate clock for imx6q.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22 23:20:41 +08:00
Shawn Guo
6cd622357d ARM: imx6q: add the missing cko output selection
The clock output on imx6q CCM_CLKO1 pad is not always cko1 clock, and
there is a multiplexer to select between cko1 and cko2.  Add this
missing selection as the clock cko.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22 23:20:39 +08:00
Shawn Guo
6526bb3cc5 ARM: imx6q: add cko2 clocks
It adds the missing cko2 clocks, including multiplexer, divider and
gate.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22 23:20:38 +08:00
Shawn Guo
1fa5007b3a ARM: imx6q: add spdif gate clock
It adds the missing spdif gate clock into imx6q clock driver.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22 23:20:37 +08:00
Liu Ying
dfd871442e ARM: imx6: change some clocks to fixup clocks
All the clocks controlled by the register 'CCM Serial Clock
Multiplexer Register 1' should be fixup clocks. This patch
changes those clocks from basic multiplexer or divider clocks
to fixup clocks.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16 13:11:25 +08:00
Philipp Zabel
a6fc9d194d ARM i.MX6DL: parent LDB DI clocks to PLL5 on i.MX6S/DL
i.MX6S/DL have the Video PLL post dividers fixed already in revision 1.0

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16 13:11:21 +08:00
Liu Ying
3b79cd15bf ARM: i.MX6Q: correct emi_sel clock muxing
The correct muxing for emi_sel clock should be
2b'00 - 396M PFD
2b'01 - PLL3
2b'10 - AXI clk root
2b'11 - 352M PFD

This patch corrects the muxing in the clock driver.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2013-07-15 08:28:08 +08:00
Nicolin Chen
e7eccc7e16 ARM: clk-imx6qdl: Add clko1 configuration for imx6qdl-sabresd
WM8962 needs 24MHz clock for its MCLK, so choose PLL4 as the parent of clko1.

Signed-off-by: Nicolin Chen <b42378@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17 15:45:16 +08:00
Shawn Guo
53bb71da1c ARM: imx6: use common of_clk_init() call to initialize clocks
Instead of explicitly calling clock initialization functions, we can
declare the functions with CLK_OF_DECLARE() and then call common
of_clk_init() to have them invoked properly.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17 15:45:14 +08:00
Shawn Guo
12aad63ca4 ARM: imx6q: call of_clk_init() to register fixed rate clocks
As the fixed rate clocks are defined in device tree, we can just call
of_clk_init() to register them.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17 15:45:14 +08:00
Dirk Behme
fbcb441217 ARM: i.MX6: clk: add different DualLite MLB clock config
The CCM_CBCMR register (address 0x02C4018) has different meaning
between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite.

Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the
i.MX6 Solo/DualLite reuses the gpu2d_core bits for the MLB clock
configuration.

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17 15:45:13 +08:00
Huang Shijie
9545b2ed68 ARM: imx6q: clk: add the eim_slow clock
Add the eim_slow clock, since the weim needs it.

Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17 15:45:12 +08:00
Jiada Wang
7f96d2d4d8 ARM: imx: disable pll8_mlb in mx6q_clks
The MLB PLL clock's operation doesn't fit for clock framework and
it should be handled internally in MLB driver.
Remove initialization of pll8_mlb clock device but leave its
declaration in mx6q_clks to avoid affecting imx6q clock numbering.

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17 15:45:11 +08:00
Dirk Behme
2e603ad984 ARM: i.MX6: clk: add i.MX6 DualLite differences
The CCM_CBCMR register (address 0x02C4018) has different meaning
between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite.

Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the
i.MX6 Solo/DualLite doesn't have a gpu3d_shader configuration and
moves the gpu2_core configuration at that place.

Handle these i.MX6 Quad/Dual vs. i.MX6 Solo/DualLite clock differences
by using cpu_is_mx6dl().

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17 15:45:09 +08:00
Anson Huang
a08b9bc586 ARM: imx: clk-imx6q: AXI clock select index is incorrect
The AXI clock mux should be as below:

00: periph;
01: pll2_pfd2_396m;
10: periph;
11: pll3_pfd1_540m;

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-03 13:47:12 +08:00
Jiada Wang
cc9a3e9994 ARM i.MX6q: fix for ldb_di_sels
As pll5_video_div has been introduced to represent the clock
generated from post-divider for video.
Instead of pll5_video, pll5_video_div should be proper root clock
for ldb_di_sel.

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-05-23 10:10:57 +08:00
Shawn Guo
de78a23d73 ARM: imx: fix typo in gpu3d_shader_sels
There is no clock pll2_pfd9_720m.  Instead it should be pll3_pfd0_720m.
Fix the typo in gpu3d_shader_sels.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2013-05-12 21:39:51 +08:00
Dirk Behme
0e574461c4 ARM i.MX6: correct MLB clock configuration
According to the i.MX6 Dual/Quad technical reference manual
(Figure 18-2. Clock Tree - Part 1) the MLB clock is directly
feed by the AXI_CLK_ROOT. This is called 'axi' in our code.

Note that the clock of the MLB IP block on the i.MX6 is completely
independent of the PLL8 (MLB PLL). The MLB PLL isn't responsible
for feeding the MLB IP block with a clock. Instead, it's used
internally by the MLB module to sync the bus clock in case the MLB
6-pin interface is enabled:

MediaLB Control 0 Register, MLB150_MLBC0[5], MLBPEN:
1 MediaLB 6-pin interface enabled. MLB PLL and MLB PHY is enabled in this case.

I.e. the PLL8 MLB PLL has to be handled by the MLB driver and isn't needed
for clocking the MLB module itself.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jiada Wang <Jiada_Wang@mentor.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-05-12 21:35:29 +08:00
Philipp Zabel
72cd7447e7 ARM i.MX6q: Fix periph_clk2_sel and periph2_clk2_sel clocks
The periph_clk2_sel mux can be set to pll3, osc/pll1_ref_clk, or osc/
pll2_burn_in_clk. The periph2_clk2_sel mux can be set to pll3 or pll2.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-05-12 21:35:22 +08:00
Shawn Guo
3c03a2fed6 ARM: imx: add initial imx6dl support
The i.MX6 DualLite/Solo is another i.MX6 family SoC, which is highly
compatible with i.MX6 Quad/Dual.  And that's why we choose to support
it using imx6q code with cpu_is_imx6dl() check when necessary.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12 19:28:15 +08:00
Philipp Zabel
32f3b8da22 ARM i.MX6q: set the LDB serial clock parent to the video PLL
On i.MX6q revision 1.1 and later, set the video PLL as parent for
the LDB clock branch. On revision 1.0, the video PLL is useless
due to missing dividers, so keep the default parent (mmdc_ch1_axi).

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12 19:28:13 +08:00
Philipp Zabel
2df1d026ed ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1
Query silicon revision to determine clock tree and add post
dividers for newer revisions.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12 19:28:12 +08:00
Philipp Zabel
d19dacb732 ARM i.MX6q: fix ldb di divider and selector clocks
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12 19:01:45 +08:00
Anson Huang
263475d4e0 ARM: imx: enable RBC to support anatop LPM mode
RBC is to control whether some ANATOP sub modules
can enter lpm mode when SOC is into STOP mode, if
RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP
will have below behaviors:

1. Digital LDOs(CORE, SOC and PU) are bypassed;
2. Analog LDOs(1P1, 2P5, 3P0) are disabled;

As the 2P5 is necessary for DRAM IO pre-drive in
STOP mode, so we need to enable weak 2P5 in STOP
mode when 2P5 LDO is disabled.

For RBC settings, there are some rules as below
due to hardware design:

1. All interrupts must be masked during operating
   RBC registers;
2. At least 2 CKIL(32K) cycles is needed after the
   RBC setting is changed.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12 19:01:43 +08:00
Anson Huang
e7b82d645d ARM: imx: enable periphery well bias for suspend
Enable periphery charge pump for well biasing
at suspend to reduce periphery leakage.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-12 19:01:43 +08:00
Dirk Behme
e8094b2c17 ARM i.MX6: Fix ldb_di clock selection
According to the recent i.MX6 Quad technical reference manual, mode 0x4 (100b)
of the CCM_CS2DCR register (address 0x020C402C) bits [11-9] and [14-12] select
the PLL3 clock, and not the PLL3 PFD1 540M clock. In our code, the PLL3 root
clock is named 'pll3_usb_otg', select this instead of the 540M clock.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-09 19:48:09 +08:00
Shawn Guo
2bb4b70b1d ARM: imx: provide twd clock lookup from device tree
While booting from device tree, imx6q used to provide twd clock lookup
by calling clk_register_clkdev() in clock driver.  However, the commit
bd60345 (ARM: use device tree to get smp_twd clock) forces DT boot to
look up the clock from device tree.  It causes the failure below when
twd driver tries to get the clock, and hence kernel has to calibrate the
local timer frequency.

 smp_twd: clock not found -2
 ...
 Calibrating local timer... 396.13MHz.

Fix the regression by providing twd clock lookup from device tree, and
remove the unused twd clk_register_clkdev() call from clock driver.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-09 19:46:31 +08:00
Shawn Guo
395816623d ARM: imx: pll1_sys should be an initial on clk
We always boot from PLL1, so let's have pll1_sys in the clks_init_on
list to have clk prepare/enable use count match the hardware status,
so that drivers managing pll1_sys like cpufreq can get the use count
right from the start.

Reported-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-03-11 10:44:40 +08:00
Arnd Bergmann
4a9226a3d1 Merge branch 'imx/cpuidle' into late/dt
This resolves one non-obvious merge conflict between the imx cpuidle
patches and the imx DT changes for 3.9.

Conflicts:
	arch/arm/mach-imx/mach-imx6q.c

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-02-19 17:22:34 +01:00
Peter Chen
a5120e89e7 ARM i.MX6: change mxs usbphy clock usage
This mxs usbphy is only needs to be on after system boots
up, and software never needs to control it anymore.
Meanwhile, usbphy's parent needs to be notified if usb
is suspend or not. So we design below mxs usbphy usage:

- usbphy1_gate and usbphy2_gate:
Their parents are dummy clock, we only needs to enable
it after system boots up.
- usbphy1 and usbphy2
Usage reserved bit for this clock, in that case, the refcount
will be updated, but without hardware changing.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-10 23:25:45 +08:00
Shawn Guo
e5f9dec8ff ARM: imx6q: support WAIT mode using cpuidle
Add WAIT mode (ARM core clock gating) support to imx6q cpuidle driver.
As WAIT mode is broken on imx6q TO 1.0 and 1.1, it only enables the
support for revision 1.2 with chicken bit set.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-01-30 21:09:31 +08:00
Shawn Guo
cd4842f558 ARM: imx: remove unused imx6q_clock_map_io()
imx6q_clock_map_io() becomes an empty function since imx6q clock driver
is moved to common clock framework.  It's used nowhere now.  Remove it.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-01-29 14:05:39 +08:00
Shawn Guo
83ae20981a ARM: imx: correct low-power mode setting
The hardware reset value of bit CCM_CLPCR_LPM enables WAIT mode
(WAIT_UNCLOCKED) by default.  However this is undesirable because
WAIT mode should only be enabled when there is a driver managing
ARM clock gating.  Correct the initial power mode to WAIT_CLOCKED
(disable WAIT mode).  While at it, the power mode after resuming
is also set back to WAIT_CLOCKED from STOP_POWER_OFF.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-01-14 22:19:48 +08:00
Linus Torvalds
db5b0ae007 ARM: arm-soc: device tree conversions and enablement
Continued device tree conversion and enablement across a number of
 platforms; Kirkwood, tegra, i.MX, Exynos, zynq and a couple of other
 smaller series as well.
 
 ux500 has seen continued conversion for platforms. Several platforms have
 seen pinctrl-via-devicetree conversions for simpler multiplatform. Tegra
 is adding data for new devices/drivers, and Exynos has a bunch of new
 bindings and devices added as well.
 
 So, pretty much the same progression in the right direction as the last
 few releases.
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Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree conversions and enablement from Olof Johansson:
 "Continued device tree conversion and enablement across a number of
  platforms; Kirkwood, tegra, i.MX, Exynos, zynq and a couple of other
  smaller series as well.

  ux500 has seen continued conversion for platforms.  Several platforms
  have seen pinctrl-via-devicetree conversions for simpler
  multiplatform.  Tegra is adding data for new devices/drivers, and
  Exynos has a bunch of new bindings and devices added as well.

  So, pretty much the same progression in the right direction as the
  last few releases."

Fix up conflicts as per Olof.

* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (185 commits)
  ARM: ux500: Rename dbx500 cpufreq code to be more generic
  ARM: dts: add missing ux500 device trees
  ARM: ux500: Stop registering the PCM driver from platform code
  ARM: ux500: Move board specific GPIO info out to subordinate DTS files
  ARM: ux500: Disable the MMCI gpio-regulator by default
  ARM: Kirkwood: remove kirkwood_ehci_init() from new boards
  ARM: Kirkwood: Add support LED of OpenBlocks A6
  ARM: Kirkwood: Convert to EHCI via DT for OpenBlocks A6
  ARM: kirkwood: Add NAND partiton map for OpenBlocks A6
  ARM: kirkwood: Add support second I2C bus and RTC on OpenBlocks A6
  ARM: kirkwood: Add support DT of second I2C bus
  ARM: kirkwood: Convert mplcec4 board to pinctrl
  ARM: Kirkwood: Convert km_kirkwood to pinctrl
  ARM: Kirkwood: support 98DX412x kirkwoods with pinctrl
  ARM: Kirkwood: Convert IX2-200 to pinctrl.
  ARM: Kirkwood: Convert lsxl boards to pinctrl.
  ARM: Kirkwood: Convert ib62x0 to pinctrl.
  ARM: Kirkwood: Convert GoFlex Net to pinctrl.
  ARM: Kirkwood: Convert dreamplug to pinctrl.
  ARM: Kirkwood: Convert dockstar to pinctrl.
  ...
2012-12-13 10:39:26 -08:00
Sascha Hauer
2b254693be ARM i.MX6: remove gate_mask from pllv3
Now that the additional enable bits in the enet PLL are handled
as gates, the gate_mask is identical for all plls. Remove the
gate_mask from the code and use the BM_PLL_ENABLE bit for
enabling/disabling the PLL.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
2012-11-22 15:32:39 +01:00
Sascha Hauer
7a04092c73 ARM i.MX6: Fix ethernet PLL clocks
In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz
and has different outputs. Only the enet reference clock is implemented. This
patch changes the PLL so that it outputs 500MHz and adds the additional outputs
as dividers. This now matches the datasheet which says:

> This PLL synthesizes a low jitter clock from 24 MHz reference clock.
> The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are:
>  • Ref_PCIe = 125 MHz
>  • Ref_SATA = 100 MHz
>  • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
2012-11-22 15:32:33 +01:00
Sascha Hauer
13861701a8 ARM i.MX6: rename PLLs according to datasheet
In recent reference manuals the PLLs were renumbered. PLL8 now is
PLL6 and vice versa. Change the code according to the reference
manual to avoid confusion.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
2012-11-22 15:32:24 +01:00
Steffen Trumtrar
80be8aa31e ARM i.MX6: fix ldb_di_sel mux
This adds the mmdc_ch1 as a possible parent for the ldb_di clk.
According to the datasheet, this clock can be selected at this mux.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
2012-11-16 16:33:25 +01:00
Shawn Guo
d90df97863 ARM: imx: enable cpufreq for imx6q
It enables cpufreq support for imx6q with generic cpufreq-cpu0 driver.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-11-16 14:18:53 +08:00
Shawn Guo
e3372474cf ARM: imx: include common.h rather than mach/common.h
Rename mach-imx/include/mach/common.h to mach-imx/common.h and update
all users to include common.h rather than mach/common.h.

It also removes an unneeded inclusion to common.h in
mach-imx/devices/devices.c.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-10-15 10:03:10 +08:00