2
0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-18 18:23:53 +08:00
Commit Graph

2 Commits

Author SHA1 Message Date
Thomas Gleixner
b886d83c5b treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 441
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation version 2 of the license

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 315 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Armijn Hemel <armijn@tjaldur.nl>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190531190115.503150771@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05 17:37:17 +02:00
Robert Jarzmik
73317712d9 pinctrl: pxa: pxa2xx: add pin control skeleton
Add a pincontrol driver for pxa2xx architecture, encompassing all pxa25x
and pxa27x variants. This is only the pin muxing part of the driver.

One specific consideration is also the memory space (MMIO), which is
intertwined with the GPIO registers. To make things worse, the GPIO
direction register also affect pin muxing, as it chooses the "kind" of
pin, ie. the 4 output functions or 4 input functions.

The mapping between pinctrl notions and PXA Technical Reference Manual
is as follows :
 - a pin is obviously a pin
 - a group is also a pin, ie. group P101 is the pin 101
 - a mux function is an alternate function
   (ie. gpio-in, gpio-out, MMCLK, BTRTS, etc ...)

The individual architecture (pxa27x, pxa25x) instantiate a pin control
by providing a table of pins, each pin being provided a list of
PXA_FUNCTION (alternate functions).

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10 16:10:16 +01:00