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Commit Graph

6 Commits

Author SHA1 Message Date
Michal Simek
e67f04c918 spi: cadence: Remove .owner field for driver
There is no need to init .owner field.

Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"

This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-08-16 17:11:32 -05:00
Mark Brown
d1345c524e Merge remote-tracking branches 'spi/topic/adi-v3', 'spi/topic/atmel', 'spi/topic/cleanup' and 'spi/topic/davinci' into spi-next 2014-08-04 17:21:04 +01:00
Lars-Peter Clausen
b48b9488e3 spi: cadence: Configure SPI clock in the prepare_message() callback
Currently the cadence SPI driver does the SPI clock configuration (setup CPOL
and CPHA) in the prepare_transfer_hardware() callback. The
prepare_transfer_hardware() callback is only called though when the controller
transitions from a idle state to a non-idle state. Such a transitions happens
when the message queue goes from empty to non-empty. If multiple messages from
different SPI slaves with different clock settings are in the message queue the
clock settings will not be properly updated when switching from one slave device
to another. Instead do the updating of the clock configuration in the
prepare_message() callback which will be called for each individual message.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-07-11 14:39:26 +01:00
Lars-Peter Clausen
a39e65e9cc spi: cadence: Make sure that clock polarity changes are applied
It seems that the cadence SPI controller does not immediately change the clock
polarity setting when writing the CR register. Instead the change is delayed
until the next transfer starts. This happens after the chip select line has
already been asserted. As a result the first transfer after a clock polarity
change will generate spurious clock transitions which typically results in the
SPI slave not being able to properly understand the message. Toggling the ER
register seems to cause the SPI controller to apply the clock polarity changes,
so implement this as a workaround to fix the issue.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-07-11 14:39:26 +01:00
Jingoo Han
f7f994a4c5 spi: cadence: Make of_device_id array const
Make of_device_id array const, because all OF functions handle
it as const.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Harini Katakam <harinik@xilinx.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-06-06 12:37:41 +01:00
Harini Katakam
c474b38665 spi: Add driver for Cadence SPI controller
Add driver for Cadence SPI controller. This is used in Xilinx Zynq.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-04-14 21:00:28 +01:00