Some header files were reordered while I was at it.
The only device currently registered is the ATLAS PMIC (MC13783) chip.
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit splits the support code for LogicPD's mx31lite hardware
into module and board specific parts.
This introduces a new mandatory coreparam called 'mx31lite_baseboard'
which specifies the base board support to use. For now, only the LiteKit
development board is supported, and developers of own boards are
encouraged to use that as reference.
The UART support moved to the board code.
Some comments were amended along the way.
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The address area of the NFC in the i.MX35 silicon is much larger than 4k.
Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
According to Russell King handle_edge_irq is only useful for "edge-based
inputs where the controller does not remember transitions with the input
masked."
So using handle_edge_irq unconditionally for both edge and level irqs is
wrong. Testing showed that the controller does remember transitions
while the interrupt is masked. So use handle_level_irq unconditionally.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ARC USB OTG Core has support for accessing ULPI tranceivers
through so called ULPI viewports. Export a set of function for use with
the USB OTG framework.
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Cc: Greg Kroah-Hartman <gregkh@suse.de>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Cc: linux-usb@vger.kernel.org
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We have two mt9t031 cameras that have a muxed bus on the robot.
Only one is currently initialized because of limitations in
soc_camera that should be removed later.
Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We get rid of CTS/RTS lines on uart0 on our platform.
This is the port we use as main kernel console. We do not
want it to be blocking because of CTS/RTS signals, not allowing
the system to boot or print messages.
However we often use it with a bluetooth module needing CTS/RTS
lines as backup login in case of trouble. To be able to use it,
we assert CTS low so that the module can always send chars.
Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The RTC chip Seiko Instruments S-35390A is connected to the Application
Processor over the second bus i2c with the hard coded address 0x30.
Signed-off-by: Alberto Panizzo <maramaopercheseimorto@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This add pin allocation an device registration for the
second bus i2c.
Signed-off-by: Alberto Panizzo <maramaopercheseimorto@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Armadillo500 Correct bus length for SMSC9118 on board chip.
The SMSC9118 network chip is connected to the data bus with a 16 bit
interface, not 32 as early suggested.
Signed-off-by: Alberto Panizzo <maramaopercheseimorto@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There are two low active Buttons on boards.
This patch connect those to the Input Subsystem over gpio-keys driver.
Signed-off-by: Alberto Panizzo <maramaopercheseimorto@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The chip is actually located on the module, not on the base board. But
other base boards might add more SPI devices, so the spi_board_info
struct must be separated from the module code.
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support for the two SPI busses found on the lilly1131 module.
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The module does not use these pins for I2C but for SPI.
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* 'for-linus' of git://github.com/at91linux/linux-2.6-at91:
at91: at91sam9g45 family: identify several chip versions
avr32: add two new at91 to cpu.h definition
cpu_is_xxx() macros are identifying generic at91sam9g45 chip. This patch adds
the capacity to differentiate Engineering Samples and final lots through the
inclusion of at91_cpu_fully_identify() and the related chip IDs with chip
version field preserved.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Somme common drivers will need those at91 cpu_is_xxx() definitions. As
at91sam9g10 and at91sam9g45 are on the way to linus' tree, here is the patch
that adds those chips to cpu.h in AVR32 architecture.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
MIPS: O32: Fix ppoll
MIPS: Oprofile: Rename cpu_type from godson2 to loongson2
MIPS: Alchemy: Fix hang with high-frequency edge interrupts
MIPS: TXx9: Fix spi-baseclk value
MIPS: bcm63xx: Set the correct BCM3302 CPU name
MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store
MIPS: Avoid potential hazard on Context register
MIPS: Octeon: Use lockless interrupt controller operations when possible.
MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache
MIPS: SMTC: Avoid queing multiple reschedule IPIs
MIPS: GCMP: Avoid accessing registers when they are not present
MIPS: GIC: Random fixes and enhancements.
MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start
MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
MIPS: SPRAM: Clean up support code a little
MIPS: 1004K: Enable SPRAM support.
MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4
MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.
MIPS: MTI: Fix accesses to device registers on MIPS boards
...
