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Commit Graph

220 Commits

Author SHA1 Message Date
Yijing Wang
7ec725b2d5 PCI: tegra: Save MSI controller in pci_sys_data
Save MSI controller in pci_sys_data instead of assigning MSI controller
pointer to every PCI bus in .add_bus().

[bhelgaas: use struct tegra_msi.chip, not ctrl]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-21 09:33:45 -07:00
Yijing Wang
c2791b8069 PCI/MSI: Rename "struct msi_chip" to "struct msi_controller"
"msi_chip" isn't very descriptive, so rename it to "msi_controller".  That
tells a little more about what it does and is already used in device tree
bindings.

No functional change.

[bhelgaas: changelog, change *only* the struct name so it's reviewable]
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-12 07:49:38 -07:00
Linus Torvalds
80213c03c4 PCI changes for the v3.18 merge window:
Enumeration
     - Check Vendor ID only for Config Request Retry Status (Rajat Jain)
     - Enable Config Request Retry Status when supported (Rajat Jain)
     - Add generic domain handling (Catalin Marinas)
     - Generate uppercase hex for modalias interface class (Ricardo Ribalda Delgado)
 
   Resource management
     - Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources() (Yinghai Lu)
     - Increase IBM ipr SAS Crocodile BARs to at least system page size (Douglas Lehr)
 
   PCI device hotplug
     - Prevent NULL dereference during pciehp probe (Andreas Noever)
     - Move _HPP & _HPX handling into core (Bjorn Helgaas)
     - Apply _HPP to PCIe devices as well as PCI (Bjorn Helgaas)
     - Apply _HPP/_HPX to display devices (Bjorn Helgaas)
     - Preserve SERR & PARITY settings when applying _HPP/_HPX (Bjorn Helgaas)
     - Preserve MPS and MRRS settings when applying _HPP/_HPX (Bjorn Helgaas)
     - Apply _HPP/_HPX to all devices, not just hot-added ones (Bjorn Helgaas)
     - Fix wait time in pciehp timeout message (Yinghai Lu)
     - Add more pciehp Slot Control debug output (Yinghai Lu)
     - Stop disabling pciehp notifications during init (Yinghai Lu)
 
   MSI
     - Remove arch_msi_check_device() (Alexander Gordeev)
     - Rename pci_msi_check_device() to pci_msi_supported() (Alexander Gordeev)
     - Move D0 check into pci_msi_check_device() (Alexander Gordeev)
     - Remove unused kobject from struct msi_desc (Yijing Wang)
     - Remove "pos" from the struct msi_desc msi_attrib (Yijing Wang)
     - Add "msi_bus" sysfs MSI/MSI-X control for endpoints (Yijing Wang)
     - Use __get_cached_msi_msg() instead of get_cached_msi_msg() (Yijing Wang)
     - Use __read_msi_msg() instead of read_msi_msg() (Yijing Wang)
     - Use __write_msi_msg() instead of write_msi_msg() (Yijing Wang)
 
   Power management
     - Drop unused runtime PM support code for PCIe ports (Rafael J.  Wysocki)
     - Allow PCI devices to be put into D3cold during system suspend (Rafael J. Wysocki)
 
   AER
     - Add additional AER error strings (Gong Chen)
     - Make <linux/aer.h> standalone includable (Thierry Reding)
 
   Virtualization
     - Add ACS quirk for Solarflare SFC9120 & SFC9140 (Alex Williamson)
     - Add ACS quirk for Intel 10G NICs (Alex Williamson)
     - Add ACS quirk for AMD A88X southbridge (Marti Raudsepp)
     - Remove unused pci_find_upstream_pcie_bridge(), pci_get_dma_source() (Alex Williamson)
     - Add device flag helpers (Ethan Zhao)
     - Assume all Mellanox devices have broken INTx masking (Gavin Shan)
 
   Generic host bridge driver
     - Fix ioport_map() for !CONFIG_GENERIC_IOMAP (Liviu Dudau)
     - Add pci_register_io_range() and pci_pio_to_address() (Liviu Dudau)
     - Define PCI_IOBASE as the base of virtual PCI IO space (Liviu Dudau)
     - Fix the conversion of IO ranges into IO resources (Liviu Dudau)
     - Add pci_get_new_domain_nr() and of_get_pci_domain_nr() (Liviu Dudau)
     - Add support for parsing PCI host bridge resources from DT (Liviu Dudau)
     - Add pci_remap_iospace() to map bus I/O resources (Liviu Dudau)
     - Add arm64 architectural support for PCI (Liviu Dudau)
 
   APM X-Gene
     - Add APM X-Gene PCIe driver (Tanmay Inamdar)
     - Add arm64 DT APM X-Gene PCIe device tree nodes (Tanmay Inamdar)
 
   Freescale i.MX6
     - Probe in module_init(), not fs_initcall() (Lucas Stach)
     - Delay enabling reference clock for SS until it stabilizes (Tim Harvey)
 
   Marvell MVEBU
     - Fix uninitialized variable in mvebu_get_tgt_attr() (Thomas Petazzoni)
 
   NVIDIA Tegra
     - Make sure the PCIe PLL is really reset (Eric Yuen)
     - Add error path tegra_msi_teardown_irq() cleanup (Jisheng Zhang)
     - Fix extended configuration space mapping (Peter Daifuku)
     - Implement resource hierarchy (Thierry Reding)
     - Clear CLKREQ# enable on port disable (Thierry Reding)
     - Add Tegra124 support (Thierry Reding)
 
   ST Microelectronics SPEAr13xx
     - Pass config resource through reg property (Pratyush Anand)
 
   Synopsys DesignWare
     - Use NULL instead of false (Fabio Estevam)
     - Parse bus-range property from devicetree (Lucas Stach)
     - Use pci_create_root_bus() instead of pci_scan_root_bus() (Lucas Stach)
     - Remove pci_assign_unassigned_resources() (Lucas Stach)
     - Check private_data validity in single place (Lucas Stach)
     - Setup and clear exactly one MSI at a time (Lucas Stach)
     - Remove open-coded bitmap operations (Lucas Stach)
     - Fix configuration base address when using 'reg' (Minghuan Lian)
     - Fix IO resource end address calculation (Minghuan Lian)
     - Rename get_msi_data() to get_msi_addr() (Minghuan Lian)
     - Add get_msi_data() to pcie_host_ops (Minghuan Lian)
     - Add support for v3.65 hardware (Murali Karicheri)
     - Fold struct pcie_port_info into struct pcie_port (Pratyush Anand)
 
   TI Keystone
     - Add TI Keystone PCIe driver (Murali Karicheri)
     - Limit MRSS for all downstream devices (Murali Karicheri)
     - Assume controller is already in RC mode (Murali Karicheri)
     - Set device ID based on SoC to support multiple ports (Murali Karicheri)
 
   Xilinx AXI
     - Add Xilinx AXI PCIe driver (Srikanth Thokala)
     - Fix xilinx_pcie_assign_msi() return value test (Dan Carpenter)
 
   Miscellaneous
     - Clean up whitespace (Quentin Lambert)
     - Remove assignments from "if" conditions (Quentin Lambert)
     - Move PCI_VENDOR_ID_VMWARE to pci_ids.h (Francesco Ruggeri)
     - x86: Mark DMI tables as initialization data (Mathias Krause)
     - x86: Move __init annotation to the correct place (Mathias Krause)
     - x86: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst (Mathias Krause)
     - x86: Constify pci_mmcfg_probes[] array (Mathias Krause)
     - x86: Mark PCI BIOS initialization code as such (Mathias Krause)
     - Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters (Megan Kamiya)
     - Remove unnecessary variable in pci_add_dynid() (Tobias Klauser)
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Merge tag 'pci-v3.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI updates from Bjorn Helgaas:
 "The interesting things here are:

   - Turn on Config Request Retry Status Software Visibility.  This
     caused hangs last time, but we included a fix this time.
   - Rework PCI device configuration to use _HPP/_HPX more aggressively
   - Allow PCI devices to be put into D3cold during system suspend
   - Add arm64 PCI support
   - Add APM X-Gene host bridge driver
   - Add TI Keystone host bridge driver
   - Add Xilinx AXI host bridge driver

  More detailed summary:

  Enumeration
    - Check Vendor ID only for Config Request Retry Status (Rajat Jain)
    - Enable Config Request Retry Status when supported (Rajat Jain)
    - Add generic domain handling (Catalin Marinas)
    - Generate uppercase hex for modalias interface class (Ricardo Ribalda Delgado)

  Resource management
    - Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources() (Yinghai Lu)
    - Increase IBM ipr SAS Crocodile BARs to at least system page size (Douglas Lehr)

  PCI device hotplug
    - Prevent NULL dereference during pciehp probe (Andreas Noever)
    - Move _HPP & _HPX handling into core (Bjorn Helgaas)
    - Apply _HPP to PCIe devices as well as PCI (Bjorn Helgaas)
    - Apply _HPP/_HPX to display devices (Bjorn Helgaas)
    - Preserve SERR & PARITY settings when applying _HPP/_HPX (Bjorn Helgaas)
    - Preserve MPS and MRRS settings when applying _HPP/_HPX (Bjorn Helgaas)
    - Apply _HPP/_HPX to all devices, not just hot-added ones (Bjorn Helgaas)
    - Fix wait time in pciehp timeout message (Yinghai Lu)
    - Add more pciehp Slot Control debug output (Yinghai Lu)
    - Stop disabling pciehp notifications during init (Yinghai Lu)

  MSI
    - Remove arch_msi_check_device() (Alexander Gordeev)
    - Rename pci_msi_check_device() to pci_msi_supported() (Alexander Gordeev)
    - Move D0 check into pci_msi_check_device() (Alexander Gordeev)
    - Remove unused kobject from struct msi_desc (Yijing Wang)
    - Remove "pos" from the struct msi_desc msi_attrib (Yijing Wang)
    - Add "msi_bus" sysfs MSI/MSI-X control for endpoints (Yijing Wang)
    - Use __get_cached_msi_msg() instead of get_cached_msi_msg() (Yijing Wang)
    - Use __read_msi_msg() instead of read_msi_msg() (Yijing Wang)
    - Use __write_msi_msg() instead of write_msi_msg() (Yijing Wang)

  Power management
    - Drop unused runtime PM support code for PCIe ports (Rafael J.  Wysocki)
    - Allow PCI devices to be put into D3cold during system suspend (Rafael J. Wysocki)

  AER
    - Add additional AER error strings (Gong Chen)
    - Make <linux/aer.h> standalone includable (Thierry Reding)

  Virtualization
    - Add ACS quirk for Solarflare SFC9120 & SFC9140 (Alex Williamson)
    - Add ACS quirk for Intel 10G NICs (Alex Williamson)
    - Add ACS quirk for AMD A88X southbridge (Marti Raudsepp)
    - Remove unused pci_find_upstream_pcie_bridge(), pci_get_dma_source() (Alex Williamson)
    - Add device flag helpers (Ethan Zhao)
    - Assume all Mellanox devices have broken INTx masking (Gavin Shan)

  Generic host bridge driver
    - Fix ioport_map() for !CONFIG_GENERIC_IOMAP (Liviu Dudau)
    - Add pci_register_io_range() and pci_pio_to_address() (Liviu Dudau)
    - Define PCI_IOBASE as the base of virtual PCI IO space (Liviu Dudau)
    - Fix the conversion of IO ranges into IO resources (Liviu Dudau)
    - Add pci_get_new_domain_nr() and of_get_pci_domain_nr() (Liviu Dudau)
    - Add support for parsing PCI host bridge resources from DT (Liviu Dudau)
    - Add pci_remap_iospace() to map bus I/O resources (Liviu Dudau)
    - Add arm64 architectural support for PCI (Liviu Dudau)

  APM X-Gene
    - Add APM X-Gene PCIe driver (Tanmay Inamdar)
    - Add arm64 DT APM X-Gene PCIe device tree nodes (Tanmay Inamdar)

  Freescale i.MX6
    - Probe in module_init(), not fs_initcall() (Lucas Stach)
    - Delay enabling reference clock for SS until it stabilizes (Tim Harvey)

  Marvell MVEBU
    - Fix uninitialized variable in mvebu_get_tgt_attr() (Thomas Petazzoni)

  NVIDIA Tegra
    - Make sure the PCIe PLL is really reset (Eric Yuen)
    - Add error path tegra_msi_teardown_irq() cleanup (Jisheng Zhang)
    - Fix extended configuration space mapping (Peter Daifuku)
    - Implement resource hierarchy (Thierry Reding)
    - Clear CLKREQ# enable on port disable (Thierry Reding)
    - Add Tegra124 support (Thierry Reding)

  ST Microelectronics SPEAr13xx
    - Pass config resource through reg property (Pratyush Anand)

  Synopsys DesignWare
    - Use NULL instead of false (Fabio Estevam)
    - Parse bus-range property from devicetree (Lucas Stach)
    - Use pci_create_root_bus() instead of pci_scan_root_bus() (Lucas Stach)
    - Remove pci_assign_unassigned_resources() (Lucas Stach)
    - Check private_data validity in single place (Lucas Stach)
    - Setup and clear exactly one MSI at a time (Lucas Stach)
    - Remove open-coded bitmap operations (Lucas Stach)
    - Fix configuration base address when using 'reg' (Minghuan Lian)
    - Fix IO resource end address calculation (Minghuan Lian)
    - Rename get_msi_data() to get_msi_addr() (Minghuan Lian)
    - Add get_msi_data() to pcie_host_ops (Minghuan Lian)
    - Add support for v3.65 hardware (Murali Karicheri)
    - Fold struct pcie_port_info into struct pcie_port (Pratyush Anand)

  TI Keystone
    - Add TI Keystone PCIe driver (Murali Karicheri)
    - Limit MRSS for all downstream devices (Murali Karicheri)
    - Assume controller is already in RC mode (Murali Karicheri)
    - Set device ID based on SoC to support multiple ports (Murali Karicheri)

  Xilinx AXI
    - Add Xilinx AXI PCIe driver (Srikanth Thokala)
    - Fix xilinx_pcie_assign_msi() return value test (Dan Carpenter)

  Miscellaneous
    - Clean up whitespace (Quentin Lambert)
    - Remove assignments from "if" conditions (Quentin Lambert)
    - Move PCI_VENDOR_ID_VMWARE to pci_ids.h (Francesco Ruggeri)
    - x86: Mark DMI tables as initialization data (Mathias Krause)
    - x86: Move __init annotation to the correct place (Mathias Krause)
    - x86: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst (Mathias Krause)
    - x86: Constify pci_mmcfg_probes[] array (Mathias Krause)
    - x86: Mark PCI BIOS initialization code as such (Mathias Krause)
    - Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters (Megan Kamiya)
    - Remove unnecessary variable in pci_add_dynid() (Tobias Klauser)"

* tag 'pci-v3.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (109 commits)
  arm64: dts: Add APM X-Gene PCIe device tree nodes
  PCI: Add ACS quirk for AMD A88X southbridge devices
  PCI: xgene: Add APM X-Gene PCIe driver
  PCI: designware: Remove open-coded bitmap operations
  PCI/MSI: Remove unnecessary temporary variable
  PCI/MSI: Use __write_msi_msg() instead of write_msi_msg()
  MSI/powerpc: Use __read_msi_msg() instead of read_msi_msg()
  PCI/MSI: Use __get_cached_msi_msg() instead of get_cached_msi_msg()
  PCI/MSI: Add "msi_bus" sysfs MSI/MSI-X control for endpoints
  PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib
  PCI/MSI: Remove unused kobject from struct msi_desc
  PCI/MSI: Rename pci_msi_check_device() to pci_msi_supported()
  PCI/MSI: Move D0 check into pci_msi_check_device()
  PCI/MSI: Remove arch_msi_check_device()
  irqchip: armada-370-xp: Remove arch_msi_check_device()
  PCI/MSI/PPC: Remove arch_msi_check_device()
  arm64: Add architectural support for PCI
  PCI: Add pci_remap_iospace() to map bus I/O resources
  of/pci: Add support for parsing PCI host bridge resources from DT
  of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()
  ...

Conflicts:
	arch/arm64/boot/dts/apm-storm.dtsi
2014-10-09 15:03:49 -04:00
Bjorn Helgaas
f92d9ee3ab Merge branch 'pci/host-xgene' into next
* pci/host-xgene:
  arm64: dts: Add APM X-Gene PCIe device tree nodes
  PCI: xgene: Add APM X-Gene PCIe driver

Conflicts:
	drivers/pci/host/Kconfig
	drivers/pci/host/Makefile
2014-10-06 09:59:15 -06:00
Bjorn Helgaas
b9c9c2558b Merge branch 'pci/host-designware' into next
* pci/host-designware:
  PCI: designware: Remove open-coded bitmap operations
  PCI: designware: Setup and clear exactly one MSI at a time

Conflicts:
	drivers/pci/host/pcie-designware.c
2014-10-01 16:45:01 -06:00
Tanmay Inamdar
5f6b6ccdbe PCI: xgene: Add APM X-Gene PCIe driver
Add the AppliedMicro X-Gene SOC PCIe host controller driver.  The X-Gene
PCIe controller supports up to 8 lanes and GEN3 speed.  The X-Gene SOC
supports up to 5 PCIe ports.

[bhelgaas: folded in MAINTAINERS and bindings updates]
Tested-by: Ming Lei <ming.lei@canonical.com>
Tested-by: Dann Frazier <dann.frazier@canonical.com>
Signed-off-by: Tanmay Inamdar <tinamdar@apm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> (driver)
2014-10-01 13:01:35 -06:00
Lucas Stach
c8df6ac945 PCI: designware: Remove open-coded bitmap operations
Replace them by using the standard kernel bitmap ops.  No functional
change, but makes the code a lot cleaner.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
2014-10-01 12:40:21 -06:00
Bjorn Helgaas
359c660e99 Merge branch 'pci/msi' into next
* pci/msi:
  PCI/MSI: Remove unnecessary temporary variable
  PCI/MSI: Use __write_msi_msg() instead of write_msi_msg()
  MSI/powerpc: Use __read_msi_msg() instead of read_msi_msg()
  PCI/MSI: Use __get_cached_msi_msg() instead of get_cached_msi_msg()
  PCI/MSI: Add "msi_bus" sysfs MSI/MSI-X control for endpoints
  PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib
  PCI/MSI: Remove unused kobject from struct msi_desc
  PCI/MSI: Rename pci_msi_check_device() to pci_msi_supported()
  PCI/MSI: Move D0 check into pci_msi_check_device()
  PCI/MSI: Remove arch_msi_check_device()
  irqchip: armada-370-xp: Remove arch_msi_check_device()
  PCI/MSI/PPC: Remove arch_msi_check_device()

Conflicts:
	drivers/pci/host/pcie-designware.c
2014-10-01 12:31:46 -06:00
Bjorn Helgaas
07a7cbd3b8 Merge branch 'pci/host-generic' into next
* pci/host-generic:
  arm64: Add architectural support for PCI
  PCI: Add pci_remap_iospace() to map bus I/O resources
  of/pci: Add support for parsing PCI host bridge resources from DT
  of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()
  PCI: Add generic domain handling
  of/pci: Fix the conversion of IO ranges into IO resources
  of/pci: Move of_pci_range_to_resource() to of/address.c
  ARM: Define PCI_IOBASE as the base of virtual PCI IO space
  of/pci: Add pci_register_io_range() and pci_pio_to_address()
  asm-generic/io.h: Fix ioport_map() for !CONFIG_GENERIC_IOMAP

Conflicts:
	drivers/pci/host/pci-tegra.c
2014-10-01 12:31:23 -06:00
Yijing Wang
48c3c38f00 PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib
"msi_attrib.pos" is only used for MSI (not MSI-X), and we already cache the
MSI capability offset in "dev->msi_cap".

Remove "pos" from the struct msi_attrib and use "dev->msi_cap" directly.

[bhelgaas: changelog, fix whitespace]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-10-01 12:21:23 -06:00
Liviu Dudau
0b0b0893d4 of/pci: Fix the conversion of IO ranges into IO resources
The ranges property for a host bridge controller in DT describes the
mapping between the PCI bus address and the CPU physical address.  The
resources framework however expects that the IO resources start at a pseudo
"port" address 0 (zero) and have a maximum size of IO_SPACE_LIMIT.  The
conversion from PCI ranges to resources failed to take that into account,
returning a CPU physical address instead of a port number.

Also fix all the drivers that depend on the old behaviour by fetching the
CPU physical address based on the port number where it is being needed.

Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Simon Horman <horms@verge.net.au>
CC: Catalin Marinas <catalin.marinas@arm.com>
2014-09-30 17:08:40 -06:00
Lucas Stach
91f8ae823f PCI: designware: Setup and clear exactly one MSI at a time
The setup_irq function is supposed to set up exactly one MSI IRQ.  Multiple
IRQ setup is handled differently, to respect the choices made by the upper
layers.

Also only clear one MSI IRQ at a time; the PCI core will call into this
function multiple times if it has to tear down more than one MSI IRQ.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
2014-09-30 15:08:58 -06:00
Bjorn Helgaas
1104528bc7 Merge branch 'pci/host-designware' into next
* pci/host-designware:
  PCI: designware: Add get_msi_data() to pcie_host_ops
  PCI: designware: Rename get_msi_data() to get_msi_addr()
  PCI: designware: Fix IO resource end address calculation
  PCI: designware: Fix configuration base address when using 'reg'
  PCI: designware: Use NULL instead of false

[bhelgaas: Fixup keystone for "PCI: designware: Rename get_msi_data() to
get_msi_addr()"]
2014-09-29 13:24:24 -06:00
Bjorn Helgaas
b1bf295778 Merge branches 'pci/host-mvebu' and 'pci/host-spear' into next
* pci/host-mvebu:
  PCI: mvebu: Fix uninitialized variable in mvebu_get_tgt_attr()

* pci/host-spear:
  PCI: spear: Pass config resource through reg property
2014-09-25 13:51:55 -06:00
Minghuan Lian
24832b4de3 PCI: designware: Add get_msi_data() to pcie_host_ops
Add a struct pcie_host_ops .get_msi_data() method for platforms to return
their special MSI message data.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
2014-09-24 07:07:43 -06:00
Minghuan Lian
450e344e42 PCI: designware: Rename get_msi_data() to get_msi_addr()
The struct pcie_host_ops .get_msi_data() method returns the MSI message
address.  To accurately express its purpose, rename it to .get_msi_addr().

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
2014-09-24 07:04:39 -06:00
Minghuan Lian
0c61ea77cc PCI: designware: Fix IO resource end address calculation
End address should be equal to start_addr + size - 1.  Fix PCI IO resource
end address calculation.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
2014-09-24 07:04:01 -06:00
Minghuan Lian
ec98e9ab6f PCI: designware: Fix configuration base address when using 'reg'
The code has calculated cfg0_base and cfg1_base when parsing 'reg' or
'ranges' property of PCI DTS node, so remove duplicate calculation.  When
using 'reg', resource cfg is not used, so this code computed an incorrect
configuration base.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
2014-09-24 07:01:47 -06:00
Fabio Estevam
9f0dbe087b PCI: designware: Use NULL instead of false
of_get_address() expects pointers in the third and fourth parameters.

Pass NULL in order to fix the following sparse warnings:

  drivers/pci/host/pcie-designware.c:433:51: warning: Using plain integer as NULL pointer
  drivers/pci/host/pcie-designware.c:433:58: warning: Using plain integer as NULL pointer

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Jingoo Han <jg1.han@samsung.com>
2014-09-22 14:52:07 -06:00
Thomas Petazzoni
56fab6e189 PCI: mvebu: Fix uninitialized variable in mvebu_get_tgt_attr()
Geert Uytterhoeven reported a warning when building pci-mvebu:

  drivers/pci/host/pci-mvebu.c: In function 'mvebu_get_tgt_attr':
  drivers/pci/host/pci-mvebu.c:887:39: warning: 'rtype' may be used uninitialized in this function [-Wmaybe-uninitialized]
     if (slot == PCI_SLOT(devfn) && type == rtype) {
					 ^

And indeed, the code of mvebu_get_tgt_attr() may lead to the usage of rtype
when being uninitialized, even though it would only happen if we had
entries other than I/O space and 32 bits memory space.

This commit fixes that by simply skipping the current DT range being
considered, if it doesn't match the resource type we're looking for.

Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v3.12+
2014-09-22 14:40:17 -06:00
Pratyush Anand
65aaae245a PCI: spear: Pass config resource through reg property
PCIe configuration space should be passed through reg property, rather than
through ranges property.  This patch does the correction for SPEAr13XX
SOCs.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-22 14:19:30 -06:00
Bjorn Helgaas
ef39ab79f7 Merge branches 'pci/host-designware', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-tegra' and 'pci/host-xilinx' into next
* pci/host-designware:
  PCI: designware: Fold struct pcie_port_info into struct pcie_port

* pci/host-imx6:
  PCI: imx6: Delay enabling reference clock for SS until it stabilizes

* pci/host-keystone:
  PCI: keystone: Set device ID based on SoC to support multiple ports
  PCI: keystone: Assume controller is already in RC mode
  PCI: keystone: Limit MRSS for all downstream devices

* pci/host-tegra:
  PCI: tegra: Add Tegra124 support
  PCI: tegra: Make sure the PCIe PLL is really reset
  PCI: tegra: Fix extended configuration space mapping
  PCI: tegra: Clear CLKREQ# enable on port disable

* pci/host-xilinx:
  PCI: xilinx: Fix xilinx_pcie_assign_msi() return value test
2014-09-22 12:31:10 -06:00
Linus Torvalds
b29f83aa8b PCI updates for v3.17:
Enumeration
     - Don't default exclusively to first video device (Bruno Prémont)
 
   PCI device hotplug
     - Remove "no hotplug settings from platform" warning (Bjorn Helgaas)
     - Add pci_ignore_hotplug() for VGA switcheroo (Bjorn Helgaas)
 
   Freescale i.MX6
     - Put LTSSM in "Detect" state before disabling (Lucas Stach)
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Merge tag 'pci-v3.17-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI fixes from Bjorn Helgaas:
 "These fix:

   - Boot video device detection on dual-GPU Apple systems
   - Hotplug fiascos on VGA switcheroo with radeon & nouveau drivers
   - Boot hang on Freescale i.MX6 systems
   - Excessive "no hotplug settings from platform" warnings

  In particular:

  Enumeration
    - Don't default exclusively to first video device (Bruno Prémont)

  PCI device hotplug
    - Remove "no hotplug settings from platform" warning (Bjorn Helgaas)
    - Add pci_ignore_hotplug() for VGA switcheroo (Bjorn Helgaas)

  Freescale i.MX6
    - Put LTSSM in "Detect" state before disabling (Lucas Stach)"

* tag 'pci-v3.17-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  vgaarb: Drop obsolete #ifndef
  vgaarb: Don't default exclusively to first video device with mem+io
  ACPIPHP / radeon / nouveau: Remove acpi_bus_no_hotplug()
  PCI: Remove "no hotplug settings from platform" warning
  PCI: Add pci_ignore_hotplug() to ignore hotplug events for a device
  PCI: imx6: Put LTSSM in "Detect" state before disabling it
  MAINTAINERS: Add Lucas Stach as co-maintainer for i.MX6 PCI driver
2014-09-19 10:50:30 -07:00
Dan Carpenter
f9dd0ce67d PCI: xilinx: Fix xilinx_pcie_assign_msi() return value test
We should be testing "hwirq" instead of "irq".  "irq" is unsigned so it's
never less than zero.  Also it's uninitialized.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Srikanth Thokala <sthokal@xilinx.com>
2014-09-16 17:41:52 -06:00
Thierry Reding
7f1f054b3f PCI: tegra: Add Tegra124 support
The PCIe controller on Tegra124 has two root ports that can be used in a
x4/x1 or x2/x1 configuration and can run at PCIe 2.0 link speeds (up to
5 GT/s).  The PHY programming has been moved into a separate controller, so
the driver now needs to request an external PHY referenced using the device
tree.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16 16:55:49 -06:00
Eric Yuen
ec73276204 PCI: tegra: Make sure the PCIe PLL is really reset
Depending on the prior state of the controller, the PLL reset may not be
pulsed.  Clear the register bit and set it after a small delay to ensure
that the PLL is really reset.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Eric Yuen <eyuen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16 16:55:33 -06:00
Peter Daifuku
8d41794c6f PCI: tegra: Fix extended configuration space mapping
The 16 chunks of 64 KiB that need to be stitched together to make up the
configuration space for one bus (1 MiB) are located 24 bits (== 16 MiB)
apart in physical address space.  This is determined by the start of the
extended register field (bits 24-27) in the physical mapping.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16 16:55:10 -06:00
Thierry Reding
0d20d62192 PCI: tegra: Clear CLKREQ# enable on port disable
When a root port is disabled, disable the CLKREQ# signal if available.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16 16:54:05 -06:00
Murali Karicheri
8665a482db PCI: keystone: Set device ID based on SoC to support multiple ports
K2E SoC has two PCI ports.  The SATA controller is connected to second PCI
port (port 1).  To support multiple port handling in Keystone PCI driver,
read the PCI device ID dynamically by iomap/read/unmap during probe and
save it in driver's private data and update it in host init code.  The PCI
device ID field in the RC's config space is not filled by default by the
hardware and has to be updated by the PCI driver by reading the same from
the SoC register indicated by reg index #2 in DT bindings.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16 15:45:46 -06:00
Murali Karicheri
4455efc908 PCI: keystone: Assume controller is already in RC mode
Keystone PCI hardware supports both RC and EP modes and devcfg register has
bits to boot strap the device to either of these modes.  It seems proper to
add this functionality to the boot loader rather than in the driver as
device will be operating in either mode, not both any time.  Currently the
driver supports only RC mode and hence register configuration in the driver
is not needed and the driver can assume the hardware is in RC mode.

Also update the DT documentation accordingly.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-09-16 15:45:45 -06:00
Murali Karicheri
c15982dfa8 PCI: keystone: Limit MRSS for all downstream devices
Keystone PCIe controller has a limitation that memory read request size
must not exceed 256 bytes.  This is a hardware limitation.  Add a quirk to
force this limit on all downstream devices by updating MRRS.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16 15:31:21 -06:00
Pratyush Anand
adf70fc087 PCI: designware: Fold struct pcie_port_info into struct pcie_port
The struct pcie_port_info doesn't contain any exclusive information
compared to other elements of struct pcie_port.  So, keeping a separate
structure does not seem very logical.  Therefore remove this struct and
embed its elements directly into struct pcie_port.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-05 17:48:54 -06:00
Tim Harvey
3fce0e882f PCI: imx6: Delay enabling reference clock for SS until it stabilizes
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is
running at the appropriate frequency.

Delay enabling the reference clock for the SS function until it has
stabilized.  This prevents a high link failure rate (>5%) on certain IMX6
boards at various temperatures.

[bhelgaas: reword changelog slightly]
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
2014-09-05 11:16:41 -06:00
Bjorn Helgaas
a2351efeb3 Merge branches 'pci/misc', 'pci/pm', 'pci/host-designware', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-tegra' and 'pci/host-xilinx' into next
* pci/misc:
  PCI/AER: Make <linux/aer.h> standalone includable
  PCI: Remove unnecessary variable in pci_add_dynid()

* pci/pm:
  PCI/PM: Allow PCI devices to be put into D3cold during system suspend
  PCI/PM: Drop unused runtime PM support code for PCIe ports

* pci/host-designware:
  PCI: designware: Check private_data validity in single place
  PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
  PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
  PCI: designware: Parse bus-range property from devicetree
  PCI: designware: Add support for v3.65 hardware

* pci/host-imx6:
  PCI: imx6: Probe in module_init(), not fs_initcall()
  PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
  PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
  PCI: designware: Parse bus-range property from devicetree
  PCI: imx6: Put LTSSM in "Detect" state before disabling it
  MAINTAINERS: Add Lucas Stach as co-maintainer for i.MX6 PCI driver
  PCI: designware: Add support for v3.65 hardware

* pci/host-keystone:
  PCI: keystone: Add TI Keystone PCIe driver
  PCI: designware: Add support for v3.65 hardware

* pci/host-tegra:
  PCI: tegra: Implement a proper resource hierarchy
  PCI: tegra: Add missing cleanup in error path and tegra_msi_teardown_irq()
  resources: Add device-managed request/release_resource()

* pci/host-xilinx:
  PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver

Conflicts:
	drivers/pci/host/Kconfig
	drivers/pci/host/Makefile
2014-09-05 10:57:20 -06:00
Lucas Stach
84a263f394 PCI: designware: Check private_data validity in single place
The driver had checks for this sprinkled all over.  As we call
sys_to_pcie() before every instance of this check, we can move the
check to this single location to make things clear.

Removing the statements after BUG[_ON]() is safe as the kernel is halted at
this point anyway.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-05 09:37:55 -06:00
Lucas Stach
61da50da90 PCI: imx6: Probe in module_init(), not fs_initcall()
This effectively reverts f216f57ffe ("PCI: imx6: Probe the PCIe in
fs_initcall()") as the resource allocation issue that prevented the driver
from working properly at module_initcall level is now fixed in
pcie-designware.c.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Richard Zhu <r65037@freescale.com>
2014-09-05 09:36:48 -06:00
Bjorn Helgaas
c346a54a6f Merge branch 'pci/host-designware' into pci/host-imx6
* pci/host-designware:
  PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
  PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
  PCI: designware: Parse bus-range property from devicetree
  PCI: designware: Add support for v3.65 hardware
2014-09-05 09:28:08 -06:00
Lucas Stach
8ddebc4103 PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
The pci_common_init_dev() call right before will already handle the device
resource allocation, so this call was a no-op.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-04 14:58:48 -06:00
Lucas Stach
92483df2ba PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
Use pci_create_root_bus() similar to other PCI host controller drivers.

The main problem with pci_scan_root_bus() is that it not only creates the
root bus, but also activates all devices on the bus.  This triggers PCI
device driver probe routines, which fail because resources haven't been
allocated.

To work around this we made sure that the host controller driver is probed
early and finishes resource allocation before any other device drivers are
registered.  Switching to pci_create_root_bus() allows us to get rid of
this special handling.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-04 14:58:48 -06:00
Lucas Stach
4f2ebe0059 PCI: designware: Parse bus-range property from devicetree
This allows to explicitly specify the covered bus numbers in the
devicetree, which will come in handy once we see a SoC with more than one
PCIe host controller instance.

Previously the driver relied on the behavior of pci_scan_root_bus() to fill
in a range of 0x00-0xff if no valid range was found.  We fall back to the
same range if no valid DT entry was found to keep backwards compatibility,
but now do it explicitly.

[bhelgaas: use %pR in error message to avoid duplication]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-04 14:58:48 -06:00
Murali Karicheri
0c4ffcfe1f PCI: keystone: Add TI Keystone PCIe driver
The Keystone PCIe controller is based on v3.65 version of the Designware
h/w.  Main differences are:

    1. No ATU support
    2. Legacy and MSI IRQ functions are implemented in application register
       space
    3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side.

All of the application register space handing code is organized into
pci-keystone-dw.c and the functions are called from pci-keystone.c to
implement PCI controller driver.  Also add necessary DT documentation and
update the MAINTAINERS file for the driver.

[bhelgaas: spelling and whitespace fixes]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Mohit Kumar <mohit.kumar@st.com>
CC: Pratyush Anand <pratyush.anand@st.com>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
2014-09-04 14:58:21 -06:00
Thierry Reding
41534e5378 PCI: tegra: Implement a proper resource hierarchy
Currently the resource hierarchy generated from the PCIe host bridge is
completely flat:

    $ cat /proc/iomem
    00000000-00000fff : /pcie-controller@00003000/pci@1,0
    00003000-000037ff : pads
    00003800-000039ff : afi
    10000000-1fffffff : cs
    28000000-28003fff : r8169
    28004000-28004fff : r8169
    ...

The host bridge driver doesn't request all the resources that are used.
Windows allocated to each of the root ports aren't tracked, so there is no
way for resources allocated to individual devices to be matched up with the
correct parent resource by the PCI core.

This patch addresses this in two steps.  It first takes the union of all
regions associated with the PCIe host bridge (control registers, root port
registers, configuration space, I/O and prefetchable as well as non-
prefetchable memory regions) and uses it as the new root of the resource
hierarchy.

Subsequently, regions are allocated from within this new root resource so
that the resource tree looks much more like what's expected:

    # cat /proc/iomem
    00000000-3fffffff : /pcie-controller@00003000
      00000000-00000fff : /pcie-controller@00003000/pci@1,0
      00003000-000037ff : pads
      00003800-000039ff : afi
      10000000-1fffffff : cs
      20000000-27ffffff : non-prefetchable
      28000000-3fffffff : prefetchable
        28000000-280fffff : PCI Bus 0000:01
          28000000-28003fff : 0000:01:00.0
            28000000-28003fff : r8169
          28004000-28004fff : 0000:01:00.0
            28004000-28004fff : r8169
    ...

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-04 14:49:26 -06:00
Jisheng Zhang
019fa46ebc PCI: tegra: Add missing cleanup in error path and tegra_msi_teardown_irq()
We should call tegra_msi_free() to free the MSI bit if irq_create_mapping()
fails.  And we need to dispose the IRQ mapping during IRQ teardown.

[bhelgaas: made irqd_to_hwirq() change suggested by Thierry]
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
2014-09-04 14:49:24 -06:00
Lucas Stach
3e3e406e38 PCI: imx6: Put LTSSM in "Detect" state before disabling it
This fixes a boot hang observed when the bootloader already enabled the
PCIe link for its own use.  The fundamental problem is that Freescale
forgot to wire up the core reset, so software doesn't have a sane way to
get the core into a defined state.

According to the DW PCIe core reference manual, configuration of the core
may only happen when the LTSSM is disabled, so this is one of the first
things we need to do.  Apparently this isn't safe to do when the LTSSM is in
any state other than "detect" as we observe an instant machine hang when
trying to do so while the link is already up.

As a workaround, force LTSSM into detect state right before hitting the
disable switch.  There is still a race window because the LTSSM may
transition out of "detect" before we can disable it, but it's the best
we can do for now.

[bhelgaas: mention race window]
Link: http://lkml.kernel.org/r/1406830565-23450-3-git-send-email-l.stach@pengutronix.de
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-09-04 07:32:21 -06:00
Srikanth Thokala
8961def568 PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP.

[bhelgaas: minor whitespace fixes]
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-09-04 07:30:14 -06:00
Linus Torvalds
f16c15a0e0 PCI update for v3.17:
ST Microelectronics SPEAr13xx
     - Remove module option (Sachin Kamat)
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Merge tag 'pci-v3.17-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI fix from Bjorn Helgaas:
 "This fixes an ARM allmodconfig build problem:

  Remove module option for ST Microelectronics SPEAr13xx"

* tag 'pci-v3.17-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: spear: Remove module option
2014-09-03 08:45:48 -07:00
Murali Karicheri
b14a3d1784 PCI: designware: Add support for v3.65 hardware
The Keystone PCI controller is based on v3.65 DesignWare hardware.  This
version differs from newer versions of the hardware in functional areas
discussed below that make it necessary to change dw_pcie_host_init() to
support v3.65 based PCI controller.

    1. No support for ATU port.  Any ATU-specific resource handling code is
       to be bypassed for v3.65 h/w.

    2. MSI controller uses application space to implement MSI and 32 MSI
       interrupts are multiplexed over 8 IRQs to the host.  Hence the code
       to process MSI IRQ needs to be different.  This patch allows
       platform driver to provide its own irq_domain_ops ptr to
       irq_domain_add_linear() through an API callback from the DesignWare
       core driver.

    3. MSI interrupt generation requires EP to write to the RC's
       application register.  So enhance the driver to allow setup of
       inbound access to MSI IRQ register as a post scan bus API callback.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
CC: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
2014-09-02 17:25:41 -06:00
Linus Torvalds
f17a6f7859 PCI changes for v3.17 (part 3):
Marvell MVEBU
     - Remove ARCH_KIRKWOOD dependency (Andrew Lunn)
 
   NVIDIA Tegra
     - Add debugfs support (Thierry Reding)
 
   Synopsys DesignWare
     - Look for configuration space in 'reg', not 'ranges' (Kishon Vijay Abraham I)
     - Program ATU with untranslated address (Kishon Vijay Abraham I)
     - Add config access-related pcie_host_ops for v3.65 hardware (Murali Karicheri)
     - Add MSI-related pcie_host_ops for v3.65 hardware (Murali Karicheri)
 
   TI DRA7xx
     - Add TI DR7xx PCIe driver (Kishon Vijay Abraham I)
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Merge tag 'pci-v3.17-changes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI changes from Bjorn Helgaas:
 "Marvell MVEBU
    - Remove ARCH_KIRKWOOD dependency (Andrew Lunn)

  NVIDIA Tegra
    - Add debugfs support (Thierry Reding)

  Synopsys DesignWare
    - Look for configuration space in 'reg', not 'ranges' (Kishon Vijay Abraham I)
    - Program ATU with untranslated address (Kishon Vijay Abraham I)
    - Add config access-related pcie_host_ops for v3.65 hardware (Murali Karicheri)
    - Add MSI-related pcie_host_ops for v3.65 hardware (Murali Karicheri)

  TI DRA7xx
    - Add TI DR7xx PCIe driver (Kishon Vijay Abraham I)"

* tag 'pci-v3.17-changes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: designware: Add MSI-related pcie_host_ops for v3.65 hardware
  PCI: designware: Add config access-related pcie_host_ops for v3.65 hardware
  PCI: dra7xx: Add TI DRA7xx PCIe driver
  PCI: designware: Program ATU with untranslated address
  PCI: designware: Look for configuration space in 'reg', not 'ranges'
  PCI: tegra: Add debugfs support
  PCI: mvebu: Remove ARCH_KIRKWOOD dependency
2014-08-19 09:45:31 -05:00
Sachin Kamat
8d7004a690 PCI: spear: Remove module option
We get the following error when built as a module. Though the general fix
would be in this case to export the below mentioned symbols, considering
that dw_pcie_host_init() is marked with __init and other PCI drivers do not
support modular build, I have disabled building this driver as a module
too.

  ERROR: "dw_pcie_host_init" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  ERROR: "dw_handle_msi_irq" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  ERROR: "dw_pcie_msi_init" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  ERROR: "dw_pcie_cfg_write" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  ERROR: "dw_pcie_cfg_read" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  ERROR: "dw_pcie_setup_rc" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  ERROR: "dw_pcie_link_up" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  make[1]: *** [__modpost] Error 1
  make: *** [modules] Error 2

Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2014-08-17 22:09:16 -06:00
Linus Torvalds
10c8e05620 ARM: SoC driver changes for 3.17
A handful of driver-related changes. We've had a bunch of them going in through
 other branches as well, so it's only a part of what we really have this release.
 
 Larger pieces are:
 
 * Removal of a now unused PWM driver for atmel
   - This includes AVR32 changes that have been appropriately acked.
 * Performance counter support for the arm CCN interconnect
 * OMAP mailbox driver cleanups and consolidation
 * PCI and SATA PHY drivers for SPEAr 13xx platforms
 * Redefinition (with backwards compatibility!) of PCI DT bindings for Tegra to
   better model regulators/power.
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Merge tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver changes from Olof Johansson:
 "A handful of driver-related changes.  We've had a bunch of them going
  in through other branches as well, so it's only a part of what we
  really have this release.

  Larger pieces are:

   - Removal of a now unused PWM driver for atmel
     [ This includes AVR32 changes that have been appropriately acked ]
   - Performance counter support for the arm CCN interconnect
   - OMAP mailbox driver cleanups and consolidation
   - PCI and SATA PHY drivers for SPEAr 13xx platforms
   - Redefinition (with backwards compatibility!) of PCI DT bindings for
     Tegra to better model regulators/power"

Note: this merge also fixes up the semantic conflict with the new
calling convention for devm_phy_create(), see commit f0ed817638 ("phy:
core: Let node ptr of PHY point to PHY and not of PHY provider") that
came in through Greg's USB tree.

Semantic merge patch by Stephen Rothwell <sfr@canb.auug.org.au> through
the next tree.

* tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits)
  bus: arm-ccn: Fix error handling at event allocation
  mailbox/omap: add a parent structure for every IP instance
  mailbox/omap: remove the private mailbox structure
  mailbox/omap: consolidate OMAP mailbox driver
  mailbox/omap: simplify the fifo assignment by using macros
  mailbox/omap: remove omap_mbox_type_t from mailbox ops
  mailbox/omap: remove OMAP1 mailbox driver
  mailbox/omap: use devm_* interfaces
  bus: ARM CCN: add PERF_EVENTS dependency
  bus: ARM CCN PMU driver
  PCI: spear: Remove spear13xx_pcie_remove()
  PCI: spear: Fix Section mismatch compilation warning for probe()
  ARM: tegra: Remove legacy PCIe power supply properties
  PCI: tegra: Remove deprecated power supply properties
  PCI: tegra: Implement accurate power supply scheme
  ARM: SPEAr13xx: Update defconfigs
  ARM: SPEAr13xx: Add pcie and miphy DT nodes
  ARM: SPEAr13xx: Add bindings and dt node for misc block
  ARM: SPEAr13xx: Fix static mapping table
  phy: Add drivers for PCIe and SATA phy on SPEAr13xx
  ...
2014-08-08 11:34:32 -07:00