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2 Commits

Author SHA1 Message Date
Linus Walleij
d1ef28900d PCI: faraday: Add clock bindings 
The Faraday FTPCI100 controller has two clock ports, PCLK and PCICLK.  Add
bindings for these two clocks so we can assign them in the device tree.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
 2017-07-02 18:42:35 -05:00
Linus Walleij
1f12d3c11f PCI: Add DT bindings for Faraday Technology PCI Host Bridge 
Add device tree bindings for the Faraday technology PCI Host Bridge.  This
IP is found in the Storlink/Storm/Cortina Gemini SoC platform.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
CC: Janos Laube <janos.dev@gmail.com>
CC: Paulius Zaleckas <paulius.zaleckas@gmail.com>
CC: Hans Ulli Kroll <ulli.kroll@googlemail.com>
CC: Florian Fainelli <f.fainelli@gmail.com>
CC: devicetree@vger.kernel.org
CC: Feng-Hsin Chiang <john453@faraday-tech.com>
CC: Greentime Hu <green.hu@gmail.com>
 2017-03-24 10:30:29 -05:00