Niklas Söderlund
e6e3558626
clk: renesas: r8a7796: Add VIN clocks
...
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-07 15:16:18 +01:00
Niklas Söderlund
5fccac6d94
clk: renesas: r8a7796: Add CSI2 clocks
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Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-07 15:16:17 +01:00
Geert Uytterhoeven
a05de66ea6
Merge branch 'rcar-rst' into clk-renesas-for-v4.10
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soc: renesas: Add R-Car RST driver for obtaining mode pin state
2016-11-02 20:53:26 +01:00
Geert Uytterhoeven
05972d48d2
clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driver
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Obtain the values of the mode pins from the R-Car RST driver, which
relies on the presence in DT of a device node for the RST module.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-11-02 20:43:56 +01:00
Laurent Pinchart
dbdcc4f996
clk: renesas: r8a7796: Add DU and LVDS clocks
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Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:40:08 +01:00
Laurent Pinchart
88ddc1f8e3
clk: renesas: r8a7796: Add VSP clocks
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Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:40:07 +01:00
Laurent Pinchart
f4407a6e26
clk: renesas: r8a7796: Add FCP clocks
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Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:40:07 +01:00
Ramesh Shanmugasundaram
cf31bc71c0
clk: renesas: r8a7796: Add DRIF clock
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This patch adds DRIF module clocks for r8a7796 SoC.
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-02 20:39:55 +01:00
Ulrich Hecht
878f8baa02
clk: renesas: r8a7796: Add I2C clocks
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Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:21 +02:00
Ulrich Hecht
28aa831949
clk: renesas: r8a7796: Add HSCIF clocks
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Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:21 +02:00
Ulrich Hecht
951456c37d
clk: renesas: r8a7796: Add SCIF clocks
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Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:20 +02:00
Ulrich Hecht
cf8fe97cad
clk: renesas: r8a7796: Add SYS-DMAC clocks
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Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:20 +02:00
Bui Duc Phuc
5fad71f58f
clk: renesas: r8a7796: Add CMT clocks
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This patch adds CMT module clocks for r8a7796 SoC.
Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-12 11:08:01 +02:00
Laurent Pinchart
5576df81d2
clk: renesas: r8a7796: Add RAVB clock
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Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-12 11:08:00 +02:00
Khiem Nguyen
5086b0d6ce
clk: renesas: r8a7796: Add THS/TSC clock
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Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-05 14:16:25 +02:00
Simon Horman
0749698133
clk: renesas: r8a7796: Add SDIF clocks
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This patch adds SDIF clocks for R8A7796 SoC.
Based on work by Ai Kyuse and Yoshihiro Shimoda for the r8a7795 SoC.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-23 10:30:41 +02:00
Takeshi Kihara
4e09508a89
clk: renesas: r8a7796: Add GPIO clocks
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Add GPIO clocks for the R8A7796 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-19 09:38:40 +02:00
Geert Uytterhoeven
b51d527501
clk: renesas: r8a7796: Add watchdog module clock
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Add the module clock for the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-09 09:53:47 +02:00
Geert Uytterhoeven
2570d4005d
clk: renesas: r8a7796: Add watchdog core clocks
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Add all core clocks related to the Watchdog Timer (WDT) controller on
the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-09 09:53:47 +02:00
Geert Uytterhoeven
e4e2d7c388
clk: renesas: cpg-mssr: Add support for R-Car M3-W
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Initial support for R-Car M3-W (r8a7796), including basic core clocks,
and SCIF2 (console) and INTC-AP (GIC) module clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-06 11:58:35 +02:00
