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Commit Graph

100 Commits

Author SHA1 Message Date
Lucas Stach
697035c6b8 drm/panel: simple: Add support for AUO G133HAN01
This adds support for the AU Optronics G133HAN01 13.3" LVDS FullHD TFT
LCD panel, which can be supported by the simple panel driver.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-06 17:06:31 +01:00
Lucas Stach
4ae13e4868 drm/panel: simple: Add more properties to Innolux G121I1-L01
Convert from a single mode to display timings, which allow to describe
the minimum/maximium blanking and clock rates, add enable/disable delays
and provide the bus format.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-06 16:55:44 +01:00
zain wang
5466a631b2 drm/panel: simple: Add bits-per-component for Sharp LQ123P1JX31
The Sharp LQ123P1JX31 panel support 8 bits per component.

Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-06 16:52:32 +01:00
Chen-Yu Tsai
230c5b4423 drm/panel: simple: Check against num_timings when setting preferred for timing
In the loop on .timings, we should check .num_timings to see if it's the
only mode specified, not .num_modes, which should be used with .modes.

Fixes: cda553725c ("drm/panel: simple: Set appropriate mode type")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-06 16:47:07 +01:00
Randy Li
2cb35c802a drm/panel: Add support for Chunghwa CLAA070WP03XG panel
The Chunghwa CLAA070WP03XG is a 7" 1280x800 panel, which can be
supported by the simple panel driver.

Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-06 16:43:55 +01:00
Fabien Lahoudere
05ec0e4501 drm/panel: simple: Add NVD9128 as a simple panel
Add New Vision Display 7.0" 800 RGB x 480 TFT LCD panel

Signed-off-by: Fabien Lahoudere <fabien.lahoudere@collabora.co.uk>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-10-19 14:35:18 +02:00
Haixia Shi
7ee933a1d5 drm/panel: simple: Add support for AUO T215HVN01
The AUO T215HVN01 is a 21.5" FHD (1920x1080) color TFT LCD panel.

This panel is used on the Acer Chromebase 21.5-inch All-in-One (DC221HQ).

Link to spec: http://www.udmgroup.com/ftp/T215HVN01.0.pdf

v2: fix alphabetical order
v3: remove minor revision suffix ".0" and add link to spec
v4: add dt-binding documentation

Signed-off-by: Haixia Shi <hshi@chromium.org>
Tested-by: Haixia Shi <hshi@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-10-19 14:33:16 +02:00
Gustaf Lindström
0f9cdd743f drm/panel: simple: Add support for Sharp LQ150X1LG11 panels
The Sharp 15" LQ150X1LG11 panel is an XGA TFT LCD panel.

The simple-panel driver is used to get support for essential
functionality of the panel.

Signed-off-by: Gustaf Lindström <gl@axentia.se>
Signed-off-by: Peter Rosin <peda@axentia.se>
[treding@nvidia.com: change .bpc from 8 to 6]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-10-19 14:32:15 +02:00
Jonathan Liu
5c2a7c6be1 drm/panel: simple: Fix bus_format for the Olimex LCD-OLinuXino-4.3TS
The format is RGB888 not RGB666.

Signed-off-by: Jonathan Liu <net147@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-09-16 17:19:35 +02:00
Brian Norris
c46b924bb2 drm/panel: simple-panel: Add delay timings for Starry KR122EA0SRA
Taking our cue from commit a42f6e3f8f ("drm/panel: simple: Add delay
timing for Sharp LQ123P1JX31"), let's add timings:

 .prepare = t1 + t3
 .enable = t7
 .unprepare = t11 + 12

Without this, the panel may not be given enough time to come up.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-09-16 17:17:59 +02:00
Marek Vasut
e0932f9d7b drm/panel: simple: Fix bus flags for Ortustech com43h4m85ulc
This display expects DE pin and data lines to be active high, add the
necessary flags.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Thierry Reding <treding@nvidia.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-09-16 17:09:35 +02:00
Michael Olbrich
1e29b840af drm/panel: simple: Add Innolux G101ICE-L01 panel
This patch adds support for Innolux Corporation 10.1" G101ICE-L01 WXGA
(1280x800) LVDS panel to the simple-panel driver.

Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-09-16 17:05:34 +02:00
Yakir Yang
a42f6e3f8f drm/panel: simple: Add delay timing for Sharp LQ123P1JX31
According to page 16 of the Sharp LQ123P1JX31 datasheet, we need to add
the missing delay timing. Panel prepare time should be t1 (0.5 to 10 ms)
plus t3 (0 to 100 ms), panel enable time should equal to t7 (0 to 50 ms)
and panel unprepare time should be t11 (1 to 50 ms) plus t12 (500 ms).

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24 16:19:48 +02:00
Douglas Anderson
9bb34c4c73 drm/panel: simple: Add support for Starry KR122EA0SRA panel
The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected
using eDP interfaces.

EDID shows:
  Detailed mode: Clock 147.000 MHz, 263 mm x 164 mm
                 1920 1936 1952 1984 hborder 0
                 1200 1215 1217 1235 vborder 0
                 -hsync -vsync
  Manufacturer-specified data, tag 15
  ASCII string: STARRY
  ASCII string: KR122EA0SRA

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11 14:30:43 +02:00
Joshua Clayton
592aa02bd1 drm/panel: simple: Add support for Sharp LQ101K1LY04
Add simple-panel support for the  Sharp LQ101K1LY04, which  is a 10"
WXGA (1280x800) LVDS panel.

Signed-off-by: Joshua Clayton <stillcompiling@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11 14:30:41 +02:00
Yakir Yang
c5ece40249 drm/panel: simple: Add support for LG LP079QX1-SP0V panel
The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and
32 pins eDP interface. This module supports 1536x2048 mode.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11 14:30:41 +02:00
Yakir Yang
739c7de9a1 drm/panel: simple: Add support for Sharp LQ123P1JX31 panel
The Sharp LQ123P1JX31 is an 12.3", 2400x1600 TFT-LCD panel connected
using eDP interfaces.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11 14:30:39 +02:00
Yakir Yang
0330eaf390 drm/panel: simple: Add support for Samsung LSN122DL01-C01 panel
The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel
connected using eDP interfaces.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11 14:30:38 +02:00
Yakir Yang
0355dde26e drm/panel: simple: Add support for LG LP097QX1-SPA1 panel
The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel
connected using eDP interfaces.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11 14:30:37 +02:00
Thierry Reding
e4aa34289e drm/panel: simple: Update backlight state property
Some backlight drivers ignore the power property and instead only use
the state property. Fixup the panel driver to set the state property in
addition to the power property.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11 14:30:35 +02:00
Thierry Reding
dc982832bf drm/panel: simple: Remove gratuitous blank line
This blank line was introduced in commit c8521969de ("drm/panel:
simple: Add support for BOE TV080WUM-NL0"), likely by mistake.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-13 08:30:48 +02:00
Thierry Reding
8159884644 drm/panel: simple: Fix a couple of physical sizes
Both the Innolux ZJ070NA-01P and Samsung LTN101NT05 were listing the
horizontal and vertical resolutions in the size.width and size.height
fields, whereas they should contain the physical dimensions of the
panel.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-10 15:33:13 +02:00
Bhuvanchandra DV
227e4f4079 drm/panel: simple: Add support for TPK U.S.A. LLC Fusion 7" and 10.1" panels
Add support for TPK U.S.A. LLC Fusion 7", 10.1" panels to the DRM simple
panel driver.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-12 11:32:14 +02:00
Riccardo Bortolato
4fc24ab3a1 drm/panel: simple: Add support for Innolux AT070TN92
Add support for the Innolux AT070TN92 panel.

Signed-off-by: Riccardo Bortolato <bortolato@navaltechitalia.it>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-12 11:32:14 +02:00
Boris Brezillon
844e2f5290 drm/panel: simple: Remove useless drm_mode_set_name()
drm_display_mode_from_videomode() already calls drm_mode_set_name() on
the provided mode.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[treding@nvidia.com: slightly reword commit message]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-12 11:32:14 +02:00
Boris Brezillon
cda553725c drm/panel: simple: Set appropriate mode type
All modes exposed by simple panels should be tagged as driver defined
modes. Moreover, if a panel supports only one mode, this mode is
obviously the preferred one.

Doing this also fix a problem occurring when a 'video=' parameter is
passed on the kernel command line. In some cases the user provided mode
will be preferred over the simple panel ones, which might result in
unpredictable behavior.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[treding@nvidia.com: reshuffle some code for consistency]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-12 11:32:14 +02:00
Maxime Ripard
cf5c9e6dc7 drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS
Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple
panel driver.

It is a 480x272 panel connected through a 24-bits RGB interface.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-12 11:32:14 +02:00
Eric Anholt
e8b6f561b2 drm/panel: simple: Add the 7" DPI panel from Adafruit
This is a basic TFT panel with a 40-pin FPC connector on it.  The
specification doesn't define timings, but the Adafruit instructions
were setting up 800x480 CVT.

v2: Add .bus_format and vsync/hsync flags.

Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Rob Herring <robh@kernel.org>
[treding@nvidia.com: keep entries properly sorted]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-05-12 11:32:14 +02:00
Stefan Agner
2c80661d2e drm/fsl-dcu: use bus_flags for pixel clock polarity
The drivers current default configuration drives the pixel data
on rising edge of the pixel clock. However, most display sample
data on rising edge... This leads to color shift artefacts visible
especially at edges.

This patch changes the relevant defines to be useful and actually
set the bits, and changes pixel clock polarity to drive the pixel
data on falling edge by default. The patch also adds an explicit
pixel clock polarity flag to the display introduced with the driver
(NEC WQVGA "nec,nl4827hc19-05b") using the new bus_flags field to
retain the initial behavior.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-05-05 10:09:06 -07:00
Stefan Agner
f0aa08387b drm: introduce bus_flags in drm_display_info
Introduce bus_flags to specify display bus properties like signal
polarities. This is useful for parallel display buses, e.g. to
specify the pixel clock or data enable polarity.

Suggested-by: Thierry Reding <thierry.reding@gmail.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Manfred Schlaegl <manfred.schlaegl@gmx.at>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-05-05 10:09:01 -07:00
Dave Airlie
5e2368a3bb drm/panel: Changes for v4.6-rc1
This contains a refactoring of parts of the DSI core to allow creating
 DSI devices from non-DSI control busses (i.e. I2C, SPI, ...).
 
 Other than that there's support for a couple of new panels as well as
 a few cleanup patches.
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Merge tag 'drm/panel/for-4.6-rc1' of http://anongit.freedesktop.org/git/tegra/linux into drm-next

drm/panel: Changes for v4.6-rc1

This contains a refactoring of parts of the DSI core to allow creating
DSI devices from non-DSI control busses (i.e. I2C, SPI, ...).

Other than that there's support for a couple of new panels as well as
a few cleanup patches.

* tag 'drm/panel/for-4.6-rc1' of http://anongit.freedesktop.org/git/tegra/linux:
  drm/bridge: Make (pre/post) enable/disable callbacks optional
  drm/panel: simple: Add URT UMSH-8596MD-xT panels support
  dt-bindings: Add URT UMSH-8596MD-xT panel bindings
  of: Add United Radiant Technology Corporation vendor prefix
  drm/panel: simple: Support for LG lp120up1 panel
  dt-bindings: Add LG lp120up1 panel bindings
  drm/panel: simple: Fix g121x1_l03 hsync/vsync polarity
  drm/dsi: Get DSI host by DT device node
  drm/dsi: Add routine to unregister a DSI device
  drm/dsi: Try to match non-DT DSI devices
  drm/dsi: Use mipi_dsi_device_register_full() for DSI device creation
  drm/dsi: Check for CONFIG_OF when defining of_mipi_dsi_device_add()
2016-03-17 08:09:44 +10:00
Maciej S. Szmigiero
06a9dc65af drm/panel: simple: Add URT UMSH-8596MD-xT panels support
Add support for United Radiant Technology UMSH-8596MD-xT 7.0" WVGA TFT
LCD panels in the simple-panel driver.

Signed-off-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-02 17:16:46 +01:00
Jitao Shi
690d8fa70d drm/panel: simple: Support for LG lp120up1 panel
The LG lp120up1 TFT LCD panel with eDP interface is a 12.0" 1920x1280
panel, which can be supported by the simple panel driver.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-02 17:09:46 +01:00
Akshay Bhat
2e8c5eb9ef drm/panel: simple: Fix g121x1_l03 hsync/vsync polarity
Set hsync/vsync to active low for g121x1_l03 panel to match the
recommended setting in the datasheet.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-02 17:05:01 +01:00
Stefan Agner
4bc390c633 drm/fsl-dcu: use mode flags for hsync/vsync polarity
The current default configuration is as follows:
- Invert VSYNC signal (active LOW)
- Invert HSYNC signal (active LOW)

The mode flags allow to specify the required polarity per
mode. Furthermore, none of the current driver settings is
actually a standard polarity.

This patch applies the current driver default polarities as
explicit flags to the display which has been introduced with
the driver (NEC WQVGA "nec,nl4827hc19-05b"). The driver now
also parses the flags field and applies the configuration
accordingly, by using the following values as standard
polarities: (e.g. when no flags are specified):
- VSYNC signal not inverted (active HIGH)
- HSYNC signal not inverted (active HIGH)

Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
2016-02-25 16:13:16 -08:00
Josh Wu
d2a6f0f559 drm/panel: simple: Add QiaoDian qd43003c0-40
The QiaoDian Xianshi QD43003C0-40 is a 4"3 TFT LCD panel.

Timings from the OTA5180A document, ver 0.9, section
10.1.1:
  http://www.orientdisplay.com/pdf/OTA5180A.pdf

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-16 18:15:26 +01:00
Ulrich Ölmann
85533e3b32 drm/panel: add kernel doc for size attributes in panel_desc
Document that 'width' and 'height' are measured in millimeters.

Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-16 16:21:13 +01:00
Lucas Stach
8def22e50f drm/panel: simple: Add support for Kyocera TCG121XGLP panel
The Kyocera TCG121XGLP panel is an XGA LCD TFT panel connected through
LVDS, which can be supported by the simple panel driver.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-16 16:13:47 +01:00
Akshay Bhat
f8fa17ba81 drm/panel: simple: Add support for Innolux G121X1-L03
Add support for Innolux CheMei 12" G121X1-L03 XGA LVDS display.

Datasheet: http://www.azdisplays.com/PDF/G121X1-L03.pdf
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-23 12:20:52 +01:00
Chris Zhong
c8521969de drm/panel: simple: Add support for BOE TV080WUM-NL0
The BOE TV080WUM-NL0 is an 8.0", 1200x1920 (WUXGA) TFT-LCD panel
connected using four DSI lanes. It can be supported by the simple-panel
driver.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-23 09:07:48 +01:00
Gary Bisson
a99fb6269d drm/panel: Add display timing for Okaya RS800480T-7X0GP
Add support for the Okaya RS800480T-7X0GP to the DRM simple panel
driver.

The RS800480T-7X0GP is a WVGA (800x480) panel with an 18-bit parallel
LCD interface. It supports pixel clocks in the range of 30-40 MHz.

This panel details can be found at:
http://boundarydevices.com/product/7-800x480-display/

Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-14 21:35:35 +02:00
jianwei wang
c6e87f91f0 drm/panel: simple: Add support for NEC NL4827HC19-05B 480x272 panel
This adds support for the NEC NL4827HC19-05B 480x272 panel to the DRM
simple panel driver.

Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com>
Signed-off-by: Jianwei Wang <jianwei.wang.chn@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[treding@nvidia.com: add .bpc field for panel]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-14 21:35:33 +02:00
Thierry Reding
d718d79e57 drm/panel: simple: Add support for AUO B080UAN01
The AUO B080UAN01 is an 8.0" WUXGA TFT LCD panel connected using four
DSI lanes. It can be supported by the simple-panel driver.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-14 21:35:33 +02:00
Philipp Zabel
d901d2ba8a drm/panel: simple: Correct minimum hsync length of the HannStar HSD070PWW1 panel
According to the data sheet, the minimum horizontal blanking interval
is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
minimum working horizontal blanking interval to be 60 clocks.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-14 21:35:32 +02:00
Philipp Zabel
58d6a7bc4f drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel
The bus format both specifies the bpc and the way the individual bits get
serialized into the 7 LVDS timeslots.

While the is only one standard mapping for 6 bpc and so the driver could
infer the bit mapping from the bpc alone, there are more options for the
8 bpc case which makes specifiying the bus format mandatory.
To keep things consistent across panels and to set a precedent for new
panel additions add the proper bus format.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-14 21:35:31 +02:00
Philipp Zabel
4946b0430c drm/panel: simple: Add bus format for HannStar HSD100PXN1
This patch adds the bus_format field to the HSD100PXN1 panel structure.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-12 16:40:42 +02:00
Eric Nelson
c0d607e5a2 drm/panel: simple: Add display timing for HannStar HSD100PXN1
Add support for the Hannstar HSD100PXN1 to the DRM simple panel driver.

The HSD100PXN1 is an XGA (1024x768) panel with an 18-bit LVDS interface.
It supports pixel clocks in the range of 55-75 MHz.

This panel is offered for sale by Freescale as a companion part to its'
i.MX5x Quick Start board and i.MX6 SABRE platforms with under the name
MCIMX-LVDS1.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-06-12 16:40:35 +02:00
Heiko Schocher
dd01500269 drm/panel: simple: Add support for LG LB070WV8 800x480 7" panel
This adds support for the LG LB070WV8 7" 800x480 panel to the DRM simple
panel driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-05-22 15:02:59 +02:00
Philipp Zabel
1c550fa193 drm/panel: Add support for Ampire AM-800480R3TMQW-A1H 800x480 7" panel
This adds support for the AM-800480R3TMQW-A1H 7" 800x480 panel to the
DRM simple panel driver.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02 19:04:15 +02:00
Philipp Zabel
ab07725abc drm/panel: Add display timing for HannStar HSD070PWW1
The HannStar HSD070PWW1 LVDS panel data sheet lists allowed ranges
additionally to the typical values for pixel clock rate (64.3-82 MHz)
and blanking intervals (54-681 clock cycles horizontally, 3-23 lines
vertically).

This patch replaces this panel's display mode with the display timing
information to describe acceptable timings. Since the HSYNC and VSYNC
are unused, the distribution between front porches, back porches, and
sync pulse lengths was chosen at will.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02 19:04:14 +02:00