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Commit Graph

7521 Commits

Author SHA1 Message Date
Laurent Pinchart
31a42c2f3b clk: mediatek: mux: Update parent at enable time
The mux clocks don't always correctly take the new parent into account
when the parent is updated while the clock is disabled. Set the update
bit when enabling the clock to force an update of the mux.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20210125170819.26130-3-laurent.pinchart@ideasonboard.com
Reviewed-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-09 00:01:28 -08:00
Laurent Pinchart
6df3c6d9fd clk: mediatek: mux: Drop unused clock ops
Three out of the four defined clock ops are unused. Drop them.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20210125170819.26130-2-laurent.pinchart@ideasonboard.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-09 00:01:28 -08:00
Enric Balletbo i Serra
8c18e927b1 clk: mediatek: Select all the MT8183 clocks by default
If MT8183 SoC support is enabled, almost all machines will use topckgen,
apmixedsys, infracfg, mcucfg and subsystem clocks, so it feels wrong to
require each one to select that symbols manually.

Instead, enable it whenever COMMON_CLK_MT8183_* is disabled as
a simplification. This would add few KB in the kernel image size but
will make the life a bit easier to the users, anyway you'll need to probably
enable all of them if you want to have proper support for that SoC.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20210203105423.682960-1-enric.balletbo@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 23:47:04 -08:00
Arnd Bergmann
ee7294ba49 clk: remove u300 driver
The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-5-arnd@kernel.org
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 23:42:03 -08:00
Arnd Bergmann
ed0f3e23d1 clk: remove sirf prima2/atlas drivers
The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.

Cc: Barry Song <baohua@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-4-arnd@kernel.org
Acked-by: Barry Song <baohua@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 23:42:03 -08:00
Arnd Bergmann
bcbe6005eb clk: remove zte zx driver
The zte zx platform is getting removed, so this driver is no
longer needed.

Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-3-arnd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 23:42:03 -08:00
Arnd Bergmann
7765f32a8e clk: remove tango4 driver
The tango platform is getting removed, so the driver is no
longer needed.

Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Cc: Mans Rullgard <mans@mansr.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210120131026.1721788-2-arnd@kernel.org
Acked-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 23:42:02 -08:00
Michael Tretter
a2fe7baa27 clk: xilinx: move xlnx_vcu clock driver from soc
The xlnx_vcu driver is actually a clock controller driver which provides
clocks that can be used by a driver for the encoder/decoder units. There
is no reason to keep this driver in soc. Move the driver to clk.

NOTE: The register mapping actually contains registers for AXI
performance monitoring, but these are not used by the driver.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-16-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 18:31:25 -08:00
Michael Tretter
0225daea08 clk: divider: fix initialization with parent_hw
If a driver registers a divider clock with a parent_hw instead of the
parent_name, the parent_hw is ignored and the clock does not have a
parent.

Fix this by initializing the parents the same way they are initialized
for clock gates.

Fixes: ff25881713 ("clk: divider: Add support for specifying parents via DT/pointers")
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-3-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 18:31:24 -08:00
Alexandru Ardelean
6ba7ea7630 clk: axi-clkgen: use devm_platform_ioremap_resource() short-hand
No major functional change. Noticed while checking the driver code that
this could be used.
Saves two lines.

Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20210201151245.21845-5-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 18:13:13 -08:00
Alexandru Ardelean
da68c30963 clk: clk-axiclkgen: add ZynqMP PFD and VCO limits
For ZynqMP (Ultrascale) the PFD and VCO limits are different. In order to
support these, this change adds a compatible string (i.e.
'adi,zynqmp-axi-clkgen-2.00.a')  which will take into account for these
limits and apply them.

Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Mathias Tausen <mta@gomspace.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20210201151245.21845-3-alexandru.ardelean@analog.com
Acked-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 18:13:12 -08:00
Alexandru Ardelean
324a810583 clk: axi-clkgen: replace ARCH dependencies with driver deps
The intent is to be able to run this driver to access the IP core in setups
where FPGA board is also connected via a PCIe bus. In such cases the number
of combinations explodes, where the host system can be an x86 with Xilinx
Zynq/ZynqMP/Microblaze board connected via PCIe.
Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.

To accommodate for these cases, this change removes the limitation for this
driver to be compilable only on Zynq/Microblaze architectures.
And adds dependencies on the mechanisms required by the driver to work (OF
and HAS_IOMEM).

Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20210201151245.21845-2-alexandru.ardelean@analog.com
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 18:13:12 -08:00
Uwe Kleine-König
33034d7422 clk: Drop unused efm32gg driver
Support for this machine was just removed, so drop the now unused clk
driver, too.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20210114151630.128830-3-u.kleine-koenig@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 12:20:40 -08:00
AngeloGioacchino Del Regno
68e1d106eb clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on
This GDSC enables (or cuts!) power to the Multimedia Subsystem IOMMU
(mmss smmu), which has bootloader pre-set secure contexts.
In the event of a complete power loss, the secure contexts will be
reset and the hypervisor will crash the SoC.

To prevent this, and get a working multimedia subsystem, set this
GDSC as always on.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-10-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:24:34 -08:00
AngeloGioacchino Del Regno
fa92f3b093 clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks
Hardware clock gating is supported on some of the clocks declared in
there: ignoring that it does exist may lead to unstabilities on some
firmwares.
Add the HWCG registers where applicable to stop potential crashes.

This was verified on a smartphone shipped with a recent MSM8998
firmware, which will experience random crashes without this change.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-9-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:24:33 -08:00
AngeloGioacchino Del Regno
292f75ecff clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs
All of the GPLLs in the MSM8998 Global Clock Controller are Fabia PLLs
and not generic alphas: this was producing bad effects over the entire
clock tree of MSM8998, where any GPLL child clock was declaring a false
clock rate, due to their parent also showing the same.

The issue resides in the calculation of the clock rate for the specific
Alpha PLL type, where Fabia has a different register layout; switching
the MSM8998 GPLLs to the correct Alpha Fabia PLL type fixes the rate
(calculation) reading. While at it, also make these PLLs fixed since
their rate is supposed to *never* be changed while the system runs, as
this would surely crash the entire SoC.

Now all the children of all the PLLs are also complying with their
specified clock table and system stability is improved.

Fixes: b5f5f525c5 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-7-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:17:49 -08:00
AngeloGioacchino Del Regno
f861149130 clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as critical
The GPU IOMMU depends on this clock and the hypervisor will crash
the SoC if this clock gets disabled because the secure contexts
that have been set on this IOMMU by the bootloader will become
unaccessible (or they get reset).
Mark this clock as critical to avoid this issue when the Adreno
GPU is enabled.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-6-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:17:49 -08:00
AngeloGioacchino Del Regno
b791620cf4 clk: qcom: gcc-msm8998: Add missing hmss_gpll0_clk_src clock
To achieve CPR-Hardened functionality this clock must be on: add it
in order to be able to get it managed by the CPR3 driver.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-5-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:17:49 -08:00
AngeloGioacchino Del Regno
68f863e561 clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clock
This clock enables the GPLL0 output to the multimedia subsystem
clock controller.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-3-angelogioacchino.delregno@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:17:49 -08:00
Bryan O'Donoghue
fe8e6d5547 clk: qcom: videocc: Add gdsc mmcx-reg supply hook
This commit adds a regulator supply hook to mmcx-reg missing from

- mvs0c_gdsc
- mvs1c_gdsc
- mvs0_gdsc
- mvs1_gdsc

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210204150120.1521959-5-bryan.odonoghue@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:12:29 -08:00
Bryan O'Donoghue
c80a4285a3 clk: qcom: videocc: Add sm8250 VIDEO_CC_MVS0_CLK
This patch adds the missing video_cc_mvs0_clk entry to
videocc-sm8250 replicating in upstream the explicit entry for this clock in
downstream.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210204150120.1521959-4-bryan.odonoghue@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:12:29 -08:00
Bryan O'Donoghue
2334032f00 clk: qcom: videocc: Add sm8250 VIDEO_CC_MVS0_DIV_CLK_SRC
This patch adds the missing video_cc_mvs0_div_clk_src entry to
videocc-sm8250 replicating in upstream the explicit entry for this clock in
downstream.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210204150120.1521959-3-bryan.odonoghue@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:12:29 -08:00
Vivek Aknurwar
44c20c9ed3 clk: qcom: gcc: Add clock driver for SM8350
This adds Global Clock controller (GCC) driver for SM8350 SoC

Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210127070811.152690-6-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:03:57 -08:00
Vivek Aknurwar
f4c7e27aa4 clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLL
Lucid 5LPE is a slightly different Lucid PLL with different offsets and
porgramming sequence so add support for these

Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210127070811.152690-4-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:03:57 -08:00
Vinod Koul
80ca7765fc clk: qcom: clk-alpha-pll: modularize alpha_pll_trion_set_rate()
Trion 5LPE set rate uses code similar to alpha_pll_trion_set_rate() but
with different registers. Modularize these by moving out latch and latch
ack bits so that we can reuse the function.

Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210127070811.152690-3-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:03:57 -08:00
Vinod Koul
160210b483 clk: qcom: clk-alpha-pll: replace regval with val
Driver uses regval variable for holding register values, replace with a
shorter one val

Suggested-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210127070811.152690-2-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 10:03:56 -08:00
Bjorn Andersson
4433594bbe clk: qcom: gcc: Add global clock controller driver for SC8180x
Add clocks, resets and some of the GDSC provided by the global clock
controller found in the Qualcomm SC8180x platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210126043155.1847823-2-bjorn.andersson@linaro.org
[sboyd@kernel.org: Drop F macro as it's already defined]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 09:59:46 -08:00
Taniya Das
d79dfa19ca clk: qcom: gcc-sc7180: Mark the MM XO clocks to be always ON
There are intermittent GDSC power-up failures observed for titan top
gdsc, which requires the XO clock. Thus mark all the MM XO clocks always
enabled from probe.

Fixes: 8d4025943e ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1611128871-5898-1-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 09:53:30 -08:00
Bjorn Andersson
8a1f7fb175 clk: qcom: rpmhcc: Add sc8180x rpmh clocks
Add clocks provides by RPMH in the Qualcomm SC8180x platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210120223741.1610344-2-bjorn.andersson@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 09:52:20 -08:00
Srinivas Kandagatla
78ddb79cab clk: qcom: gfm-mux: fix clk mask
For some reason global GFM_MASK ended up with bit 1 instead of bit 0.
Remove the global GFM_MASK and reuse mux_mask field.

Fixes: a2d8f50780 ("clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks")
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20210119113851.18946-1-srinivas.kandagatla@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 09:50:46 -08:00
Manivannan Sadhasivam
f28dec1ab7 clk: qcom: Add SDX55 APCS clock controller support
Add a driver for the SDX55 APCS clock controller. It is part of the APCS
hardware block, which among other things implements also a combined mux
and half integer divider functionality. The APCS clock controller has 3
parent clocks:

1. Board XO
2. Fixed rate GPLL0
3. A7 PLL

This is required for enabling CPU frequency scaling on SDX55-based
platforms.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210118041156.50016-6-manivannan.sadhasivam@linaro.org
[sboyd@kernel.org: Fix unused ret in probe by hardcoding it]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 09:46:23 -08:00
Manivannan Sadhasivam
5a5223ffd7 clk: qcom: Add A7 PLL support
Add support for PLL found in Qualcomm SDX55 platforms which is used to
provide clock to the Cortex A7 CPU via a mux. This PLL can provide high
frequency clock to the CPU above 1GHz as compared to the other sources
like GPLL0.

In this driver, the power domain is attached to the cpudev. This is
required for CPUFreq functionality and there seems to be no better place
to do other than this driver (no dedicated CPUFreq driver).

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210118041156.50016-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08 09:46:23 -08:00
Heiko Stuebner
4bc23b3c83 clk: rockchip: fix DPHY gate locations on rk3368
Fix the register and bits of the DPHY gate locations.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20210205110502.1850669-5-heiko@sntech.de
2021-02-06 01:05:04 +01:00
Heiko Stuebner
ed2243e003 clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368
Export the vip-out clock via the newly added clock-id.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20210205110502.1850669-4-heiko@sntech.de
2021-02-06 01:05:04 +01:00
Heiko Stuebner
fabb841c5b clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
Export the clocks via the newly added clock-ids.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20210205110502.1850669-2-heiko@sntech.de
2021-02-06 01:05:04 +01:00
Lee Jones
de5774d192 clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible header
Fixes the following W=1 kernel build warning(s):

 drivers/clk/imx/clk-imx6sl.c:156:6: warning: no previous prototype for ‘imx6sl_set_wait_clk’ [-Wmissing-prototypes]

Cc: Russell King <linux@armlinux.org.uk>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-30 22:13:23 +08:00
Lucas Stach
3af4df6550 clk: imx8mn: add clkout1/2 support
clkout1 and clkout2 allow to supply clocks from the SoC to the board,
which is used by some board designs to provide reference clocks.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-30 21:35:33 +08:00
Lucas Stach
c1ae5c6f78 clk: imx8mm: add clkout1/2 support
clkout1 and clkout2 allow to supply clocks from the SoC to the board,
which is used by some board designs to provide reference clocks.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-30 21:35:30 +08:00
Lucas Stach
75a352bc66 clk: imx8mq: add PLL monitor output
The PLL monitor is mentioned as a debug feature in the reference manual,
but there are some boards that use this clock output as a reference clock
for board level components. Add support for those clocks in the clock
driver, so this clock output can be used properly.

Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the
description in the reference manual. The order in this patch has been
empirically validated.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-30 21:35:15 +08:00
Lee Jones
62a7c1c47a clk: imx: clk-imx31: Remove unused static const table 'uart_clks'
Fixes the following W=1 kernel build warning(s):

 drivers/clk/imx/clk-imx31.c:54:28: warning: ‘uart_clks’ defined but not used [-Wunused-const-variable=]

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-29 21:31:52 +08:00
Ahmad Fatoum
f3afd3fb3d clk: imx6q: demote warning about pre-boot ldb_di_clk reparenting
Since 5d283b0838 ("clk: imx6: Fix procedure to switch the parent
of LDB_DI_CLK"), the clock driver warns if ldb_di\d_sel is changed
from reset value on system boot. This warning is printed even if
the bootloader (or a previous kernel that did kexec) followed the
correct procedure for glitch-free reparenting.

As such systems are doing everything correctly, a warning is too
harsh. Demote to a notice, so users are still alerted, but without
cluttering a loglevel=5 boot.

While at it, add the words "possible glitch" into the log message, to
make it more user-friendly.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-29 16:23:34 +08:00
Linus Torvalds
a467b07361 A handful of clk driver fixes
- Build fix for CONFIG_PM=n in the mmp2 driver
  - Kconfig warning for unmet dependencies in the i.MX driver
  - Make the camera AHB clk always be enabled on qcom sc7180
  - Use rate round down semantics for qcom sm8250 SD clks
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "A handful of clk driver fixes:

   - Build fix for CONFIG_PM=n in the mmp2 driver

   - Kconfig warning for unmet dependencies in the i.MX driver

   - Make the camera AHB clk always be enabled on qcom sc7180

   - Use rate round down semantics for qcom sm8250 SD clks"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: mmp2: fix build without CONFIG_PM
  clk: qcom: gcc-sm250: Use floor ops for sdcc clks
  clk: imx: fix Kconfig warning for i.MX SCU clk
  clk: qcom: gcc-sc7180: Mark the camera abh clock always ON
2021-01-28 09:14:58 -08:00
Andre Przywara
88dde5e23d
clk: sunxi-ng: Add support for the Allwinner H616 CCU
While the clocks are fairly similar to the H6, many differ in tiny
details, so a separate clock driver seems indicated.

Derived from the H6 clock driver, and adjusted according to the manual.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210127172500.13356-4-andre.przywara@arm.com
2021-01-28 11:14:35 +01:00
Andre Przywara
394a36dd9d
clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
The clocks itself are identical to the H6 R-CCU, it's just that the H616
has not all of them implemented (or connected).

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210127172500.13356-3-andre.przywara@arm.com
2021-01-28 11:14:30 +01:00
Lee Jones
24ece96554 clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentation
Fixes the following W=1 kernel build warning(s):

 drivers/clk/renesas/renesas-cpg-mssr.c:168: warning: Function parameter or member 'smstpcr_saved' not described in 'cpg_mssr_priv'

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-12-lee.jones@linaro.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-28 09:45:56 +01:00
Nicolas Pitre
0bfa0820c2 PM: clk: make PM clock layer compatible with clocks that must sleep
The clock API splits its interface into sleepable ant atomic contexts:

 - clk_prepare/clk_unprepare for stuff that might sleep

 - clk_enable_clk_disable for anything that may be done in atomic context

The code handling runtime PM for clocks only calls clk_disable() on
suspend requests, and clk_enable on resume requests. This means that
runtime PM with clock providers that only have the prepare/unprepare
methods implemented is basically useless.

Many clock implementations can't accommodate atomic contexts. This is
often the case when communication with the clock happens through another
subsystem like I2C or SCMI.

Let's make the clock PM code useful with such clocks by safely invoking
clk_prepare/clk_unprepare upon resume/suspend requests. Of course, when
such clocks are registered with the PM layer then pm_runtime_irq_safe()
can't be used, and neither pm_runtime_suspend() nor pm_runtime_resume()
may be invoked in atomic context.

For clocks that do implement the enable and disable methods then
everything just works as before.

A note on sparse:
According to https://lwn.net/Articles/109066/ there are things
that sparse can't cope with. In particular, pm_clk_op_lock() and
pm_clk_op_unlock() may or may not lock/unlock psd->lock depending on
some runtime condition. To work around that we tell it the lock is
always untaken for the purpose of static analisys.

Thanks to Naresh Kamboju for reporting issues with the initial patch.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-01-27 19:29:32 +01:00
Lee Jones
d48fbef962 clk: rockchip: Demote non-conformant kernel-doc header in half-divider
Fixes the following W=1 kernel build warning(s):

 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'name' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'parent_names' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'num_parents' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'base' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'muxdiv_offset' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'mux_shift' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'mux_width' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'mux_flags' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'div_shift' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'div_width' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'div_flags' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'gate_offset' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'gate_shift' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'gate_flags' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'flags' not described in 'rockchip_clk_register_halfdiv'
 drivers/clk/rockchip/clk-half-divider.c:168: warning: Function parameter or member 'lock' not described in 'rockchip_clk_register_halfdiv'

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-5-lee.jones@linaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-26 00:24:05 +01:00
Lee Jones
eee7b95589 clk: rockchip: Demote kernel-doc abuses to standard comment blocks in plls
Fixes the following W=1 kernel build warning(s):

 drivers/clk/rockchip/clk-pll.c:104: warning: Function parameter or member 'i' not described in 'RK3036_PLLCON'
 drivers/clk/rockchip/clk-pll.c:365: warning: Function parameter or member 'nr' not described in 'RK3066_PLL_RESET_DELAY'
 drivers/clk/rockchip/clk-pll.c:584: warning: Function parameter or member 'i' not described in 'RK3399_PLLCON'

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Xing Zheng <zhengxing@rock-chips.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-4-lee.jones@linaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-26 00:24:05 +01:00
Lee Jones
274ae6da4b clk: rockchip: Remove unused/undocumented struct members from clk-cpu
Fixes the following W=1 kernel build warning(s):

 drivers/clk/rockchip/clk-cpu.c:65: warning: Function parameter or member 'cpu_mux' not described in 'rockchip_cpuclk'
 drivers/clk/rockchip/clk-cpu.c:65: warning: Function parameter or member 'cpu_mux_ops' not described in 'rockchip_cpuclk'

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-3-lee.jones@linaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-26 00:24:05 +01:00
Lee Jones
4151737120 clk: rockchip: Demote non-conformant kernel-doc headers in main clock code
Fixes the following W=1 kernel build warning(s):

 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'name' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'parent_names' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'num_parents' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'base' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'muxdiv_offset' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'mux_shift' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'mux_width' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'mux_flags' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_offset' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_shift' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_width' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_flags' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_table' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'gate_offset' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'gate_shift' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'gate_flags' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'flags' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'lock' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'hw' not described in 'rockchip_fractional_approximation'
 drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'rate' not described in 'rockchip_fractional_approximation'
 drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'parent_rate' not described in 'rockchip_fractional_approximation'
 drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'm' not described in 'rockchip_fractional_approximation'
 drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'n' not described in 'rockchip_fractional_approximation'

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Xing Zheng <zhengxing@rock-chips.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-2-lee.jones@linaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-26 00:24:04 +01:00
Wolfram Sang
c5e91ba25a clk: renesas: r8a779a0: Add RAVB clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210121100619.5653-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-25 09:46:22 +01:00
Wolfram Sang
6893a77279 clk: renesas: r8a779a0: Add I2C clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210121095420.5023-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-25 09:46:22 +01:00
Andre Przywara
04ef679591
clk: sunxi-ng: h6: Fix clock divider range on some clocks
While comparing clocks between the H6 and H616, some of the M factor
ranges were found to be wrong: the manual says they are only covering
two bits [1:0], but our code had "5" in the number-of-bits field.

By writing 0xff into that register in U-Boot and via FEL, it could be
confirmed that bits [4:2] are indeed masked off, so the manual is right.

Change to number of bits in the affected clock's description.

Fixes: 524353ea48 ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210118000912.28116-1-andre.przywara@arm.com
2021-01-20 10:59:30 +01:00
Lee Jones
eec9d9b7b0
clk: sunxi: clk-mod0: Demote non-conformant kernel-doc header
Fixes the following W=1 kernel build warning(s):

 drivers/clk/sunxi/clk-mod0.c:24: warning: Function parameter or member 'req' not described in 'sun4i_a10_get_mod0_factors'

Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Jernej Skrabec <jernej.skrabec@siol.net>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210120093040.1719407-19-lee.jones@linaro.org
2021-01-20 10:58:29 +01:00
Lee Jones
29f476d443
clk: sunxi: clk-a10-ve: Demote obvious kernel-doc abuse
Fixes the following W=1 kernel build warning(s):

 drivers/clk/sunxi/clk-a10-ve.c:27: warning: cannot understand function prototype: 'struct ve_reset_data '

Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Jernej Skrabec <jernej.skrabec@siol.net>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210120093040.1719407-18-lee.jones@linaro.org
2021-01-20 10:56:29 +01:00
Lee Jones
58fdf74d43
clk: sunxi: clk-sunxi: Demote a bunch of non-conformant kernel-doc headers
Fixes the following W=1 kernel build warning(s):

 drivers/clk/sunxi/clk-sunxi.c:34: warning: Function parameter or member 'req' not described in 'sun4i_get_pll1_factors'
 drivers/clk/sunxi/clk-sunxi.c:81: warning: Function parameter or member 'req' not described in 'sun6i_a31_get_pll1_factors'
 drivers/clk/sunxi/clk-sunxi.c:158: warning: Function parameter or member 'req' not described in 'sun8i_a23_get_pll1_factors'
 drivers/clk/sunxi/clk-sunxi.c:202: warning: Function parameter or member 'req' not described in 'sun4i_get_pll5_factors'
 drivers/clk/sunxi/clk-sunxi.c:229: warning: Function parameter or member 'req' not described in 'sun6i_a31_get_pll6_factors'
 drivers/clk/sunxi/clk-sunxi.c:250: warning: Function parameter or member 'req' not described in 'sun5i_a13_get_ahb_factors'
 drivers/clk/sunxi/clk-sunxi.c:289: warning: Function parameter or member 'req' not described in 'sun6i_get_ahb1_factors'
 drivers/clk/sunxi/clk-sunxi.c:328: warning: Function parameter or member 'req' not described in 'sun6i_ahb1_recalc'
 drivers/clk/sunxi/clk-sunxi.c:346: warning: Function parameter or member 'req' not described in 'sun4i_get_apb1_factors'
 drivers/clk/sunxi/clk-sunxi.c:385: warning: Function parameter or member 'req' not described in 'sun7i_a20_get_out_factors'
 drivers/clk/sunxi/clk-sunxi.c:415: warning: cannot understand function prototype: 'const struct clk_factors_config sun4i_pll1_config = '
 drivers/clk/sunxi/clk-sunxi.c:724: warning: cannot understand function prototype: 'struct div_data '
 drivers/clk/sunxi/clk-sunxi.c:945: warning: Function parameter or member 'node' not described in 'sunxi_divs_clk_setup'
 drivers/clk/sunxi/clk-sunxi.c:945: warning: Function parameter or member 'data' not described in 'sunxi_divs_clk_setup'

Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Jernej Skrabec <jernej.skrabec@siol.net>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210120093040.1719407-15-lee.jones@linaro.org
2021-01-20 10:56:22 +01:00
Arnd Bergmann
c361c5a6c5 clk: mmp2: fix build without CONFIG_PM
pm_clk_suspend()/pm_clk_resume() are defined as NULL pointers rather than
empty inline stubs without CONFIG_PM:

drivers/clk/mmp/clk-audio.c:402:16: error: called object type 'void *' is not a function or function pointer
        pm_clk_suspend(dev);
drivers/clk/mmp/clk-audio.c:411:15: error: called object type 'void *' is not a function or function pointer
        pm_clk_resume(dev);

I tried redefining the helper functions, but that caused additional
problems. This is the simple solution of replacing the __maybe_unused
trick with an #ifdef.

Fixes: 725262d291 ("clk: mmp2: Add audio clock controller driver")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210103135503.3668784-1-arnd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-01-12 12:10:55 -08:00
Dmitry Baryshkov
fd23830935 clk: qcom: gcc-sm250: Use floor ops for sdcc clks
Followup to the commits 5e4b7e82d4 ("clk: qcom: gcc-sdm845: Use floor
ops for sdcc clks") and 6d37a8d192 ("clk: qcom: gcc-sc7180: Use floor ops
for sdcc clks"). Use floor ops for sdcc clocks on sm8250.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 3e5770921a ("clk: qcom: gcc: Add global clock controller driver for SM8250")
Link: https://lore.kernel.org/r/20210109013314.3443134-1-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-01-12 12:10:52 -08:00
Arnd Bergmann
73f6b7ed98 clk: imx: fix Kconfig warning for i.MX SCU clk
A previous patch introduced a harmless randconfig warning:

WARNING: unmet direct dependencies detected for MXC_CLK_SCU
  Depends on [n]: COMMON_CLK [=y] && ARCH_MXC [=n] && IMX_SCU [=y] && HAVE_ARM_SMCCC [=y]
  Selected by [m]:
  - CLK_IMX8QXP [=m] && COMMON_CLK [=y] && (ARCH_MXC [=n] && ARM64 [=y] || COMPILE_TEST [=y]) && IMX_SCU [=y] && HAVE_ARM_SMCCC [=y]

Since the symbol is now hidden and only selected by other symbols,
just remove the dependencies and require the other drivers to
get it right.

Fixes: 6247e31b75 ("clk: imx: scu: fix MXC_CLK_SCU module build break")
Reported-by: Anders Roxell <anders.roxell@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20201230155244.981757-1-arnd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-01-12 11:25:54 -08:00
Taniya Das
98829137a6 clk: qcom: gcc-sc7180: Mark the camera abh clock always ON
The camera clock controller requires the AHB clock, the driver when
moved to use the pm_runtime_get() API, the camera ahb clock failed turn
on before access, thus mark it as always ON.

Reported-by: Stephen Boyd <sboyd@kernel.org>
Fixes: 8d4025943e ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1608573816-1465-1-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-01-12 11:25:19 -08:00
Peter Geis
f4eccc7fea clk: tegra30: Add hda clock default rates to clock driver
Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.

This matches upstream t124 and downstream t30.

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Ion Agorria <ion@agorria.com>
Acked-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210108135913.2421585-2-pgwipeout@gmail.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2021-01-12 14:43:53 +01:00
Geert Uytterhoeven
2b6587288a clk: renesas: r8a779a0: Add SYS-DMAC clocks
Add the module clocks used by the Direct Memory Access Controller for
System (SYS-DMAC) instances on the Renesas R-Car V3U (r8a779a0) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210107180109.1946475-1-geert+renesas@glider.be
2021-01-12 12:35:13 +01:00
Wolfram Sang
792501727c clk: renesas: r8a779a0: Add SDHI support
We use the shiny new CPG library for that.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201227174202.40834-5-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12 12:35:13 +01:00
Wolfram Sang
8bb67d8734 clk: renesas: rcar-gen3: Factor out CPG library
R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but
similar enough to reuse code. Introduce a new CPG library, factor out
the SD clock handling and hook it to the generic Gen3 CPG driver so we
have an equal state. V3U will make use of it in the next patch then.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201227174202.40834-4-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12 12:35:13 +01:00
Wolfram Sang
97af391a6f clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clock
We want to reuse SD clock handling for other SoCs and, thus, need to
generalize it. So, don't access cpg_quirks in that realm.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201227174202.40834-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-12 12:35:13 +01:00
Geert Uytterhoeven
010ce438e7 clk: renesas: r8a779a0: Add MSIOF clocks
Add the module clocks used by the Clock-Synchronized Serial Interface
with FIFO (MSIOF) instances on the Renesas R-Car V3U (r8a779a0) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201117090329.2128904-3-geert+renesas@glider.be
2021-01-12 12:35:13 +01:00
Geert Uytterhoeven
f08b0d8498 clk: renesas: r8a779a0: Add PFC/GPIO clocks
Add the module clocks used by the Pin Function Controller (PFC) and
General Purpose Input/Output (GPIO) blocks, and their parent clock CP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201019120614.22149-4-geert+renesas@glider.be
2021-01-12 12:35:10 +01:00
Geert Uytterhoeven
80d3e07ec5 clk: renesas: r8a779a0: Fix parent of CBFUSA clock
According to Figure 8.1.1 ("Block Diagram of CPG (R-Car V3U-AD)") in the
R-Car V3U Series User's Manual Rev. 0.5, the parent of the CBFUSA clock
is EXTAL.

Fixes: 17bcc8035d ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201019120614.22149-3-geert+renesas@glider.be
2021-01-07 18:41:53 +01:00
Geert Uytterhoeven
5b30be15ca clk: renesas: r8a779a0: Remove non-existent S2 clock
The S2 internal core clock does not exist on R-Car V3U. Remove it.

Fixes: 17bcc8035d ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201019120614.22149-2-geert+renesas@glider.be
2021-01-07 18:41:53 +01:00
Wolfram Sang
2e16d0df87 clk: renesas: r8a779a0: Add HSCIF support
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201228112715.14947-5-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-01-07 16:23:13 +01:00
Andre Przywara
756650820a
clk: sunxi-ng: h6: Fix CEC clock
The CEC clock on the H6 SoC is a bit special, since it uses a fixed
pre-dividier for one source clock (the PLL), but conveys the other clock
(32K OSC) directly.
We are using a fixed predivider array for that, but fail to use the right
flag to actually activate that.

Fixes: 524353ea48 ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Reported-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210106143246.11255-1-andre.przywara@arm.com
2021-01-06 17:51:23 +01:00
Samuel Holland
0482a4e6de clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset
While no information about the H6 RSB controller is included in the
datasheet or manual, the vendor BSP and power management blob both
reference the RSB clock parent and register address. These values were
verified by experimentation.

Since this clock/reset are added late, the specifier is added at the end
to maintain the existing DT binding. The code is kept in register order.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2021-01-06 19:34:29 +08:00
Dmitry Osipenko
281462e593 memory: tegra124-emc: Make driver modular
Add modularization support to the Tegra124 EMC driver, which now can be
compiled as a loadable kernel module.

Note that EMC clock must be registered at clk-init time, otherwise PLLM
will be disabled as unused clock at boot time if EMC driver is compiled
as a module. Hence add a prepare/complete callbacks. similarly to what is
done for the Tegra20/30 EMC drivers.

Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201228154920.18846-2-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-01-05 18:00:09 +01:00
Liu Ying
6f88ef38ec clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems
This patch adds some SCU clocks support for i.MX8qxp MIPI-LVDS subsystems.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-05 10:55:12 +08:00
Liu Ying
e4c0ca7894 clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()
This patch corrects display clocks for i.MX8qxp DC0 subsystem by
calling imx_clk_scu2() to register them, instead of calling
imx_clk_scu().  The reason is that the clocks can source from
various parents.  The clock source selection is controlled by
Distributed Slave System Controller(DSC).  According to the DSC spec,
the below table describes the generic source selections for clocks
with the same type in various subsystems.  And, the display controller
subsystem spec says the display clocks can source from PLL1, PLL2 or
bypass clock, thus we may specify the correct parents for imx_clk_scu2().

The bypass clock's parent is determined by the SCU firmware.
Currently, the parent is 'pixel_link_clk_in' from HW point of view.
To be more specific, the parent is dummy for i.MX8qxp DC0, while
HDMI TX PHY PLL for i.MX8qm DC0.  In practice, the display clocks
source from the bypass clock only when driving i.MX8qm HDMI TX.
So, for the both display clocks, we simply specify 'dc0_bypass0_clk'
bypass clock as a valid parent.

 -----------------------------------------
| src_sel[28:26] |                        |
 -----------------------------------------
| 0x0            | xtal24M                |
| 0x1            | PLL0                   |
| 0x2            | PLL1                   |
| 0x3            | PLL2                   |
| 0x4            | bypass reference clock |
| 0x5 to 0x7     | reserved               |
 -----------------------------------------

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-05 10:55:08 +08:00
Liu Ying
de332bf242 clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks
This patch adds SCU clocks support for i.MX8qxp DC0 subsystem bypass clocks.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-05 10:55:05 +08:00
Liu Ying
95741fdb52 clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks
This patch adds SCU clocks support for i.MX8qxp DC0 subsystem PLL clocks.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-05 10:54:37 +08:00
Martin Blumenstingl
40e977400d clk: meson: meson8b: remove compatibility code for old .dtbs
The XTAL clock is provided via .dts since Linux 5.6. Remove
compatibility code for .dtbs which are older than that.

The switch to the HHI syscon has been done with Linux 5.1. Also remove
any code needed to support .dtbs that have not switched to the HHI
syscon yet.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201221183624.932649-2-martin.blumenstingl@googlemail.com
2021-01-04 11:43:19 +01:00
Martin Blumenstingl
ccdc1f0836 clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()
Popagate the error code from meson_clk_pll_set_rate() when the PLL does
not lock with the new settings.

Fixes: 722825dcd5 ("clk: meson: migrate plls clocks to clk_regmap")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201226121556.975418-4-martin.blumenstingl@googlemail.com
2021-01-04 11:42:43 +01:00
Martin Blumenstingl
9e717285f0 clk: meson: clk-pll: make "ret" a signed integer
The error codes returned by meson_clk_get_pll_settings() are all
negative. Make "ret" a signed integer in meson_clk_pll_set_rate() to
make it match with the clk_ops.set_rate API as well as the data type
returned by meson_clk_get_pll_settings().

Fixes: 8eed1db1ad ("clk: meson: pll: update driver for the g12a")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201226121556.975418-3-martin.blumenstingl@googlemail.com
2021-01-04 11:42:38 +01:00
Martin Blumenstingl
2f290b7c67 clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL
The "rate" parameter in meson_clk_pll_set_rate() contains the new rate.
Retrieve the old rate with clk_hw_get_rate() so we don't inifinitely try
to switch from the new rate to the same rate again.

Fixes: 7a29a86943 ("clk: meson: Add support for Meson clock controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201226121556.975418-2-martin.blumenstingl@googlemail.com
2021-01-04 11:42:25 +01:00
Wolfram Sang
ab2ccacd73 clk: renesas: r8a779a0: Add RWDT clocks
And introduce critical clocks, too, because RWDT is one.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201218173731.12839-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28 10:52:58 +01:00
Kieran Bingham
57be2dc8d4 clk: renesas: r8a779a0: Add VSPX clock support
Add clocks for the VSPX.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20201216151931.851547-4-kieran.bingham+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28 10:45:17 +01:00
Kieran Bingham
ed447e7d60 clk: renesas: r8a779a0: Add VSPD clock support
Add clocks for the VSPD modules on the V3U.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20201216151931.851547-3-kieran.bingham+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28 10:45:17 +01:00
Kieran Bingham
0177b5090e clk: renesas: r8a779a0: Add FCPVD clock support
Add clocks for the FCP for VSP-D module.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20201216151931.851547-2-kieran.bingham+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28 10:45:17 +01:00
Niklas Söderlund
fa7f47972b clk: renesas: r8a77995: Add TMU clocks
This patch adds TMU{0,1,2,3,4} clocks.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20201209195343.803120-6-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28 10:45:17 +01:00
Niklas Söderlund
0f3a926594 clk: renesas: r8a77990: Add TMU clocks
This patch adds TMU{0,1,2,3,4} clocks.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20201209195343.803120-5-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28 10:45:17 +01:00
Niklas Söderlund
e0c0d44934 clk: renesas: r8a77965: Add TMU clocks
This patch adds TMU{0,1,2,3,4} clocks.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20201209195343.803120-4-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28 10:45:16 +01:00
Niklas Söderlund
a26edd3d3c clk: renesas: r8a7796: Add TMU clocks
This patch adds TMU{0,1,2,3,4} clocks.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20201209195343.803120-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-28 10:45:16 +01:00
Linus Torvalds
8653b778e4 The core framework got some nice improvements this time around. We gained the
ability to get struct clk pointers from a struct clk_hw so that clk providers
 can consume the clks they provide, if they need to do something like that. This
 has been a long missing part of the clk provider API that will help us move
 away from exposing a struct clk pointer in the struct clk_hw. Tracepoints are
 added for the clk_set_rate() "range" functions, similar to the tracepoints we
 already have for clk_set_rate() and we added a column to debugfs to help
 developers understand the hardware enable state of clks in case firmware or
 bootloader state is different than what is expected. Overall the core changes
 are mostly improving the clk driver writing experience.
 
 At the driver level, we have the usual collection of driver updates and new
 drivers for new SoCs. This time around the Qualcomm folks introduced a good
 handful of clk drivers for various parts of three or four SoCs. The SiFive
 folks added a new clk driver for their FU740 SoCs, coming in second on the
 diffstat and then Atmel AT91 and Amlogic SoCs had lots of work done after that
 for various new features. One last thing to note in the driver area is that the
 i.MX driver has gained a new binding to support SCU clks after being on the
 list for many months. It uses a two cell binding which is sort of rare in clk
 DT bindings. Beyond that we have the usual set of driver fixes and tweaks that
 come from more testing and finding out that some configuration was wrong or
 that a driver could support being built as a module.
 
 Core:
  - Add some trace points for clk_set_rate() "range" functions
  - Add hardware enable information to clk_summary debugfs
  - Replace clk-provider.h with of_clk.h when possible
  - Add devm variant of clk_notifier_register()
  - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw
 
 New Drivers:
  - Bindings for Canaan K210 SoC clks
  - Support for SiFive FU740 PRCI
  - Camera clks on Qualcomm SC7180 SoCs
  - GCC and RPMh clks on Qualcomm SDX55 SoCs
  - RPMh clks on Qualcomm SM8350 SoCs
  - LPASS clks on Qualcomm SM8250 SoCs
 
 Updates:
  - DVFS support for AT91 clk driver
  - Update git repo branch for Renesas clock drivers
  - Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U
  - Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E
  - Stop using __raw_*() I/O accessors in Renesas clk drivers
  - One more conversion of DT bindings to json-schema
  - Make i.MX clk-gate2 driver more flexible
  - New two cell binding for i.MX SCU clks
  - Drop of_match_ptr() in i.MX8 clk drivers
  - Add arch dependencies for Rockchip clk drivers
  - Fix i2s on Rockchip rk3066
  - Add MIPI DSI clks on Amlogic axg and g12 SoCs
  - Support modular builds of Amlogic clk drivers
  - Fix an Amlogic Video PLL clock dependency
  - Samsung Kconfig dependencies updates for better compile test coverage
  - Refactoring of the Samsung PLL clocks driver
  - Small Tegra driver cleanups
  - Minor fixes to Ingenic and VC5 clk drivers
  - Cleanup patches to remove unused variables and plug memory leaks
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The core framework got some nice improvements this time around. We
  gained the ability to get struct clk pointers from a struct clk_hw so
  that clk providers can consume the clks they provide, if they need to
  do something like that. This has been a long missing part of the clk
  provider API that will help us move away from exposing a struct clk
  pointer in the struct clk_hw. Tracepoints are added for the
  clk_set_rate() "range" functions, similar to the tracepoints we
  already have for clk_set_rate() and we added a column to debugfs to
  help developers understand the hardware enable state of clks in case
  firmware or bootloader state is different than what is expected.
  Overall the core changes are mostly improving the clk driver writing
  experience.

  At the driver level, we have the usual collection of driver updates
  and new drivers for new SoCs. This time around the Qualcomm folks
  introduced a good handful of clk drivers for various parts of three or
  four SoCs. The SiFive folks added a new clk driver for their FU740
  SoCs, coming in second on the diffstat and then Atmel AT91 and Amlogic
  SoCs had lots of work done after that for various new features. One
  last thing to note in the driver area is that the i.MX driver has
  gained a new binding to support SCU clks after being on the list for
  many months. It uses a two cell binding which is sort of rare in clk
  DT bindings. Beyond that we have the usual set of driver fixes and
  tweaks that come from more testing and finding out that some
  configuration was wrong or that a driver could support being built as
  a module.

  Summary:

  Core:
   - Add some trace points for clk_set_rate() "range" functions
   - Add hardware enable information to clk_summary debugfs
   - Replace clk-provider.h with of_clk.h when possible
   - Add devm variant of clk_notifier_register()
   - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw

  New Drivers:
   - Bindings for Canaan K210 SoC clks
   - Support for SiFive FU740 PRCI
   - Camera clks on Qualcomm SC7180 SoCs
   - GCC and RPMh clks on Qualcomm SDX55 SoCs
   - RPMh clks on Qualcomm SM8350 SoCs
   - LPASS clks on Qualcomm SM8250 SoCs

  Updates:
   - DVFS support for AT91 clk driver
   - Update git repo branch for Renesas clock drivers
   - Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U
   - Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E
   - Stop using __raw_*() I/O accessors in Renesas clk drivers
   - One more conversion of DT bindings to json-schema
   - Make i.MX clk-gate2 driver more flexible
   - New two cell binding for i.MX SCU clks
   - Drop of_match_ptr() in i.MX8 clk drivers
   - Add arch dependencies for Rockchip clk drivers
   - Fix i2s on Rockchip rk3066
   - Add MIPI DSI clks on Amlogic axg and g12 SoCs
   - Support modular builds of Amlogic clk drivers
   - Fix an Amlogic Video PLL clock dependency
   - Samsung Kconfig dependencies updates for better compile test coverage
   - Refactoring of the Samsung PLL clocks driver
   - Small Tegra driver cleanups
   - Minor fixes to Ingenic and VC5 clk drivers
   - Cleanup patches to remove unused variables and plug memory leaks"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits)
  dt-binding: clock: Document canaan,k210-clk bindings
  dt-bindings: Add Canaan vendor prefix
  clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"
  clk: ingenic: Fix divider calculation with div tables
  clk: sunxi-ng: Make sure divider tables have sentinel
  clk: s2mps11: Fix a resource leak in error handling paths in the probe function
  clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
  clk: si5351: Wait for bit clear after PLL reset
  clk: at91: sam9x60: remove atmel,osc-bypass support
  clk: at91: sama7g5: register cpu clock
  clk: at91: clk-master: re-factor master clock
  clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
  clk: at91: sama7g5: decrease lower limit for MCK0 rate
  clk: at91: sama7g5: remove mck0 from parent list of other clocks
  clk: at91: clk-sam9x60-pll: allow runtime changes for pll
  clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
  clk: at91: clk-master: add 5th divisor for mck master
  clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
  dt-bindings: clock: at91: add sama7g5 pll defines
  clk: at91: sama7g5: fix compilation error
  ...
2020-12-21 10:39:37 -08:00
Stephen Boyd
abe7e32f1d Merge branches 'clk-ingenic', 'clk-vc5', 'clk-cleanup', 'clk-canaan' and 'clk-marvell' into clk-next
- Bindings for Canaan K210 SoC clks

* clk-ingenic:
  clk: ingenic: Fix divider calculation with div tables

* clk-vc5:
  clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"

* clk-cleanup:
  clk: sunxi-ng: Make sure divider tables have sentinel
  clk: s2mps11: Fix a resource leak in error handling paths in the probe function
  clk: bcm: dvp: Add MODULE_DEVICE_TABLE()
  clk: bcm: dvp: drop a variable that is assigned to only

* clk-canaan:
  dt-binding: clock: Document canaan,k210-clk bindings
  dt-bindings: Add Canaan vendor prefix

* clk-marvell:
  clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
2020-12-20 17:18:05 -08:00
Stephen Boyd
b53a1603b4 Merge branches 'clk-ti', 'clk-analog', 'clk-trace', 'clk-at91' and 'clk-silabs' into clk-next
- Add some trace points for clk_set_rate() "range" functions
 - DVFS support for AT91 clk driver

* clk-ti:
  clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs
  clk: ti: Fix memleak in ti_fapll_synth_setup

* clk-analog:
  clk: axi-clkgen: move the OF table at the bottom of the file
  clk: axi-clkgen: wrap limits in a struct and keep copy on the state object
  dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format

* clk-trace:
  clk: Trace clk_set_rate() "range" functions

* clk-at91:
  clk: at91: sam9x60: remove atmel,osc-bypass support
  clk: at91: sama7g5: register cpu clock
  clk: at91: clk-master: re-factor master clock
  clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
  clk: at91: sama7g5: decrease lower limit for MCK0 rate
  clk: at91: sama7g5: remove mck0 from parent list of other clocks
  clk: at91: clk-sam9x60-pll: allow runtime changes for pll
  clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
  clk: at91: clk-master: add 5th divisor for mck master
  clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
  dt-bindings: clock: at91: add sama7g5 pll defines
  clk: at91: sama7g5: fix compilation error

* clk-silabs:
  clk: si5351: Wait for bit clear after PLL reset
2020-12-20 17:17:51 -08:00
Stephen Boyd
699eda2814 Merge branches 'clk-tegra', 'clk-imx', 'clk-sifive', 'clk-mediatek' and 'clk-summary' into clk-next
- Support for SiFive FU740 PRCI
 - Add hardware enable information to clk_summary debugfs

* clk-tegra:
  clk: tegra: Fix duplicated SE clock entry
  clk: tegra: bpmp: Clamp clock rates on requests
  clk: tegra: Do not return 0 on failure

* clk-imx: (24 commits)
  clk: imx: scu: remove the calling of device_is_bound
  clk: imx: scu: Make pd_np with static keyword
  clk: imx8mq: drop of_match_ptr from of_device_id table
  clk: imx8mp: drop of_match_ptr from of_device_id table
  clk: imx8mn: drop of_match_ptr from of_device_id table
  clk: imx8mm: drop of_match_ptr from of_device_id table
  clk: imx: gate2: Remove unused variable ret
  clk: imx: gate2: Add locking in is_enabled op
  clk: imx: gate2: Add cgr_mask for more flexible number of control bits
  clk: imx: gate2: Check if clock is enabled against cgr_val
  clk: imx: gate2: Keep the register writing in on place
  clk: imx: gate2: Remove the IMX_CLK_GATE2_SINGLE_BIT special case
  clk: imx: scu: fix build break when compiled as modules
  clk: imx: remove redundant assignment to pointer np
  clk: imx: remove unneeded semicolon
  clk: imx: lpcg: add suspend/resume support
  clk: imx: clk-imx8qxp-lpcg: add runtime pm support
  clk: imx: lpcg: allow lpcg clk to take device pointer
  clk: imx: imx8qxp-lpcg: add parsing clocks from device tree
  clk: imx: scu: add suspend/resume support
  ...

* clk-sifive:
  clk: sifive: Add clock enable and disable ops
  clk: sifive: Fix the wrong bit field shift
  clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
  clk: sifive: Use common name for prci configuration
  clk: sifive: Extract prci core to common base
  dt-bindings: fu740: prci: add YAML documentation for the FU740 PRCI

* clk-mediatek:
  clk: mediatek: Make mtk_clk_register_mux() a static function

* clk-summary:
  clk: Add hardware-enable column to clk summary
2020-12-20 17:17:37 -08:00
Stephen Boyd
d240d4c205 Merge branches 'clk-amlogic', 'clk-rockchip', 'clk-of', 'clk-freescale' and 'clk-unused' into clk-next
- Replace clk-provider.h with of_clk.h when possible

* clk-amlogic:
  clk: meson: g12a: add MIPI DSI Host Pixel Clock
  dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings
  clk: meson: enable building as modules
  clk: meson: Kconfig: fix dependency for G12A
  clk: meson: axg: add MIPI DSI Host clock
  clk: meson: axg: add Video Clocks
  dt-bindings: clk: axg-clkc: add MIPI DSI Host clock binding
  dt-bindings: clk: axg-clkc: add Video Clocks

* clk-rockchip:
  clk: rockchip: fix i2s gate bits on rk3066 and rk3188
  clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks
  clk: rockchip: Remove redundant null check before clk_prepare_enable
  clk: rockchip: Add appropriate arch dependencies

* clk-of:
  xtensa: Replace <linux/clk-provider.h> by <linux/of_clk.h>
  sh: boards: Replace <linux/clk-provider.h> by <linux/of_clk.h>

* clk-freescale:
  clk: fsl-flexspi: new driver
  dt-bindings: clock: document the fsl-flexspi-clk device
  clk: divider: add devm_clk_hw_register_divider_table()
  clk: qoriq: provide constants for the type
  clk: fsl-sai: use devm_clk_hw_register_composite_pdata()
  clk: composite: add devm_clk_hw_register_composite_pdata()
  clk: fsl-sai: fix memory leak
  clk: qoriq: Add platform dependencies

* clk-unused:
  clk: scpi: mark scpi_clk_match as maybe unused
  clk: pwm: drop of_match_ptr from of_device_id table
2020-12-20 17:17:25 -08:00
Stephen Boyd
23cae54f52 Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', 'clk-renesas' and 'clk-samsung' into clk-next
- Camera clks on Qualcomm SC7180 SoCs
 - GCC and RPMh clks on Qualcomm SDX55 SoCs
 - RPMh clks on Qualcomm SM8350 SoCs
 - LPASS clks on Qualcomm SM8250 SoCs
 - Add devm variant of clk_notifier_register()
 - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw

* clk-doc:
  clk: fix a kernel-doc markup

* clk-qcom: (27 commits)
  clk: qcom: rpmh: add support for SM8350 rpmh clocks
  dt-bindings: clock: Add RPMHCC bindings for SM8350
  clk: qcom: lpasscc: Introduce pm autosuspend for SC7180
  clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2
  clk: qcom: gcc-sc7180: Use floor ops for sdcc clks
  clk: qcom: Add GDSC support for SDX55 GCC
  dt-bindings: clock: Add GDSC in SDX55 GCC
  clk: qcom: Add support for SDX55 RPMh clocks
  dt-bindings: clock: Introduce RPMHCC bindings for SDX55
  clk: qcom: Add SDX55 GCC support
  dt-bindings: clock: Add SDX55 GCC clock bindings
  clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic"
  clk: qcom: rpmh: Add CE clock on sdm845.
  dt-bindings: clock: Add entry for crypto engine RPMH clock resource
  clk: qcom: dispcc-sm8250: handle MMCX power domain
  clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones
  clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init()
  clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocks
  clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks
  dt-bindings: clock: Add support for LPASS Always ON Controller
  ...

* clk-simplify:
  clk: remove unneeded dead-store initialization

* clk-hw:
  clk: meson: g12: use devm variant to register notifiers
  clk: add devm variant of clk_notifier_register
  clk: meson: g12: drop use of __clk_lookup()
  clk: add api to get clk consumer from clk_hw
  clk: avoid devm_clk_release name clash

* clk-renesas:
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema
  clk: renesas: sh73a0: Stop using __raw_*() I/O accessors
  clk: renesas: r8a774c0: Add RPC clocks
  clk: renesas: r8a779a0: Fix R and OSC clocks
  clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv
  clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get()
  clk: renesas: r8a774b1: Add RPC clocks
  clk: renesas: r8a774a1: Add RPC clocks
  clk: renesas: r8a779a0: Add VIN clocks
  clk: renesas: r8a779a0: Add CSI4[0-3] clocks
  MAINTAINERS: Update git repo for Renesas clock drivers
  clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static
  clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI

* clk-samsung:
  clk: samsung: Prevent potential endless loop in the PLL ops
  clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
2020-12-20 17:17:01 -08:00
Geert Uytterhoeven
4b003f5fca clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"
Commit 45c940184b ("dt-bindings: clk: versaclock5: convert to
yaml") accidentally changed "idt,voltage-microvolts" to
"idt,voltage-microvolt" in the DT bindings, while the driver still used
the former.

Update the driver to match the bindings, as
Documentation/devicetree/bindings/property-units.txt actually recommends
using "microvolt".

Fixes: 260249f929 ("clk: vc5: Enable addition output configurations of the Versaclock")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201218125253.3815567-1-geert+renesas@glider.be
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 16:08:51 -08:00
Paul Cercueil
11a163f2c7 clk: ingenic: Fix divider calculation with div tables
The previous code assumed that a higher hardware value always resulted
in a bigger divider, which is correct for the regular clocks, but is
an invalid assumption when a divider table is provided for the clock.

Perfect example of this is the PLL0_HALF clock, which applies a /2
divider with the hardware value 0, and a /1 divider otherwise.

Fixes: a9fa2893fc ("clk: ingenic: Add support for divider tables")
Cc: <stable@vger.kernel.org> # 5.2
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 16:04:58 -08:00
Jernej Skrabec
48f68de00c clk: sunxi-ng: Make sure divider tables have sentinel
Two clock divider tables are missing sentinel at the end. Effect of that
is that clock framework reads past the last entry. Fix that with adding
sentinel at the end.

Issue was discovered with KASan.

Fixes: 0577e4853b ("clk: sunxi-ng: Add H3 clocks")
Fixes: c6a0637460 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Link: https://lore.kernel.org/r/20201202203817.438713-1-jernej.skrabec@siol.net
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 15:54:02 -08:00
Christophe JAILLET
d2d94fc567 clk: s2mps11: Fix a resource leak in error handling paths in the probe function
Some resource should be released in the error handling path of the probe
function, as already done in the remove function.

The remove function was fixed in commit bf416bd457 ("clk: s2mps11: Add
missing of_node_put and of_clk_del_provider")

Fixes: 7cc560dea4 ("clk: s2mps11: Add support for s2mps11")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/20201212122818.86195-1-christophe.jaillet@wanadoo.fr
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 15:53:31 -08:00
Terry Zhou
6f37689cf6 clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
There is an error in the current code that the XTAL MODE
pin was set to NB MPP1_31 which should be NB MPP1_9.
The latch register of NB MPP1_9 has different offset of 0x8.

Signed-off-by: Terry Zhou <bjzhou@marvell.com>
[pali: Fix pin name in commit message]
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 7ea8250406 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20201106100039.11385-1-pali@kernel.org
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 15:51:18 -08:00
Sascha Hauer
5142cbcea3 clk: si5351: Wait for bit clear after PLL reset
Documentation states that SI5351_PLL_RESET_B and SI5351_PLL_RESET_A bits
are self clearing bits, so wait until they are cleared before
continuing.
This fixes a case when the clock doesn't come up properly after a PLL
reset. It worked properly when the frequency was below 900MHz, but with
900MHz it only works when we are waiting for the bit to clear.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20201130091033.1687-1-s.hauer@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 15:49:54 -08:00
Alexandre Belloni
01324f9e88 clk: at91: sam9x60: remove atmel,osc-bypass support
The sam9x60 doesn't have the MOSCXTBY bit to enable the crystal oscillator
bypass.

Fixes: 01e2113de9 ("clk: at91: add sam9x60 pmc driver")
Reported-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20201202125816.168618-1-alexandre.belloni@bootlin.com
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 15:33:00 -08:00
Claudiu Beznea
91f3bf0d53 clk: at91: sama7g5: register cpu clock
Register CPU clock as being the master clock prescaler. This would
be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
frequencies supported by SAMA7G5 could be directly received from
CPUPLL + master clock prescaler and the extra divider would do no work in
case it would be enabled.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:56 -08:00
Claudiu Beznea
7a110b9107 clk: at91: clk-master: re-factor master clock
Re-factor master clock driver by splitting it into 2 clocks: prescaller
and divider clocks. Based on registered clock flags the prescaler's rate
could be changed at runtime. This is necessary for platforms supporting
DVFS (e.g. SAMA7G5) where master clock could be changed at run-time.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:56 -08:00
Claudiu Beznea
120d5d8b46 clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:56 -08:00
Claudiu Beznea
f803858af8 clk: at91: sama7g5: decrease lower limit for MCK0 rate
On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
also changed by DVFS to avoid over/under clocking of MCK0 consumers.
The lower limit is changed to be able to set MCK0 accordingly by
DVFS.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:56 -08:00
Claudiu Beznea
4011f03ee4 clk: at91: sama7g5: remove mck0 from parent list of other clocks
MCK0 is changed at runtime by DVFS. Due to this, since not all IPs
are glitch free aware at MCK0 changes, remove MCK0 from parent list
of other clocks (e.g. generic clock, programmable/system clock, MCKX).

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-8-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:56 -08:00
Claudiu Beznea
8dc4af8bef clk: at91: clk-sam9x60-pll: allow runtime changes for pll
Allow runtime frequency changes for PLLs registered with proper flags.
This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:55 -08:00
Eugen Hristev
0bb4623f13 clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:55 -08:00
Eugen Hristev
e26b3006ff clk: at91: clk-master: add 5th divisor for mck master
clk-master can have 5 divisors with a field width of 3 bits
on some products.

Change the mask and number of divisors accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-5-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:55 -08:00
Eugen Hristev
83d0028773 clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
from phandle in DT.

Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[claudiu.beznea@microchip.com: adapt commit message, add CPU PLL]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:55 -08:00
Eugen Hristev
3d86ee17d4 dt-bindings: clock: at91: add sama7g5 pll defines
Add SAMA7G5 specific PLL defines to be referenced in a phandle as a
PMC_TYPE_CORE clock.

Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:55 -08:00
Claudiu Beznea
91274497c7 clk: at91: sama7g5: fix compilation error
pmc_data_allocate() has been changed. pmc_data_free() was removed.
Adapt the code taking this into consideration. With this the programmable
clocks were also saved in sama7g5_pmc so that they could be later
referenced.

Fixes: cb783bbbcf ("clk: at91: sama7g5: add clock support for sama7g5")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:55 -08:00
Nicolas Saenz Julienne
be439cc4c4 clk: bcm: dvp: Add MODULE_DEVICE_TABLE()
Add MODULE_DEVICE_TABLE() so as to be able to use the driver as a
module. More precisely, for the driver to be loaded automatically at
boot.

Fixes: 1bc9597271 ("clk: bcm: Add BCM2711 DVP driver")
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Link: https://lore.kernel.org/r/20201202103518.21889-1-nsaenzjulienne@suse.de
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:48:29 -08:00
Uwe Kleine-König
c82cf05190 clk: bcm: dvp: drop a variable that is assigned to only
The third parameter to devm_platform_get_and_ioremap_resource() is used
only to provide the used resource. As this variable isn't used
afterwards, switch to the function devm_platform_ioremap_resource()
which doesn't provide this output parameter.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20201120132121.2678997-1-u.kleine-koenig@pengutronix.de
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:45:47 -08:00
Maxime Ripard
03813d9b7d clk: Trace clk_set_rate() "range" functions
The clk_set_rate "range" functions don't have any tracepoints even
though it might be useful. Add some.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20201207105050.2096917-1-maxime@cerno.tech
[sboyd@kernel.org: Reword commit text]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:54:31 -08:00
Alexandru Ardelean
16214f97f4 clk: axi-clkgen: move the OF table at the bottom of the file
The change is mostly cosmetic. No functional changes.
Since the driver now uses of_device_get_match_data() to obtain some driver
specific info, there is no need to define the OF table before the probe
function.

Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20201203074037.26940-2-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:52:54 -08:00
Alexandru Ardelean
ac1ee86a9c clk: axi-clkgen: wrap limits in a struct and keep copy on the state object
Up until the these limits were global/hard-coded, since they are typically
limits of the fabric.

However, since this is an FPGA generated clock, this may run on setups
where one clock is on a fabric, and another one synthesized on another
fabric connected via PCIe (or some other inter-connect, and then these
limits need to be adjusted for each instance of the AXI CLKGEN.

This change wraps the current constants in 'axi_clkgen_limits' struct and
the 'axi_clkgen' instance keeps a copy of these limits, which is
initialized at probe from the default limits.

The limits are stored on the device-tree OF table, so that we can adjust
them via the compatible string.

Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:52:54 -08:00
David Shah
66cc7af381 clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs
Having the ABE DPLL ref and bypass muxes set to different inputs was
causing the DPLL not to lock when TIMER8 was used, as it is in the Pyra
for the backlight.

This patch fixes this by setting abe_dpll_bypass_clk_mux to sys_32k_ck
in omap5xxx_dt_clk_init.

A similar patch may also be needed for OMAP44xx which has similar code
in omap4xxx_dt_clk_init, but I have not added this as I have no hardware
to test on.

Signed-off-by: David Shah <dave@ds0.me>
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Link: https://lore.kernel.org/r/1d3abe2512054866cc2ea7b2592238f4fa06502a.1607253531.git.hns@goldelico.com
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:47:01 -08:00
Zhang Qilong
8c6239f6e9 clk: ti: Fix memleak in ti_fapll_synth_setup
If clk_register fails, we should goto free branch
before function returns to prevent memleak.

Fixes: 163152cbbe ("clk: ti: Add support for FAPLL on dm816x")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
Link: https://lore.kernel.org/r/20201113131623.2098222-1-zhangqilong3@huawei.com
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:46:37 -08:00
Dmitry Osipenko
bf6d43d723 clk: Add hardware-enable column to clk summary
Add "hardware enable" column to the clk summary in order to show actual
hardware enable-state of all clocks. The possible states are "Y/N/?",
where question mark means that state is unknown, i.e. clock isn't a
mux and clk-driver doesn't support is_enabled() callback for this clock.

In conjunction with clk_ignore_unused, this tells us what unused clocks
are left enabled after bootloader. This is also a useful aid for
debugging interactions with firmware which changes clock states without
notifying kernel.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201115203432.13934-1-digetx@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:43:32 -08:00
Weiyi Lu
2aeff9d8c8 clk: mediatek: Make mtk_clk_register_mux() a static function
mtk_clk_register_mux() should be a static function

Fixes: a3ae549917 ("clk: mediatek: Add new clkmux register API")
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Link: https://lore.kernel.org/r/1605256192-31307-1-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 00:41:54 -08:00
Linus Torvalds
accefff5b5 ARM: SoC updates for OMAP GenPD
These are additional updates for the power domain support on OMAP,
 moving to an implementation based on device tree information instead of
 SoC specific code. This is the latest step in the ongoing process for
 moving code out of arch/arm/mach-omap2.
 
 I kept this separate from the other driver changes since it touches
 code in multiple areas.
 
 There is one conflict in the dra7.dts file, which adds another node
 in a different branch. Watch out for adding the trailing '};'
 both times.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-soc-omap-genpd-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC OMAP GenPD updates from Arnd Bergmann:
 "These are additional updates for the power domain support on OMAP,
  moving to an implementation based on device tree information instead
  of SoC specific code. This is the latest step in the ongoing process
  for moving code out of arch/arm/mach-omap2.

  I kept this separate from the other driver changes since it touches
  code in multiple areas"

* tag 'arm-soc-omap-genpd-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (51 commits)
  ARM: OMAP2+: Fix am4 only build after genpd changes
  ARM: dts: Configure power domain for omap5 dss
  ARM: dts: omap5: add remaining PRM instances
  soc: ti: omap-prm: omap5: add genpd support for remaining PRM instances
  ARM: OMAP2+: Drop legacy platform data for dra7 gpmc
  ARM: dts: Configure interconnect target module for dra7 iva
  ARM: dts: dra7: add remaining PRM instances
  soc: ti: omap-prm: dra7: add genpd support for remaining PRM instances
  clk: ti: dra7: Drop idlest polling from IVA clkctrl clocks
  ARM: OMAP2+: Drop legacy platform data for omap4 gpmc
  ARM: OMAP2+: Drop legacy platform data for omap4 iva
  ARM: dts: Configure power domain for omap4 dsp
  ARM: dts: Configure power domain for omap4 dss
  ARM: dts: omap4: add remaining PRM instances
  soc: ti: omap-prm: omap4: add genpd support for remaining PRM instances
  clk: ti: omap4: Drop idlest polling from IVA clkctrl clocks
  ARM: OMAP2+: Drop legacy remaining legacy platform data for am4
  ARM: dts: Use simple-pm-bus for genpd for am4 l3
  ARM: dts: Move am4 l3 noc to a separate node
  ARM: dts: Use simple-pm-bus for genpd for am4 l4_per
  ...
2020-12-16 16:53:54 -08:00
Linus Torvalds
48c1c40ab4 ARM: SoC drivers for v5.11
There are a couple of subsystems maintained by other people that
 merge their drivers through the SoC tree, those changes include:
 
  - The SCMI firmware framework gains support for sensor notifications
    and for controlling voltage domains.
 
  - A large update for the Tegra memory controller driver, integrating
    it better with the interconnect framework
 
  - The memory controller subsystem gains support for Mediatek MT8192
 
  - The reset controller framework gains support for sharing pulsed
    resets
 
 For Soc specific drivers in drivers/soc, the main changes are
 
  - The Allwinner/sunxi MBUS gets a rework for the way it handles
    dma_map_ops and offsets between physical and dma address spaces.
 
  - An errata fix plus some cleanups for Freescale Layerscape SoCs
 
  - A cleanup for renesas drivers regarding MMIO accesses.
 
  - New SoC specific drivers for Mediatek MT8192 and MT8183 power domains
 
  - New SoC specific drivers for Aspeed AST2600 LPC bus control
    and SoC identification.
 
  - Core Power Domain support for Qualcomm MSM8916, MSM8939, SDM660
    and SDX55.
 
  - A rework of the TI AM33xx 'genpd' power domain support to use
    information from DT instead of platform data
 
  - Support for TI AM64x SoCs
 
  - Allow building some Amlogic drivers as modules instead of built-in
 
 Finally, there are numerous cleanups and smaller bug fixes for
 Mediatek, Tegra, Samsung, Qualcomm, TI OMAP, Amlogic, Rockchips,
 Renesas, and Xilinx SoCs.
 
 There is a trivial conflict in the cedrus driver, with two branches
 adding the same CEDRUS_CAPABILITY_H265_DEC flag, and another trivial
 remove/remove conflict in linux/dma-mapping.h.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-soc-drivers-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "There are a couple of subsystems maintained by other people that merge
  their drivers through the SoC tree, those changes include:

   - The SCMI firmware framework gains support for sensor notifications
     and for controlling voltage domains.

   - A large update for the Tegra memory controller driver, integrating
     it better with the interconnect framework

   - The memory controller subsystem gains support for Mediatek MT8192

   - The reset controller framework gains support for sharing pulsed
     resets

  For Soc specific drivers in drivers/soc, the main changes are

   - The Allwinner/sunxi MBUS gets a rework for the way it handles
     dma_map_ops and offsets between physical and dma address spaces.

   - An errata fix plus some cleanups for Freescale Layerscape SoCs

   - A cleanup for renesas drivers regarding MMIO accesses.

   - New SoC specific drivers for Mediatek MT8192 and MT8183 power
     domains

   - New SoC specific drivers for Aspeed AST2600 LPC bus control and SoC
     identification.

   - Core Power Domain support for Qualcomm MSM8916, MSM8939, SDM660 and
     SDX55.

   - A rework of the TI AM33xx 'genpd' power domain support to use
     information from DT instead of platform data

   - Support for TI AM64x SoCs

   - Allow building some Amlogic drivers as modules instead of built-in

  Finally, there are numerous cleanups and smaller bug fixes for
  Mediatek, Tegra, Samsung, Qualcomm, TI OMAP, Amlogic, Rockchips,
  Renesas, and Xilinx SoCs"

* tag 'arm-soc-drivers-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (222 commits)
  soc: mediatek: mmsys: Specify HAS_IOMEM dependency for MTK_MMSYS
  firmware: xilinx: Properly align function parameter
  firmware: xilinx: Add a blank line after function declaration
  firmware: xilinx: Remove additional newline
  firmware: xilinx: Fix kernel-doc warnings
  firmware: xlnx-zynqmp: fix compilation warning
  soc: xilinx: vcu: add missing register NUM_CORE
  soc: xilinx: vcu: use vcu-settings syscon registers
  dt-bindings: soc: xlnx: extract xlnx, vcu-settings to separate binding
  soc: xilinx: vcu: drop useless success message
  clk: samsung: mark PM functions as __maybe_unused
  soc: samsung: exynos-chipid: initialize later - with arch_initcall
  soc: samsung: exynos-chipid: order list of SoCs by name
  memory: jz4780_nemc: Fix potential NULL dereference in jz4780_nemc_probe()
  memory: ti-emif-sram: only build for ARMv7
  memory: tegra30: Support interconnect framework
  memory: tegra20: Support hardware versioning and clean up OPP table initialization
  dt-bindings: memory: tegra20-emc: Document opp-supported-hw property
  soc: rockchip: io-domain: Fix error return code in rockchip_iodomain_probe()
  reset-controller: ti: force the write operation when assert or deassert
  ...
2020-12-16 16:38:41 -08:00
Pragnesh Patel
732374a0b4 clk: sifive: Add clock enable and disable ops
Add new functions "sifive_prci_clock_enable(), sifive_prci_clock_disable()
and sifive_clk_is_enabled()" to enable or disable the PRCI clock

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Zong Li <zong.li@sifive.com>
Link: https://lore.kernel.org/r/20201209094916.17383-6-zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-16 12:23:13 -08:00
Zong Li
263ac39085 clk: sifive: Fix the wrong bit field shift
The clk enable bit should be 31 instead of 24.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reported-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Link: https://lore.kernel.org/r/20201209094916.17383-5-zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-16 12:23:12 -08:00
Zong Li
efc91ae43c clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
Add driver code for the SiFive FU740 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU740 device and
implements SoC-level clock tree controls and dividers.

The link of unmatched as follow, and the U740-C000 manual would
be present in the same page as soon.
https://www.sifive.com/boards/hifive-unmatched

This driver contains bug fixes and contributions from
Henry Styles <hes@sifive.com>
Erik Danie <erik.danie@sifive.com>
Pragnesh Patel <pragnesh.patel@sifive.com>

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: Henry Styles <hes@sifive.com>
Cc: Erik Danie <erik.danie@sifive.com>
Cc: Pragnesh Patel <pragnesh.patel@sifive.com>
Link: https://lore.kernel.org/r/20201209094916.17383-4-zong.li@sifive.com
[sboyd@kernel.org: Include header to silence sparse]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-16 12:22:59 -08:00
Zong Li
28108fc8a0 clk: sifive: Use common name for prci configuration
Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
patch is prepared for fu740 support.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Link: https://lore.kernel.org/r/20201209094916.17383-3-zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-16 12:22:59 -08:00
Zong Li
c816e1ddf2 clk: sifive: Extract prci core to common base
Extract common core of prci driver to an independent file, it could
allow other chips to reuse it. Separate SoCs-dependent code 'fu540'
from prci core, then we can easily add 'fu740' later.

Almost these changes are code movement. The different is adding the
private data for each SoC use, so it needs to get match data in probe
callback function, then use the data for initialization.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Link: https://lore.kernel.org/r/20201209094916.17383-2-zong.li@sifive.com
[sboyd@kernel.org: Include header to silence sparse]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-16 12:22:39 -08:00
Linus Torvalds
b4ec805464 Power management updates for 5.11-rc1
- Use local_clock() instead of jiffies in the cpufreq statistics to
    improve accuracy (Viresh Kumar).
 
  - Fix up OPP usage in the cpufreq-dt and qcom-cpufreq-nvmem cpufreq
    drivers (Viresh Kumar).
 
  - Clean up the cpufreq core, the intel_pstate driver and the
    schedutil cpufreq governor (Rafael Wysocki).
 
  - Fix up error code paths in the sti-cpufreq and mediatek cpufreq
    drivers (Yangtao Li, Qinglang Miao).
 
  - Fix cpufreq_online() to return error codes instead of success (0)
    in all cases when it fails (Wang ShaoBo).
 
  - Add mt8167 support to the mediatek cpufreq driver and blacklist
    mt8516 in the cpufreq-dt-platdev driver (Fabien Parent).
 
  - Modify the tegra194 cpufreq driver to always return values from
    the frequency table as the current frequency and clean up that
    driver (Sumit Gupta, Jon Hunter).
 
  - Modify the arm_scmi cpufreq driver to allow it to discover the
    power scale present in the performance protocol and provide this
    information to the Energy Model (Lukasz Luba).
 
  - Add missing MODULE_DEVICE_TABLE to several cpufreq drivers (Pali
    Rohár).
 
  - Clean up the CPPC cpufreq driver (Ionela Voinescu).
 
  - Fix NVMEM_IMX_OCOTP dependency in the imx cpufreq driver (Arnd
    Bergmann).
 
  - Rework the poling interval selection for the polling state in
    cpuidle (Mel Gorman).
 
  - Enable suspend-to-idle for PSCI OSI mode in the PSCI cpuidle
    driver (Ulf Hansson).
 
  - Modify the OPP framework to support empty (node-less) OPP tables
    in DT for passing dependency information (Nicola Mazzucato).
 
  - Fix potential lockdep issue in the OPP core and clean up the OPP
    core (Viresh Kumar).
 
  - Modify dev_pm_opp_put_regulators() to accept a NULL argument and
    update its users accordingly (Viresh Kumar).
 
  - Add frequency changes tracepoint to devfreq (Matthias Kaehlcke).
 
  - Add support for governor feature flags to devfreq, make devfreq
    sysfs file permissions depend on the governor and clean up the
    devfreq core (Chanwoo Choi).
 
  - Clean up the tegra20 devfreq driver and deprecate it to allow
    another driver based on EMC_STAT to be used instead of it (Dmitry
    Osipenko).
 
  - Add interconnect support to the tegra30 devfreq driver, allow it
    to take the interconnect and OPP information from DT and clean it
    up ((Dmitry Osipenko).
 
  - Add interconnect support to the exynos-bus devfreq driver along
    with interconnect properties documentation (Sylwester Nawrocki).
 
  - Add suport for AMD Fam17h and Fam19h processors to the RAPL power
    capping driver (Victor Ding, Kim Phillips).
 
  - Fix handling of overly long constraint names in the powercap
    framework (Lukasz Luba).
 
  - Fix the wakeup configuration handling for bridges in the ACPI
    device power management core (Rafael Wysocki).
 
  - Add support for using an abstract scale for power units in the
    Energy Model (EM) and document it (Lukasz Luba).
 
  - Add em_cpu_energy() micro-optimization to the EM (Pavankumar
    Kondeti).
 
  - Modify the generic power domains (genpd) framwework to support
    suspend-to-idle (Ulf Hansson).
 
  - Fix creation of debugfs nodes in genpd (Thierry Strudel).
 
  - Clean up genpd (Lina Iyer).
 
  - Clean up the core system-wide suspend code and make it print
    driver flags for devices with debug enabled (Alex Shi, Patrice
    Chotard, Chen Yu).
 
  - Modify the ACPI system reboot code to make it prepare for system
    power off to avoid confusing the platform firmware (Kai-Heng Feng).
 
  - Update the pm-graph (multiple changes, mostly usability-related)
    and cpupower (online and offline CPU information support) PM
    utilities (Todd Brandt, Brahadambal Srinivasan).
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Merge tag 'pm-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

Pull power management updates from Rafael Wysocki:
 "These update cpufreq (core and drivers), cpuidle (polling state
  implementation and the PSCI driver), the OPP (operating performance
  points) framework, devfreq (core and drivers), the power capping RAPL
  (Running Average Power Limit) driver, the Energy Model support, the
  generic power domains (genpd) framework, the ACPI device power
  management, the core system-wide suspend code and power management
  utilities.

  Specifics:

   - Use local_clock() instead of jiffies in the cpufreq statistics to
     improve accuracy (Viresh Kumar).

   - Fix up OPP usage in the cpufreq-dt and qcom-cpufreq-nvmem cpufreq
     drivers (Viresh Kumar).

   - Clean up the cpufreq core, the intel_pstate driver and the
     schedutil cpufreq governor (Rafael Wysocki).

   - Fix up error code paths in the sti-cpufreq and mediatek cpufreq
     drivers (Yangtao Li, Qinglang Miao).

   - Fix cpufreq_online() to return error codes instead of success (0)
     in all cases when it fails (Wang ShaoBo).

   - Add mt8167 support to the mediatek cpufreq driver and blacklist
     mt8516 in the cpufreq-dt-platdev driver (Fabien Parent).

   - Modify the tegra194 cpufreq driver to always return values from the
     frequency table as the current frequency and clean up that driver
     (Sumit Gupta, Jon Hunter).

   - Modify the arm_scmi cpufreq driver to allow it to discover the
     power scale present in the performance protocol and provide this
     information to the Energy Model (Lukasz Luba).

   - Add missing MODULE_DEVICE_TABLE to several cpufreq drivers (Pali
     Rohár).

   - Clean up the CPPC cpufreq driver (Ionela Voinescu).

   - Fix NVMEM_IMX_OCOTP dependency in the imx cpufreq driver (Arnd
     Bergmann).

   - Rework the poling interval selection for the polling state in
     cpuidle (Mel Gorman).

   - Enable suspend-to-idle for PSCI OSI mode in the PSCI cpuidle driver
     (Ulf Hansson).

   - Modify the OPP framework to support empty (node-less) OPP tables in
     DT for passing dependency information (Nicola Mazzucato).

   - Fix potential lockdep issue in the OPP core and clean up the OPP
     core (Viresh Kumar).

   - Modify dev_pm_opp_put_regulators() to accept a NULL argument and
     update its users accordingly (Viresh Kumar).

   - Add frequency changes tracepoint to devfreq (Matthias Kaehlcke).

   - Add support for governor feature flags to devfreq, make devfreq
     sysfs file permissions depend on the governor and clean up the
     devfreq core (Chanwoo Choi).

   - Clean up the tegra20 devfreq driver and deprecate it to allow
     another driver based on EMC_STAT to be used instead of it (Dmitry
     Osipenko).

   - Add interconnect support to the tegra30 devfreq driver, allow it to
     take the interconnect and OPP information from DT and clean it up
     (Dmitry Osipenko).

   - Add interconnect support to the exynos-bus devfreq driver along
     with interconnect properties documentation (Sylwester Nawrocki).

   - Add suport for AMD Fam17h and Fam19h processors to the RAPL power
     capping driver (Victor Ding, Kim Phillips).

   - Fix handling of overly long constraint names in the powercap
     framework (Lukasz Luba).

   - Fix the wakeup configuration handling for bridges in the ACPI
     device power management core (Rafael Wysocki).

   - Add support for using an abstract scale for power units in the
     Energy Model (EM) and document it (Lukasz Luba).

   - Add em_cpu_energy() micro-optimization to the EM (Pavankumar
     Kondeti).

   - Modify the generic power domains (genpd) framwework to support
     suspend-to-idle (Ulf Hansson).

   - Fix creation of debugfs nodes in genpd (Thierry Strudel).

   - Clean up genpd (Lina Iyer).

   - Clean up the core system-wide suspend code and make it print driver
     flags for devices with debug enabled (Alex Shi, Patrice Chotard,
     Chen Yu).

   - Modify the ACPI system reboot code to make it prepare for system
     power off to avoid confusing the platform firmware (Kai-Heng Feng).

   - Update the pm-graph (multiple changes, mostly usability-related)
     and cpupower (online and offline CPU information support) PM
     utilities (Todd Brandt, Brahadambal Srinivasan)"

* tag 'pm-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (86 commits)
  cpufreq: Fix cpufreq_online() return value on errors
  cpufreq: Fix up several kerneldoc comments
  cpufreq: stats: Use local_clock() instead of jiffies
  cpufreq: schedutil: Simplify sugov_update_next_freq()
  cpufreq: intel_pstate: Simplify intel_cpufreq_update_pstate()
  PM: domains: create debugfs nodes when adding power domains
  opp: of: Allow empty opp-table with opp-shared
  dt-bindings: opp: Allow empty OPP tables
  media: venus: dev_pm_opp_put_*() accepts NULL argument
  drm/panfrost: dev_pm_opp_put_*() accepts NULL argument
  drm/lima: dev_pm_opp_put_*() accepts NULL argument
  PM / devfreq: exynos: dev_pm_opp_put_*() accepts NULL argument
  cpufreq: qcom-cpufreq-nvmem: dev_pm_opp_put_*() accepts NULL argument
  cpufreq: dt: dev_pm_opp_put_regulators() accepts NULL argument
  opp: Allow dev_pm_opp_put_*() APIs to accept NULL opp_table
  opp: Don't create an OPP table from dev_pm_opp_get_opp_table()
  cpufreq: dt: Don't (ab)use dev_pm_opp_get_opp_table() to create OPP table
  opp: Reduce the size of critical section in _opp_kref_release()
  PM / EM: Micro optimization in em_cpu_energy
  cpufreq: arm_scmi: Discover the power scale in performance protocol
  ...
2020-12-15 16:30:31 -08:00
Rafael J. Wysocki
d3569c149d Update devfreq for 5.11
Detailed description for this pull request:
 
 1. Update devfreq core
 - Add new devfreq_frequency tracepoint to show the frequency change
 information.
 
 - Add governor feature flag. The devfreq governor is able to
 have the specific flag in order to contain the non-common feature.
 For example, if governor contains the 'immutable' feature, don't allow
 user to change the governor via sysfs.
 
 - Add governor sysfs attribute flag for each sysfs file. Prior to that
 devfreq subsystem show the all sysfs files regardless of governor type.
 But, some sysfs fils are not supported on the specific devfreq governor.
 In order to show the only supported sysfs files according to the governor,
 clarify the access permission of sysfs attributes according to governor.
 When adding the devfreq governor, can specify the available attribute
 information by using DEVFREQ_GOV_ATTR_* constant variable. The user can
 read or write the sysfs attributes in accordance to the specified attributes.
 
 - Clean-up the code to remove the duplicate code for the devfreq tracepoint
 and to remove redundant governor_name field from struct devfreq
 
 2. Update exynos-bus.c devfreq driver
 - Add interconnect API support for the Samsung Exynos Bus Frequency driver
 of exynos-bus.c. Complementing the devfreq driver with an interconnect
 functionality allows to ensure the QoS requirements of devices accessing
 the system memory (e.g. video processing devices) are fulfilled
 and allows to avoid issues like the DMA underrun.
 
 3. Update tegra devfreq driver
 - Add interconnect support and OPP interface for tegra30-devfreq.c.
 Also, it is to guarantee the QoS requirement of some devices like
 display controller.
 
 - Move tegra20-devfreq.c from drivers/devfreq/ into driver/memory/tegra/
 in order to use the more proper monitoring feature such as EMC_STAT
 which is based in driver/memory/tegra/.
 
 - Separate the configuration information for different SoC on
 tegra30-devfrqe.c. The tegra30-devfreq.c had been supported both
 tegra30-actmon and tegra124-actmon devices. In order to use
 the more correct configuration data, separate them.
 
 - Use dev_err_probe() to handle the deferred probe error on tegra30-devfreq.c.
 
 4. Pull the request of 'Tegra SoC and clock controller changes for v5.11'
 sent by Krzysztof Kozlowski <krzk@kernel.org> in order to prevent the
 build error.
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Merge tag 'devfreq-next-for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux

Pull devfreq updates for 5.11 from Chanwoo Choi:

 1. Update devfreq core

  - Add new devfreq_frequency tracepoint to show the frequency change
    information.

  - Add governor feature flag. The devfreq governor is able to set the
    specific flag in order to support a non-common feature. For
    example, if the governor supports the 'immutable' feature, don't
    allow user space to change the governor via sysfs.

  - Add governor sysfs attribute flag for each sysfs file. Prior to that
    the devfreq subsystem allowed all of the sysfs files to be accessed
    regardless of the governor type. But some sysfs fils are not
    supported by specific devfreq governors. In order to only allow the
    sysfs files supported by the governor to be accessed, clarify the
    access permissions of sysfs attributes according to the governor.
    When adding the devfreq governor, specify the available attribute
    information by using DEVFREQ_GOV_ATTR_* symbols. The user can read
    or write the sysfs attributes in accordance to the specified
    access permissions.

  - Clean-up the code to reduce duplication for the devfreq tracepoint
    and to remove redundant governor_name field from struct devfreq.

 2. Update exynos-bus.c devfreq driver

  - Add interconnect API support to the Samsung Exynos Bus Frequency
    driver, exynos-bus.c. Complementing the devfreq driver with
    interconnect functionality allows to ensure that the QoS
    requirements regarding devices accessing the system memory (e.g.
    video processing devices) will be met and allows to avoid issues
    like DMA underrun.

 3. Update tegra devfreq driver

  - Add interconnect support and OPP interface to tegra30-devfreq.c.
    Also, it is to guarantee the QoS requirement of some devices like
    the display controller.

  - Move tegra20-devfreq.c from drivers/devfreq/ into drivers/memory/tegra/
    in order to use the more proper monitoring feature such as EMC_STAT
    which is located in drivers/memory/tegra/.

  - Separate the configuration information for different SoCs in
    tegra30-devfrqe.c. The tegra30-devfreq.c had been supporting both
    tegra30-actmon and tegra124-actmon devices. In order to use the
    more correct configuration data, separate them.

  - Use dev_err_probe() to handle the deferred probe error in
    tegra30-devfreq.c.

 4. Pull the request of 'Tegra SoC and clock controller changes for
    v5.11' sent by Krzysztof Kozlowski <krzk@kernel.org> in order to
    avoid a build error."

* tag 'devfreq-next-for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux:
  PM / devfreq: tegra30: Separate configurations per-SoC generation
  PM / devfreq: tegra30: Support interconnect and OPPs from device-tree
  PM / devfreq: tegra20: Deprecate in a favor of emc-stat based driver
  PM / devfreq: exynos-bus: Add registration of interconnect child device
  dt-bindings: devfreq: Add documentation for the interconnect properties
  soc/tegra: fuse: Add stub for tegra_sku_info
  soc/tegra: fuse: Export tegra_read_ram_code()
  clk: tegra: Export Tegra20 EMC kernel symbols
  PM / devfreq: tegra30: Silence deferred probe error
  PM / devfreq: tegra20: Relax Kconfig dependency
  PM / devfreq: tegra20: Silence deferred probe error
  PM / devfreq: Remove redundant governor_name from struct devfreq
  PM / devfreq: Add governor attribute flag for specifc sysfs nodes
  PM / devfreq: Add governor feature flag
  PM / devfreq: Add tracepoint for frequency changes
  PM / devfreq: Unify frequency change to devfreq_update_target func
  trace: events: devfreq: Use fixed indentation size to improve readability
2020-12-11 19:40:00 +01:00
Dmitry Osipenko
5bf5861d6e clk: tegra: Fix duplicated SE clock entry
The periph_clks[] array contains duplicated entry for Security Engine
clock which was meant to be defined for T210, but it wasn't added
properly. This patch corrects the T210 SE entry and fixes the following
error message on T114/T124: "Tegra clk 127: register failed with -17".

Fixes: dc37fec483 ("clk: tegra: periph: Add new periph clks and muxes for Tegra210")
Tested-by Nicolas Chauvet <kwizart@gmail.com>
Reported-by Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201025224212.7790-1-digetx@gmail.com
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:51:59 -08:00
Vinod Koul
f7b36cc19e clk: qcom: rpmh: add support for SM8350 rpmh clocks
This adds the RPMH clocks present in SM8350 SoC

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20201208064702.3654324-3-vkoul@kernel.org
[sboyd@kernel.org: Move sdx55 to the right place]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:47:11 -08:00
Taniya Das
ce8c195e65 clk: qcom: lpasscc: Introduce pm autosuspend for SC7180
The LPASSCC driver's suspend/resume is invoked multiple number of times
and thus allow the device to autosuspend for 500ms.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1605890417-721-1-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:29:21 -08:00
Douglas Anderson
043577518f clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2
50 MHz is an incredibly common clock rate for SD cards to run at.
It's "high speed" mode in SD (not very fast these days, but it used to
be) or:
  #define HIGH_SPEED_MAX_DTR	50000000

If we don't support this then older "high speed" cards can only run at
25 MHz or at half their normal speed.  There doesn't seem to be any
reason to skip this clock rate, so add it.

Fixes: 17269568f7 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20201210102234.2.I26dcc0cee374f5571d9929c9985f463773167e68@changeid
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:27:30 -08:00
Douglas Anderson
6d37a8d192 clk: qcom: gcc-sc7180: Use floor ops for sdcc clks
I would repeat the same commit message that was in commit 5e4b7e82d4
("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems
silly to do so when you could just go read that commit.

NOTE: this is actually extra terrible because we're missing the 50 MHz
rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add
50 MHz clock rate for SDC2")).  That means then when you run an older
SD card it'll try to clock it at 100 MHz when it's only specced to run
at 50 MHz max.  As you can probably guess that doesn't work super
well.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Fixes: 17269568f7 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180")
Link: https://lore.kernel.org/r/20201210102234.1.I096779f219625148900fc984dd0084ed1ba87c7f@changeid
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:27:30 -08:00
Krzysztof Kozlowski
975d25cbb5 clk: scpi: mark scpi_clk_match as maybe unused
The scpi_clk_match (struct of_device_id) is referenced only with
CONFIG_OF builds thus mark it as __maybe_unused:

    drivers/clk/clk-scpi.c:132:34: warning:
        ‘scpi_clk_match’ defined but not used [-Wunused-const-variable=]

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20201103162435.13689-8-krzk@kernel.org
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:24:40 -08:00
Krzysztof Kozlowski
967069aa4d clk: pwm: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always
used and the of_match_ptr does not have any sense (this also allows ACPI
matching via PRP0001, even though it might be not relevant here).  This
fixes compile warning (!CONFIG_OF && !CONFIG_MODULES):

    drivers/clk/clk-pwm.c:139:34: warning:
        ‘clk_pwm_dt_ids’ defined but not used [-Wunused-const-variable=]

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20201103162435.13689-1-krzk@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:24:18 -08:00
Geert Uytterhoeven
fd0d8ed7c1 clk: renesas: sh73a0: Stop using __raw_*() I/O accessors
There is no reason to keep on using the __raw_{read,write}l() I/O
accessors in Renesas ARM driver code.  Switch to using the plain
{read,write}l() I/O accessors, to have a chance that this works on
big-endian.

Suggested-by: Arnd Bergmann <arnd@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20201119125053.4065746-1-geert+renesas@glider.be
2020-12-10 08:34:01 +01:00
Lad Prabhakar
40745482ee clk: renesas: r8a774c0: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
driver.

Add new clk type CLK_TYPE_GEN3_E3_RPCSRC to register rpcsrc as a fixed
clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC),
parent and the divider is set based on the register value CPG_RPCCKCR[4:3]
which has been set prior to booting the kernel.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201116101002.5986-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10 08:34:01 +01:00
Geert Uytterhoeven
14653942de clk: renesas: r8a779a0: Fix R and OSC clocks
The R-Car V3U clock driver defines the R and OSC clocks using R-Car Gen3
clock types.  However, The R-Car V3U clock driver does not use the R-Car
Gen3 clock driver core, hence registering the R and OSC clocks fails:

    renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock osc: -22
    renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock r: -22

Fix this by introducing clock definition macros specific to R-Car V3U.
Note that rcar_r8a779a0_cpg_clk_register() already handled the related
clock types.  Drop the now unneeded include of rcar-gen3-cpg.h.

Fixes: 17bcc8035d ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20201109152614.2465483-1-geert+renesas@glider.be
2020-12-10 08:34:01 +01:00
Krzysztof Kozlowski
b5fb3b8859 clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv
The struct cpg_mssr_priv missed proper formatting:

    drivers/clk/renesas/renesas-cpg-mssr.c:142: warning:
        cannot understand function prototype: 'struct cpg_mssr_priv '

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20201103162435.13689-7-krzk@kernel.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10 08:34:01 +01:00
Yejune Deng
4ef39a80da clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get()
devm_reset_control_array_get_shared() looks more readable

Signed-off-by: Yejune Deng <yejune.deng@gmail.com>
Link: https://lore.kernel.org/r/1604375093-6451-1-git-send-email-yejune.deng@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10 08:34:01 +01:00
Biju Das
fb9805c517 clk: renesas: r8a774b1: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2N (R8A774B1) CPG/MSSR
driver.

Inspired by commit 94e3935b57 ("clk: renesas: r8a77980: Add RPC clocks").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20201016121709.8447-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10 08:34:01 +01:00
Biju Das
13d2617bf2 clk: renesas: r8a774a1: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2M (R8A774A1) CPG/MSSR
driver.

Inspired by commit 94e3935b57 ("clk: renesas: r8a77980: Add RPC clocks").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20201016121709.8447-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10 08:34:01 +01:00
Jacopo Mondi
874d4eee54 clk: renesas: r8a779a0: Add VIN clocks
Add definitions of the VIN instance clocks for R-Car V3U.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20201016111158.17521-5-jacopo+renesas@jmondi.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10 08:34:00 +01:00
Jacopo Mondi
23378e70ca clk: renesas: r8a779a0: Add CSI4[0-3] clocks
Add definitions of the CSI-2 receiver clocks for R-Car V3U.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20201016111158.17521-2-jacopo+renesas@jmondi.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10 08:34:00 +01:00
Geert Uytterhoeven
0ca995f5c7 clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static
When compiling with clang:

    drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:21: warning: no previous prototype for function 'rcar_r8a779a0_cpg_clk_register' [-Wmissing-prototypes]
    struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
			   ^
    drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
    struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
    ^
    static

Similarly, with sparse:

    drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:12: warning: symbol 'rcar_r8a779a0_cpg_clk_register' was not declared. Should it be static?

There are no users of rcar_r8a779a0_cpg_clk_register() outside this
file, so it should be static.

Fixes: 17bcc8035d ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200924111808.15358-1-geert+renesas@glider.be
2020-12-10 08:32:58 +01:00
Arnd Bergmann
19cf6e6d40 Samsung SoC drivers changes for v5.11, part two
1. Mark PM functions of newly added clkout module as unused to silence
    !CONFIG_PM warnings.
 2. Initialize ChipID driver later - in arch initcall.
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Merge tag 'samsung-drivers-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers

Samsung SoC drivers changes for v5.11, part two

1. Mark PM functions of newly added clkout module as unused to silence
   !CONFIG_PM warnings.
2. Initialize ChipID driver later - in arch initcall.

* tag 'samsung-drivers-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: mark PM functions as __maybe_unused
  soc: samsung: exynos-chipid: initialize later - with arch_initcall
  soc: samsung: exynos-chipid: order list of SoCs by name

Link: https://lore.kernel.org/r/20201207074528.4475-1-krzk@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-09 20:51:26 +01:00
Arnd Bergmann
4cc6ae9896 Merge tag 'omap-for-v5.11/genpd-drivers-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/drivers
Driver changes for omaps for genpd for v5.11 merge window

This series of changes allows booting am335x with genpd and
device tree data without the legacy platform data. Also at
least am437x can be booted with gendp with power domain and
dts data. The SoC specific dts changes will be a separate
pull request.

We need the following driver changes merged before the dts
changes can be done:

- platform code needs a few improvments to probe l4_wkup first
  for clocks, and to bail out when there is no platform data

- ti-sysc driver needs a non-urgent fix for asserting rstctrl
  reset only after disabling the clocks, to probe modules with
  no known control registers, and added quirk handling for gpmc
  devices

- omap-prm driver needs a non-urgent fix for reset status bit,
  support added for pm_clk, and then we add the rest of am335x
  power domain data

- clock driver for am335x needs to keep l3_main clock enabled
  with genpd for suspend and resume to work

- wkup_m3 remoteproc driver needs support added for reset
  control if available instead of the legacy pdata callbacks

- pm33xx driver needs PM runtime support added for genpd

The am335x specific driver changes for the clock, wkup_m3,
pm33xx and remoteproc drivers are quite trivial and have not
caused merge conflicts in Linux next. I did not get acks for
these changes except from Santosh but had already pushed out
the branch already at that point. So I've added the related
driver maintainers to Cc.

* tag 'omap-for-v5.11/genpd-drivers-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  remoteproc/wkup_m3: Use reset control driver if available
  soc: ti: pm33xx: Enable basic PM runtime support for genpd
  soc: ti: omap-prm: am3: add genpd support for remaining PRM instances
  soc: ti: omap-prm: Add pm_clk for genpd
  clk: ti: am33xx: Keep am3 l3 main clock always on for genpd
  bus: ti-sysc: Implement GPMC debug quirk to drop platform data
  bus: ti-sysc: Support modules without control registers
  ARM: OMAP2+: Probe PRCM first to probe l4_wkup with simple-pm-bus
  ARM: OMAP2+: Check for inited flag
  bus: ti-sysc: Assert reset only after disabling clocks
  soc: ti: omap-prm: Do not check rstst bit on deassert if already deasserted
  bus: ti-sysc: Fix bogus resetdone warning on enable for cpsw
  bus: ti-sysc: Fix reset status check for modules with quirks
  ARM: OMAP2+: Fix missing select PM_GENERIC_DOMAINS_OF
  ARM: OMAP2+: Fix location for select PM_GENERIC_DOMAINS

Link: https://lore.kernel.org/r/pull-1606806458-694517@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-09 00:39:53 +01:00
Manivannan Sadhasivam
063930ed2d clk: qcom: Add GDSC support for SDX55 GCC
Add GDSC support to control the power supply of power domains in SDX55
GCC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20201126072844.35370-7-manivannan.sadhasivam@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 17:00:14 -08:00
Manivannan Sadhasivam
afacfbbe10 clk: qcom: Add support for SDX55 RPMh clocks
Add support for following clocks maintained by RPMh in SDX55 SoCs.

* BI TCXO
* RF_CLK1
* RF_CLK1_AO
* RF_CLK2
* RF_CLK2_AO
* QPIC (Qualcomm Technologies, Inc. Parallel Interface Controller)

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201126072844.35370-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 17:00:14 -08:00
Naveen Yadav
3fade566c0 clk: qcom: Add SDX55 GCC support
Add Global Clock Controller (GCC) support for SDX55 SoCs from Qualcomm.

Signed-off-by: Naveen Yadav <naveenky@codeaurora.org>
[mani: converted to parent_data, commented critical clocks, cleanups]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20201126072844.35370-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 16:59:58 -08:00
Michael Walle
fcf77be87e clk: fsl-flexspi: new driver
Add support for the FlexSPI clock on Freescale Layerscape SoCs. The
clock is a simple divider based one and is located inside the device
configuration space (DCFG).

This will allow switching the SCK frequencies for the FlexSPI interface
on the LS1028A and the LX2160A.

Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20201108185113.31377-8-michael@walle.cc
[sboyd@kernel.org: Drop modalias, add module table]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 16:56:41 -08:00
Michael Walle
26792699fe clk: divider: add devm_clk_hw_register_divider_table()
This will simplify drivers which would only unregister the clk in their
remove() op.

Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20201108185113.31377-6-michael@walle.cc
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 16:53:39 -08:00
Michael Walle
4cb15934ba clk: qoriq: provide constants for the type
To avoid future mistakes in the device tree for the clockgen module, add
constants for the clockgen subtype as well as a macro for the PLL
divider.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201108185113.31377-4-michael@walle.cc
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 16:53:30 -08:00
Michael Walle
fb8715157b clk: fsl-sai: use devm_clk_hw_register_composite_pdata()
Simplify the driver by using that helper and drop the remove() function.

Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20201105192746.19564-4-michael@walle.cc
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 14:06:16 -08:00
Michael Walle
0eba770790 clk: composite: add devm_clk_hw_register_composite_pdata()
This will simplify drivers which would only unregister the clk in their
remove() op.

Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20201105192746.19564-3-michael@walle.cc
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 14:06:16 -08:00
Michael Walle
e81bed419f clk: fsl-sai: fix memory leak
If the device is removed we don't unregister the composite clock. Fix
that.

Fixes: 9cd1020522 ("clk: fsl-sai: new driver")
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20201105192746.19564-2-michael@walle.cc
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 14:06:16 -08:00
Geert Uytterhoeven
b8bcece8a7 clk: qoriq: Add platform dependencies
The Freescale QorIQ clock controller is only present on Freescale E500MC
and Layerscape SoCs.  Add platform dependencies to the CLK_QORIQ config
symbol, to avoid asking the user about it when configuring a kernel
without E500MC or Layerscape support.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Li Yang <leoyang.li@nxp.com>
Link: https://lore.kernel.org/r/20201110154750.3285411-1-geert+renesas@glider.be
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 14:02:25 -08:00
Geert Uytterhoeven
ceabbf94c3 clk: renesas: r9a06g032: Drop __packed for portability
The R9A06G032 clock driver uses an array of packed structures to reduce
kernel size.  However, this array contains pointers, which are no longer
aligned naturally, and cannot be relocated on PPC64.  Hence when
compile-testing this driver on PPC64 with CONFIG_RELOCATABLE=y (e.g.
PowerPC allyesconfig), the following warnings are produced:

    WARNING: 136 bad relocations
    c000000000616be3 R_PPC64_UADDR64   .rodata+0x00000000000cf338
    c000000000616bfe R_PPC64_UADDR64   .rodata+0x00000000000cf370
    ...

Fix this by dropping the __packed attribute from the r9a06g032_clkdesc
definition, trading a small size increase for portability.

This increases the 156-entry clock table by 1 byte per entry, but due to
the compiler generating more efficient code for unpacked accesses, the
net size increase is only 76 bytes (gcc 9.3.0 on arm32).

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Fixes: 4c3d88526e ("clk: renesas: Renesas R9A06G032 clock driver")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201130085743.1656317-1-geert+renesas@glider.be
Tested-by: Stephen Rothwell <sfr@canb.auug.org.au> # PowerPC allyesconfig build
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 13:58:49 -08:00
Dong Aisheng
6247e31b75 clk: imx: scu: fix MXC_CLK_SCU module build break
This issue can be reproduced by having a kernel config with
CONFIG_IMX_MBOX=m and CONFIG_MXC_CLK_SCU=m.  It's caused by the Makefile
wanting to build clk-scu.o and clk-imx8qxp.o as different targets but
that doesn't work (e.g. MXC_CLK_SCU = y while CLK_IMX8QXP = n)

"obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o"

Having MXC_CLK_SCU=y/m while CLK_IMX8QXP=n will cause a linker problem
like below:

  LD [M]  drivers/clk/imx/clk-imx-scu.o
  arm-poky-linux-gnueabi-ld: no input files

Make MXC_CLK_SCU be un-selectable by users so it can only be selected by
the CLK_IMX8QXP option, ensuring the two symbols are built together.
Drop COMPILE_TEST too because this option isn't selectable anymore. We
can remove it from MXC_CLK_SCU because CLK_IMX8QXP selects MXC_CLK_SCU
which already has COMPILE_TEST.

Fixes: e0d0d4d86c ("clk: imx8qxp: Support building i.MX8QXP clock driver as module")
Acked-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/20201130084624.21113-1-aisheng.dong@nxp.com
[sboyd@kernel.org: Rework commit text]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07 13:54:00 -08:00
Arnd Bergmann
4c44274ee4 clk: samsung: mark PM functions as __maybe_unused
The use of SIMPLE_DEV_PM_OPS() means that the suspend/resume
functions are now unused when CONFIG_PM is disabled:

drivers/clk/samsung/clk-exynos-clkout.c:219:12: error: 'exynos_clkout_resume' defined but not used [-Werror=unused-function]
  219 | static int exynos_clkout_resume(struct device *dev)
      |            ^~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-exynos-clkout.c:210:12: error: 'exynos_clkout_suspend' defined but not used [-Werror=unused-function]
  210 | static int exynos_clkout_suspend(struct device *dev)
      |            ^~~~~~~~~~~~~~~~~~~~~

Mark them as __maybe_unused to shut up the otherwise harmless warning.

Fixes: 9484f2cb83 ("clk: samsung: exynos-clkout: convert to module driver")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lore.kernel.org/r/20201204091616.4128366-1-arnd@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-12-05 15:13:17 +01:00
Dong Aisheng
43d2479687 clk: imx: scu: remove the calling of device_is_bound
The device_is_bound() is invisible to drivers when built as modules.
It's also not aimed to be used by drivers according to Greg K.H.
Let's remove it from clk-scu driver and find another way to do proper
driver loading sequence.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Stephen Boyd <sboyd@kernel.org>
Fixes: 77d8f3068c ("clk: imx: scu: add two cells binding support")
Reported-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-30 21:53:03 +08:00
Johan Jonker
caa2fd752e clk: rockchip: fix i2s gate bits on rk3066 and rk3188
The Rockchip PX2/RK3066 uses these bits in CRU_CLKGATE7_CON:

hclk_i2s_8ch_gate_en  bit 4 (dtsi: i2s0)
hclk_i2s0_2ch_gate_en bit 2 (dtsi: i2s1)
hclk_i2s1_2ch_gate_en bit 3 (dtsi: i2s2)

The Rockchip PX3/RK3188 uses this bit in CRU_CLKGATE7_CON:

hclk_i2s_2ch_gate_en  bit 2 (dtsi: i2s0)

The bits got somehow mixed up in the clk-rk3188.c file.
The labels in the dtsi files are not suppose to change.
The sclk and hclk names should match for
"trace_event=clk_disable,clk_enable",
so remove GATE HCLK_I2S0 from the common clock tree and
fix the bits in the rk3066 and rk3188 clock tree.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20201118135822.9582-3-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-11-29 20:10:45 +01:00
Johan Jonker
5868491e12 clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks
Add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks,
so that the parent COMPOSITE_FRACMUX and COMPOSITE_NOMUX
also update.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20201118135822.9582-2-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-11-29 20:10:44 +01:00
Xu Wang
7f5b57a095 clk: rockchip: Remove redundant null check before clk_prepare_enable
Because clk_prepare_enable() already checked NULL clock parameter,
so the additional check is unnecessary, just remove it.

Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20201127090551.50254-1-vulab@iscas.ac.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-11-29 20:02:58 +01:00
Colin Ian King
02d8e879e4 clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic"
There is a spelling mistake in the Kconfig help text. Fix it.

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20201126232400.15011-1-colin.king@canonical.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-27 12:37:29 -08:00
Arnd Bergmann
8f2685c9c4 Memory controller drivers for v5.11 - Tegra SoC
There is a bigger work from Dmitry Osipenko around Tegra SoC memory
 controller drivers, mostly towards adding interconnect support and
 integration with devfreq.  This work touches all Tegra memory controller
 drivers and also few other SoC-related parts.  It's not yet finished but
 the intermediate stage seems ready to merge.
 
 Beside that Tegra 210 memory controller got few fixes and received new
 swgroups (work of Nicolin Chen).
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Merge tag 'memory-controller-drv-tegra-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

Memory controller drivers for v5.11 - Tegra SoC

There is a bigger work from Dmitry Osipenko around Tegra SoC memory
controller drivers, mostly towards adding interconnect support and
integration with devfreq.  This work touches all Tegra memory controller
drivers and also few other SoC-related parts.  It's not yet finished but
the intermediate stage seems ready to merge.

Beside that Tegra 210 memory controller got few fixes and received new
swgroups (work of Nicolin Chen).

* tag 'memory-controller-drv-tegra-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: (38 commits)
  memory: tegra30-emc: Remove unnecessary of_node_put in tegra_emc_probe
  memory: tegra: Complete tegra210_swgroups
  memory: tegra30-emc: Continue probing if timings are missing in device-tree
  memory: tegra30-emc: Make driver modular
  memory: tegra30: Add FIFO sizes to memory clients
  memory: tegra20-emc: Add devfreq support
  memory: tegra20-emc: Remove IRQ number from error message
  memory: tegra20-emc: Factor out clk initialization
  memory: tegra20-emc: Use dev_pm_opp_set_clkname()
  memory: tegra: Correct stub of devm_tegra_memory_controller_get()
  memory: tegra20: Support interconnect framework
  memory: tegra20-emc: Continue probing if timings are missing in device-tree
  memory: tegra20-emc: Make driver modular
  memory: tegra-mc: Add interconnect framework
  memory: tegra: Add missing latency allowness entry for Page Table Cache
  memory: tegra: Remove superfluous error messages around platform_get_irq()
  memory: tegra: Use devm_platform_ioremap_resource()
  memory: tegra: Add and use devm_tegra_memory_controller_get()
  dt-bindings: host1x: Document new interconnect properties
  dt-bindings: tegra30-actmon: Document OPP and interconnect properties
  ...

Link: https://lore.kernel.org/r/20201126191241.23302-1-krzk@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-11-26 22:05:15 +01:00
Sivaram Nair
a886c310d9 clk: tegra: bpmp: Clamp clock rates on requests
BPMP firmware ABI expects the rate inputs in int64_t. However,
tegra_bpmp_clk_round_rate() and tegra_bpmp_clk_set_rate() functions
directly assign 'unsigned long' inputs to a int64_t value causing
unexpected rounding errors.

Fix this by clipping the input rate to S64_MAX.

Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
[mperttunen: slight cleanup]
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-26 16:28:07 +01:00
Neil Armstrong
88b9ae6001 clk: meson: g12a: add MIPI DSI Host Pixel Clock
This adds the MIPI DSI Host Pixel Clock, unlike AXG, the pixel clock can be different
from the VPU ENCL output clock to feed the DSI Host controller with a different clock rate.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201126141600.2084586-3-narmstrong@baylibre.com
2020-11-26 15:25:20 +01:00
Thara Gopinath
dba6bc5197 clk: qcom: rpmh: Add CE clock on sdm845.
Qualcomm CE clock resource that is managed by BCM is required
by crypto driver to access the core clock.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
Link: https://lore.kernel.org/r/20201119155233.3974286-3-thara.gopinath@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-24 18:05:13 -08:00
Sylwester Nawrocki
44a9e78f92 clk: samsung: Prevent potential endless loop in the PLL ops
The PLL status polling loops in the set_rate callbacks of some PLLs
have no timeout detection and may become endless loops when something
goes wrong with the PLL.

For some PLLs there is already the ktime API based timeout detection,
but it will not work in all conditions when .set_rate gets called.
In particular, before the clocksource is initialized or when the
timekeeping is suspended.

This patch adds a common helper with the PLL status bit polling and
timeout detection. For conditions where the timekeeping API should not
be used a simple readl_relaxed/cpu_relax() busy loop is added with the
iterations limit derived from measurements of readl_relaxed() execution
time for various PLL types and Exynos SoCs variants.

Actual PLL lock time depends on the P divider value, the VCO frequency
and a constant PLL type specific LOCK_FACTOR and can be calculated as

 lock_time = Pdiv * LOCK_FACTOR / VCO_freq

For the ktime API use cases a common timeout value of 20 ms is applied
for all the PLLs with an assumption that maximum possible value of Pdiv
is 64, maximum possible LOCK_FACTOR value is 3000 and minimum VCO
frequency is 24 MHz.

Link: https://lore.kernel.org/r/20201120155731.26898-1-s.nawrocki@samsung.com
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-11-23 11:14:04 +01:00
Krzysztof Kozlowski
e44cdff051 clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
So far all Exynos, S3C64xx and S5Pv210 clock units were selected by
respective SOC/ARCH Kconfig option.  On a kernel built for selected
SoCs, this allowed to build only limited set of matching clock drivers.
However compile testing was not possible in such case as Makefile object
depends on SOC/ARCH option.

Add separate Kconfig options for each of them to be able to compile
test.

Link: https://lore.kernel.org/r/20201119164509.754851-1-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-11-23 10:25:45 +01:00
Kevin Hilman
20425f6319 clk: meson: enable building as modules
Make it possible to build all clk drivers as modules, but default
remains built-in.

No functional changes.

Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20201118191405.36798-1-khilman@baylibre.com
2020-11-23 09:08:23 +01:00
Kevin Hilman
bae69bfa3a clk: meson: Kconfig: fix dependency for G12A
When building only G12A, ensure that VID_PLL_DIV clock driver is
selected, otherwise results in this build error:

ERROR: modpost: "meson_vid_pll_div_ro_ops" [drivers/clk/meson/g12a.ko] undefined!

Fixes: 085a4ea93d ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201118190930.34352-1-khilman@baylibre.com
2020-11-23 09:08:22 +01:00
Neil Armstrong
e80d8510ff clk: meson: axg: add MIPI DSI Host clock
This adds the MIPI DSI Host clock, used to measure the signal timings
(ENC VSYNC or DW-MIPI-DSI eDPI timings).

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200915124553.8056-5-narmstrong@baylibre.com
2020-11-23 09:08:22 +01:00
Neil Armstrong
14ebb3154b clk: meson: axg: add Video Clocks
Add the clocks entries used in the video clock path, the clock path is
doubled to permit having different synchronized clocks for different parts
of the video pipeline.

The AXG only has a single ENCL CTS clock and even if VCLK exist along
VCLK2, only VCLK2 is used since it clocks the MIPI DSI IP directly.

All dividers are flagged with CLK_GET_RATE_NOCACHE, and all gates are
flagged with CLK_IGNORE_UNUSED since they are currently directly handled by
the Meson DRM Driver.  Once the DRM Driver is fully migrated to using the
Common Clock Framework to handle the video clock tree, the
CLK_GET_RATE_NOCACHE and CLK_IGNORE_UNUSED will be dropped.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200915124553.8056-4-narmstrong@baylibre.com
2020-11-23 09:08:22 +01:00
Nicolin Chen
6160aca443 clk: tegra: Do not return 0 on failure
Return values from read_dt_param() will be either TRUE (1) or
FALSE (0), while dfll_fetch_pwm_params() returns 0 on success
or an ERR code on failure.

So this patch fixes the bug of returning 0 on failure.

Fixes: 36541f0499 ("clk: tegra: dfll: support PWM regulator control")
Cc: <stable@vger.kernel.org>
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-20 17:19:46 +01:00
Tony Lindgren
57f5720136 clk: ti: dra7: Drop idlest polling from IVA clkctrl clocks
Similar to what we've done for IPU and DSP let's ignore the status bit
for the IVA clkctrl register.

The clkctrl status won't change unless the related rstctrl is deasserted,
and the rstctrl status won't change unless the clkctrl is enabled.

Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 15:09:00 +02:00
Tony Lindgren
3614fb09f9 clk: ti: omap4: Drop idlest polling from IVA clkctrl clocks
Similar to what we've done for IPU and DSP let's ignore the status bit
for the IVA clkctrl register.

The clkctrl status won't change unless the related rstctrl is deasserted,
and the rstctrl status won't change unless the clkctrl is enabled.

Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19 14:21:27 +02:00
Tony Lindgren
d36edb048f clk: ti: am437x: Keep am4 l3 main clock always on for genpd
In order for suspend and resume to work with genpd on am4, we must keep
l3 main clock always on. Otherwise prm_omap driver will shut down the l3
main clock on suspend when simple-pm-bus and GENPD_FLAG_PM_CLK are used.
Note that we already keep the l3 main clock always on with the legacy
platform code.

Later on we may want to start managing the l3 main clock with a dedicated
interconnect driver instead of using simple-pm-bus and GENPD_FLAG_PM_CLK.

Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-16 13:00:20 +02:00
Tony Lindgren
9fac08999c clk: ti: am33xx: Keep am3 l3 main clock always on for genpd
In order for suspend and resume to work with genpd on am3, we must keep
l3 main clock always on. Otherwise prm_omap driver will shut down the l3
main clock on suspend when simple-pm-bus and GENPD_FLAG_PM_CLK are used.
Note that we already keep the l3 main clock always on with the legacy
platform code.

Later on we may want to start managing the l3 main clock with a dedicated
interconnect driver instead of using simple-pm-bus and GENPD_FLAG_PM_CLK.

Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-16 12:57:29 +02:00
Dmitry Baryshkov
3105c7c91f clk: qcom: dispcc-sm8250: handle MMCX power domain
On SM8250 MMCX power domain is required to access MMDS_GDSC registers.
This power domain is expressed as mmcx-supply regulator property. Use
this regulator as MDSS_GDSC supply.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20201023131925.334864-6-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-14 13:11:44 -08:00
Jerome Brunet
e6fb7aee48 clk: meson: g12: use devm variant to register notifiers
Until now, nothing was done to unregister the dvfs clock notifiers of the
Amlogic g12 SoC family. This is not great but this driver was not really
expected to be unloaded. With the ongoing effort to build everything as
module for this platform, this needs to be cleanly handled.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201021163847.595189-3-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-14 12:58:31 -08:00
Jerome Brunet
6d30d50d03 clk: add devm variant of clk_notifier_register
Add a memory managed variant of clk_notifier_register() to make life easier
on clock consumers using notifiers

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201021163847.595189-2-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-14 12:58:30 -08:00
Jerome Brunet
8e677e7f0a clk: meson: g12: drop use of __clk_lookup()
g12 clock controller used __clk_lookup() to get struct clk from a
struct clk_hw. This type of hack is no longer required as CCF now provides
the necessary functions to get this.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201021162147.563655-4-jbrunet@baylibre.com
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-14 12:56:58 -08:00
Jerome Brunet
30d6f8c15d clk: add api to get clk consumer from clk_hw
clk_register() is deprecated. Using 'clk' member of struct clk_hw is
discouraged. With this constraint, it is difficult for driver to
register clocks using the clk_hw API and then use the clock with
the consumer API

This adds a simple helper, clk_hw_get_clk(), to get a struct clk from
a struct clk_hw. Like other clk_get() variant, each call to this helper
must be balanced with a call to clk_put(). To make life easier on the
consumers, a memory managed version is provided as well.

Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201021162147.563655-3-jbrunet@baylibre.com
Tested-by: Kevin Hilman <khilman@baylibre.com>
[sboyd@kernel.org: Fix kernel-doc]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-14 12:56:57 -08:00
Jerome Brunet
e5a4b9b99e clk: avoid devm_clk_release name clash
In clk-devres.c, devm_clk_release() is used to call clk_put() memory
managed clock. In clk.c the same name, in a different scope is used to call
clk_unregister().

As it stands, it is not really a problem but it does not readability,
especially if we need to call clk_put() on managed clock in clk.c

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201021162147.563655-2-jbrunet@baylibre.com
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-14 12:43:08 -08:00
Lukas Bulwahn
6a17849703 clk: remove unneeded dead-store initialization
make clang-analyzer on x86_64 defconfig caught my attention with:

  drivers/clk/clk.c:423:19:
  warning: Value stored to 'parent' during its initialization is never read
  [clang-analyzer-deadcode.DeadStores]
          struct clk_core *parent = ERR_PTR(-ENOENT);
                           ^

Commit fc0c209c14 ("clk: Allow parents to be specified without string
names") introduced clk_core_fill_parent_index() with this unneeded
dead-store initialization.

So, simply remove this unneeded dead-store initialization to make
clang-analyzer happy.

As compilers will detect this unneeded assignment and optimize this anyway,
the resulting object code is identical before and after this change.

No functional change. No change to object code.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20201106094820.30167-1-lukas.bulwahn@gmail.com
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-14 12:32:29 -08:00
Stephen Boyd
8d4025943e clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones
Let's call pm_runtime_get() here instead of calling the PM clk APIs
directly. This avoids a compilation problem on CONFIG_PM=n where the
pm_clk_runtime_{resume,suspend}() functions don't exist and covers the
intent, i.e. enable the clks for this device so we can program PLL
settings.

Reported-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Nathan Chancellor <natechancellor@gmail.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Taniya Das <tdas@codeaurora.org>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
Fixes: 15d09e830b ("clk: qcom: camcc: Add camera clock controller driver for SC7180")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20201114174408.579047-1-sboyd@kernel.org
2020-11-14 11:33:33 -08:00
Dan Carpenter
e4accab4e0 clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init()
Clean up the first driver if the second driver can't be registered.

Fixes: 4ee9fe3e29 ("clk: qcom: lpass-sc7180: Disentangle the two clock devices")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/20201113101419.GC168908@mwanda
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-14 09:04:09 -08:00
Krzysztof Kozlowski
124f035310 clk: samsung: allow building the clkout driver as module
The Exynos clock output driver can be built as module (it does not have
to be part of core init process) for better customization.  Adding a
KConfig entry allows also compile testing for build coverage.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lore.kernel.org/r/20201110193749.261367-1-krzk@kernel.org
2020-11-12 17:18:40 +01:00
Zou Wei
550b562a15 clk: imx: scu: Make pd_np with static keyword
Fix the following sparse warning:

./clk-scu.c:23:20: warning: symbol 'pd_np' was not declared. Should it be static?

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zou Wei <zou_wei@huawei.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-10 10:17:23 +08:00
Krzysztof Kozlowski
00cb754ac6 clk: imx8mq: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always
used and the of_match_ptr does not have any sense (this also allows ACPI
matching via PRP0001, even though it might be not relevant here).  This
fixes compile warning (!CONFIG_OF && !CONFIG_MODULES):

    drivers/clk/imx/clk-imx8mq.c:626:34: warning:
        ‘imx8mq_clk_of_match’ defined but not used [-Wunused-const-variable=]

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-10 09:53:39 +08:00
Krzysztof Kozlowski
f32e42f092 clk: imx8mp: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always
used and the of_match_ptr does not have any sense (this also allows ACPI
matching via PRP0001, even though it might be not relevant here).  This
fixes compile warning (!CONFIG_OF && !CONFIG_MODULES):

    drivers/clk/imx/clk-imx8mp.c:751:34: warning:
        ‘imx8mp_clk_of_match’ defined but not used [-Wunused-const-variable=]

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-10 09:53:25 +08:00
Krzysztof Kozlowski
8f8a323092 clk: imx8mn: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always
used and the of_match_ptr does not have any sense (this also allows ACPI
matching via PRP0001, even though it might be not relevant here).  This
fixes compile warning (!CONFIG_OF && !CONFIG_MODULES):

    drivers/clk/imx/clk-imx8mn.c:592:34: warning:
        ‘imx8mn_clk_of_match’ defined but not used [-Wunused-const-variable=]

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-10 09:53:11 +08:00
Krzysztof Kozlowski
bdb0894023 clk: imx8mm: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always
used and the of_match_ptr does not have any sense (this also allows ACPI
matching via PRP0001, even though it might be not relevant here).  This
fixes compile warning (!CONFIG_OF && !CONFIG_MODULES):

    drivers/clk/imx/clk-imx8mm.c:641:34: warning:
        ‘imx8mm_clk_of_match’ defined but not used [-Wunused-const-variable=]

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-10 09:45:44 +08:00
Zou Wei
f2bd43f1c9 clk: imx: gate2: Remove unused variable ret
This patch fixes below warning reported by coccicheck:

./clk-gate2.c:57:5-8: Unneeded variable: "ret". Return "0" on line 68

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zou Wei <zou_wei@huawei.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-10 09:08:03 +08:00
Dmitry Osipenko
4cfdad35ae clk: tegra: Export Tegra20 EMC kernel symbols
We're going to modularize Tegra EMC drivers and some of the EMC-clock
driver symbols need to be exported.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20201104164923.21238-2-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-06 19:24:04 +01:00
Srinivas Kandagatla
794aa56a78 clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocks
LPASS Always ON Clock controller has one GFM mux to control VA
and TX clocks to codec macro on LPASS.
This patch adds support to this mux.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20201026120221.18984-5-srinivas.kandagatla@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-04 18:34:54 -08:00
Srinivas Kandagatla
a2d8f50780 clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks
GFM Muxes in AUDIO_CC control clocks to LPASS WSA and RX Codec Macros.
This patch adds support to these muxes.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20201026120221.18984-4-srinivas.kandagatla@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-04 18:34:54 -08:00
Douglas Anderson
4ee9fe3e29 clk: qcom: lpass-sc7180: Disentangle the two clock devices
The sc7180 lpass clock driver manages two different devices.  These
two devices were tangled together, using one probe and a lookup to
figure out the real probe.  I think it's cleaner to really separate
the probe for these two devices since they're really different things,
just both managed by the same driver.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20201019154857.v5.2.I75c409497d4dea9daefa53ec5f93824081c4ecbe@changeid
Reviewed-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-04 18:33:06 -08:00
Douglas Anderson
7635622b77 clk: qcom: lpasscc-sc7810: Use devm in probe
Let's convert the lpass clock control driver to use devm.  This is a
few more lines of code, but it will be useful in a later patch which
disentangles the two devices handled by this driver.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20201019154857.v5.1.I4567b5e7e17bbb15ef063d447cb83fd43746cb18@changeid
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-04 18:33:06 -08:00
Taniya Das
15d09e830b clk: qcom: camcc: Add camera clock controller driver for SC7180
Add support for the camera clock controller found on SC7180 based devices.
This would allow camera drivers to probe and control their clocks.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1602873815-1677-5-git-send-email-tdas@codeaurora.org
[sboyd@kernel.org: Mark hw array static, add UL to big vco numbers]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-04 18:31:57 -08:00
Taniya Das
a2b57943a5 clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLs
Add programming sequence support for managing the Agera PLLs.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1602873815-1677-3-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-04 18:26:56 -08:00
Taniya Das
61a3129200 clk: qcom: clk-alpha-pll: Add support for helper functions
Introduce clk_alpha_pll_write_config and alpha_pll_check_rate_margin
helper functions to be across PLL configure functions and PLL set rate
functions.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1602873815-1677-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-04 18:26:56 -08:00
Peng Fan
c277ca155d clk: imx8m: fix bus critical clk registration
noc/axi/ahb are bus clk, not peripheral clk.
Since peripheral clk has a limitation that for peripheral clock slice,
IP clock slices must be stopped to change the clock source.

However if the bus clk is marked as critical clk peripheral, the
assigned clock parent operation will fail.

So we added CLK_SET_PARENT_GATE flag to avoid glitch.

And add imx8m_clk_hw_composite_bus_critical for bus critical clock usage

Fixes: 936c383673 ("clk: imx: fix composite peripheral flags")
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Reported-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/1604229834-25594-1-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-04 17:13:12 -08:00
Abel Vesa
65188f0745 clk: imx: gate2: Add locking in is_enabled op
Protect against enabling/disabling the gate while we're
checking if it is enabled.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-03 07:55:41 +08:00
Abel Vesa
bcd418a632 clk: imx: gate2: Add cgr_mask for more flexible number of control bits
On some i.MX8 platforms, there are HW gates that share the same bit.
So in order to make this clock type more usable, use a mask to specify
how many bits belong to those HW gates.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-03 07:55:38 +08:00
Abel Vesa
03681d06a5 clk: imx: gate2: Check if clock is enabled against cgr_val
Seems the logic here was wrong all along. For example, if
the cgr_val is 2 (0b10), the clk_gate2_reg_is_enabled would
report the clock as disabled. So check against cgr_val instead.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-03 07:55:35 +08:00
Abel Vesa
040adb5fe9 clk: imx: gate2: Keep the register writing in on place
Move all the register writing to the newly added clk_gate2_do_shared_clks
and call that everywhere need needed. Cleans up the code a little bit.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-03 07:55:33 +08:00
Abel Vesa
12309428c2 clk: imx: gate2: Remove the IMX_CLK_GATE2_SINGLE_BIT special case
This was a hack which would allow multiple HW gates to be controlled
by a single bit. The only user of this is the imx_dev_clk_hw_gate_shared
which is not used anywhere as of now. Basically, complicates the logic
of the driver for no reason.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-03 07:55:11 +08:00
Dong Aisheng
220175cd39 clk: imx: scu: fix build break when compiled as modules
After commit e0d0d4d86c ("clk: imx8qxp: Support building i.MX8QXP clock
driver as module"), clk-scu.c and clk-imx8qxp.c are complied in one module,
thus there can be only one module_init() in those two files.
Commit 77d8f3068c ("clk: imx: scu: add two cells binding support")
introduced another module_init() in clk_scu.c which caused the errors
below.

To fix the issue, we can remove the unnecessary builtin_platform_driver
from clk_scu.c and directly register the driver in imx_clk_scu_init().

  CC [M]  drivers/clk/imx/clk-scu.o
In file included from ../include/linux/of_device.h:6,
                 from ../include/linux/of_platform.h:12,
                 from ../drivers/clk/imx/clk-scu.c:11:
../drivers/clk/imx/clk-scu.c: In function ‘imx_clk_scu_init’:
../drivers/clk/imx/clk-scu.c:176:35: error: ‘imx_clk_scu_driver’ undeclared (first use in this function); did you mean ‘imx_clk_scu_init’?
  176 |  return platform_driver_register(&imx_clk_scu_driver);
      |                                   ^~~~~~~~~~~~~~~~~~
../include/linux/platform_device.h:218:29: note: in definition of macro ‘platform_driver_register’
  218 |  __platform_driver_register(drv, THIS_MODULE)
      |                             ^~~
../drivers/clk/imx/clk-scu.c:176:35: note: each undeclared identifier is reported only once for each function it appears in
  176 |  return platform_driver_register(&imx_clk_scu_driver);
      |                                   ^~~~~~~~~~~~~~~~~~
../include/linux/platform_device.h:218:29: note: in definition of macro ‘platform_driver_register’
  218 |  __platform_driver_register(drv, THIS_MODULE)
      |                             ^~~
../drivers/clk/imx/clk-scu.c:177:1: error: control reaches end of non-void function [-Werror=return-type]
  177 | }
      | ^
At top level:
../drivers/clk/imx/clk-scu.c:470:31: warning: ‘imx_clk_scu_driver’ defined but not used [-Wunused-variable]
  470 | static struct platform_driver imx_clk_scu_driver = {

Reported-by: kernel test robot <lkp@intel.com>
Fixes: 77d8f3068c ("clk: imx: scu: add two cells binding support")
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-03 07:35:47 +08:00
Colin Ian King
f2644bd741 clk: imx: remove redundant assignment to pointer np
Pointer np is being initialized with a value that is never read
and it is being updated with a value later on. The initialization
is redundant and can be removed.

Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-01 17:26:43 +08:00
Tom Rix
8404c66140 clk: imx: remove unneeded semicolon
A semicolon is not needed after a switch statement.

Signed-off-by: Tom Rix <trix@redhat.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-01 17:19:18 +08:00
Arnd Bergmann
8d8c313124 clk: define to_clk_regmap() as inline function
Nesting container_of() causes warnings with W=2, which is
annoying if it happens in headers and fills the build log
like:

In file included from drivers/clk/qcom/clk-alpha-pll.c:6:
drivers/clk/qcom/clk-alpha-pll.c: In function 'clk_alpha_pll_hwfsm_enable':
include/linux/kernel.h:852:8: warning: declaration of '__mptr' shadows a previous local [-Wshadow]
  852 |  void *__mptr = (void *)(ptr);     \
      |        ^~~~~~
drivers/clk/qcom/clk-alpha-pll.c:155:31: note: in expansion of macro 'container_of'
  155 | #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
      |                               ^~~~~~~~~~~~
drivers/clk/qcom/clk-regmap.h:27:28: note: in expansion of macro 'container_of'
   27 | #define to_clk_regmap(_hw) container_of(_hw, struct clk_regmap, hw)
      |                            ^~~~~~~~~~~~
drivers/clk/qcom/clk-alpha-pll.c:155:44: note: in expansion of macro 'to_clk_regmap'
  155 | #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
      |                                            ^~~~~~~~~~~~~
drivers/clk/qcom/clk-alpha-pll.c:254:30: note: in expansion of macro 'to_clk_alpha_pll'
  254 |  struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
      |                              ^~~~~~~~~~~~~~~~
include/linux/kernel.h:852:8: note: shadowed declaration is here
  852 |  void *__mptr = (void *)(ptr);     \
      |        ^~~~~~

Redefine two copies of the to_clk_regmap() macro as inline functions
to avoid a lot of these.

Fixes: ea11dda9e0 ("clk: meson: add regmap clocks")
Fixes: 085d7a4554 ("clk: qcom: Add a regmap type clock struct")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20201026161411.3708639-1-arnd@kernel.org
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-28 16:34:44 -07:00
Krzysztof Kozlowski
9484f2cb83 clk: samsung: exynos-clkout: convert to module driver
The Exynos clkout driver depends on board input clock (typically XXTI or
XUSBXTI), however on Exynos4 boards these clocks were modeled as part of
SoC clocks (Exynos4 clocks driver).  Obviously this is not proper, but
correcting it would break DT backward compatibility.

Both drivers - clkout and Exynos4 clocks - register the clock providers
with CLK_OF_DECLARE/OF_DECLARE_1 so their order is fragile (in the
Makefile clkout is behind Exynos4 clock).  It will work only if the
Exynos4 clock driver comes up before clkout.

A change in DTS adding input clock reference to Exynos4 clocks input
PLL, see reverted commit eaf2d2f689 ("ARM: dts: exynos: add input
clock to CMU in Exynos4412 Odroid"), caused probe reorder: the clkout
appeared before Exynos4 clock provider.  Since clkout depends on Exynos4
clocks and does not support deferred probe, this did not work and caused
later failure of usb3503 USB hub probe which needs clkout:

    [    5.007442] usb3503 0-0008: unable to request refclk (-517)

The Exynos clkout driver is not a critical/core clock so there is
actually no problem in instantiating it later, as a regular module.
This removes specific probe ordering and adds support for probe
deferral.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lore.kernel.org/r/20201001165646.32279-3-krzk@kernel.org
2020-10-28 23:04:46 +01:00
Robin Murphy
6e0781e092 clk: rockchip: Add appropriate arch dependencies
There's no point offering support for 32-bit platforms to users
configuring a 64-bit kernel - and vice-versa - unless they are
explicitly interested in compile-testing.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/72abb0f794b8ed77e274e8ee21c22e0bd3223dfd.1603710913.git.robin.murphy@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-10-26 12:24:56 +01:00
Wolfram Sang
7f2c2f38c1 clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI
There is no case (and none foreseen) where we would need to disable the
SDn clock. So, for simplicity, remove its handling.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20200922120036.10298-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-10-26 09:57:13 +01:00
Dong Aisheng
ea0c5cbaf8 clk: imx: lpcg: add suspend/resume support
LPCG clock state may be lost when it's power domain is completely
off during system suspend/resume and we need save and restore the
state properly.

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-10-26 10:54:08 +08:00
Dong Aisheng
18cdbad40c clk: imx: clk-imx8qxp-lpcg: add runtime pm support
add runtime pm support

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-10-26 10:54:05 +08:00
Dong Aisheng
a4bfc85ccf clk: imx: lpcg: allow lpcg clk to take device pointer
Used to support runtime pm.

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-10-26 10:54:02 +08:00
Dong Aisheng
d5f1e6a2bb clk: imx: imx8qxp-lpcg: add parsing clocks from device tree
One LPCG controller supports up to 8 clock outputs while each of them
is fixed to 4 bits.  It supports only gating function with fixed bits.
So we can use the clk-indices to fetch the corresponding clock idx from
device tree. With this way, we can write a generic LPCG clock drivers.

This patch add that support to parse clocks from device tree.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-10-26 10:54:00 +08:00
Dong Aisheng
d0409631f4 clk: imx: scu: add suspend/resume support
Clock state will be lost when its power domain is completely off
during system suspend/resume. So we save and restore the state
accordingly in suspend/resume callback.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-10-26 10:53:57 +08:00
Dong Aisheng
78edeb0803 clk: imx: scu: add runtime pm support
Add runtime pm support

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-10-26 10:53:54 +08:00
Dong Aisheng
2f1a2c1d00 clk: imx: scu: allow scu clk to take device pointer
Used to support runtime pm.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-10-26 10:53:51 +08:00
Dong Aisheng
0d5f1f4731 clk: imx: scu: bypass cpu power domains
Bypass cpu power domains which are owned by ATF.

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-10-26 10:53:38 +08:00
Dong Aisheng
77d8f3068c clk: imx: scu: add two cells binding support
This patch implements the new two cells binding for SCU clocks.
The usage is as follows:
clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>

Due to each SCU clock is associated with a power domain, without power
on the domain, the SCU clock can't work. So we create platform devices
for each domain clock respectively and manually attach the required domain
before register the clock devices, then we can register clocks in the
clock platform driver accordingly.

Note because we do not have power domain info in device tree and the SCU
resource ID is the same for power domain and clock, so we use resource ID
to find power domains.

Later, we will also use this clock platform driver to support suspend/resume
and runtime pm.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-10-26 10:53:13 +08:00
Joe Perches
33def8498f treewide: Convert macro and uses of __section(foo) to __section("foo")
Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.

Remove the quote operator # from compiler_attributes.h __section macro.

Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.

Conversion done using the script at:

    https://lore.kernel.org/lkml/75393e5ddc272dc7403de74d645e6c6e0f4e70eb.camel@perches.com/2-convert_section.pl

Signed-off-by: Joe Perches <joe@perches.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@gooogle.com>
Reviewed-by: Miguel Ojeda <ojeda@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2020-10-25 14:51:49 -07:00
Linus Torvalds
e731f3146f ARM: SoC platform updates
SoC changes, a substantial part of this is cleanup of some of the older
 platforms that used to have a bunch of board files. In particular:
 
  - Removal of non-DT i.MX platforms that haven't seen activity in years,
    it's time to remove them.
  - A bunch of cleanup and removal of platform data for TI/OMAP platforms,
    moving over to genpd for power/reset control (yay!)
  - Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them
    closer to multiplatform support (not quite there yet, but getting
    close).
 
 THere are a few other changes too, smaller fixlets, etc. For new
 platform support, the primary ones re:
 
  - New SoC: Hisilicon SD5203, ARM926EJ-S platform.
  - Cpufreq support for i.MX7ULP
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC platform updates from Olof Johansson:
 "SoC changes, a substantial part of this is cleanup of some of the
  older platforms that used to have a bunch of board files.

  In particular:

   - Remove non-DT i.MX platforms that haven't seen activity in years,
     it's time to remove them.

   - A bunch of cleanup and removal of platform data for TI/OMAP
     platforms, moving over to genpd for power/reset control (yay!)

   - Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them
     closer to multiplatform support (not quite there yet, but getting
     close).

  There are a few other changes too, smaller fixlets, etc. For new
  platform support, the primary ones are:

   - New SoC: Hisilicon SD5203, ARM926EJ-S platform.

   - Cpufreq support for i.MX7ULP"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (121 commits)
  ARM: mstar: Select MStar intc
  ARM: stm32: Replace HTTP links with HTTPS ones
  ARM: debug: add UART early console support for SD5203
  ARM: hisi: add support for SD5203 SoC
  ARM: omap3: enable off mode automatically
  clk: imx: imx35: Remove mx35_clocks_init()
  clk: imx: imx31: Remove mx31_clocks_init()
  clk: imx: imx27: Remove mx27_clocks_init()
  ARM: imx: Remove unused definitions
  ARM: imx35: Retrieve the IIM base address from devicetree
  ARM: imx3: Retrieve the AVIC base address from devicetree
  ARM: imx3: Retrieve the CCM base address from devicetree
  ARM: imx31: Retrieve the IIM base address from devicetree
  ARM: imx27: Retrieve the CCM base address from devicetree
  ARM: imx27: Retrieve the SYSCTRL base address from devicetree
  ARM: s3c64xx: bring back notes from removed debug-macro.S
  ARM: s3c24xx: fix Wunused-variable warning on !MMU
  ARM: samsung: fix PM debug build with DEBUG_LL but !MMU
  MAINTAINERS: mark linux-samsung-soc list non-moderated
  ARM: imx: Remove remnant board file support pieces
  ...
2020-10-24 10:33:08 -07:00
Linus Torvalds
3fec0eaaf0 This pull request contains zero diff to the core framework. It is a collection
of various clk driver updates. The biggest driver updates in terms of lines of
 code is the Allwinner driver, closely followed by the Qualcomm and Mediatek
 drivers. All of those hit high because we add so many lines of clk data. Coming
 in fourth place is i.MX which also adds a bunch of clk data. This accounts for
 the new driver additions this time around.
 
 Otherwise the patches are lots of little cleanups and fixes for various clk
 drivers that have baked in linux-next for a while. I suppose one highlight or
 theme is that more clk drivers are being updated to work as modules, which is
 interesting to see such critical SoC infrastructure work as a loadable module.
 
 New Drivers:
  - Support qcom SM8150/SM8250 video and display clks
  - Support Mediatek MT8167 clks
  - Add clock for CRC block found on vf610 SoCs
  - Add support for the Renesas R-Car V3U (R8A779A0) SoC
  - Add support for the VSP for Resizing clock on Renesas RZ/G1H
  - Support Allwinner A100 SoC clks
 
 Removed Drivers:
  - Remove i.MX21 clock driver, as i.MX21 platform support is being dropped
 
 Updates:
  - Change how qcom's display port clks work
  - Small non-critical fixes for TI clk driver
  - Remove various unused variables in clk drivers
  - Allow Rockchip clk driver to be a module
  - Remove most __clk_lookup() calls in Samsung drivers (yay!)
  - Support building i.MX ARMv8 platforms clock driver as module
  - Some kerneldoc fixes here and there
  - A couple of minor i.MX clk data corrections
  - Update audio clock inverter and fdiv2 flag on Amlogic g12
  - Make amlogic clk drivers configurable in Kconfig
  - Fix Renesas VSP clock names to match corrected hardware documentation
  - Sigma-delta modulation on Allwinner R40
  - Various fixes for at91 clk driver
  - Use semicolons instead of commas in some places
  - Mark some variables const so they can move to RO memory
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This contains no changes to the core framework. It is a collection of
  various clk driver updates.

  The biggest driver updates in terms of lines of code is the Allwinner
  driver, closely followed by the Qualcomm and Mediatek drivers. All of
  those hit high because we add so many lines of clk data. Coming in
  fourth place is i.MX which also adds a bunch of clk data. This
  accounts for the new driver additions this time around.

  Otherwise the patches are lots of little cleanups and fixes for
  various clk drivers that have baked in linux-next for a while. I
  suppose one highlight or theme is that more clk drivers are being
  updated to work as modules, which is interesting to see such critical
  SoC infrastructure work as a loadable module.

  New Drivers:
   - Support qcom SM8150/SM8250 video and display clks
   - Support Mediatek MT8167 clks
   - Add clock for CRC block found on vf610 SoCs
   - Add support for the Renesas R-Car V3U (R8A779A0) SoC
   - Add support for the VSP for Resizing clock on Renesas RZ/G1H
   - Support Allwinner A100 SoC clks

  Removed Drivers:
   - Remove i.MX21 clock driver, as i.MX21 platform support is being
     dropped

  Updates:
   - Change how qcom's display port clks work
   - Small non-critical fixes for TI clk driver
   - Remove various unused variables in clk drivers
   - Allow Rockchip clk driver to be a module
   - Remove most __clk_lookup() calls in Samsung drivers (yay!)
   - Support building i.MX ARMv8 platforms clock driver as module
   - Some kerneldoc fixes here and there
   - A couple of minor i.MX clk data corrections
   - Update audio clock inverter and fdiv2 flag on Amlogic g12
   - Make amlogic clk drivers configurable in Kconfig
   - Fix Renesas VSP clock names to match corrected hardware
     documentation
   - Sigma-delta modulation on Allwinner R40
   - Various fixes for at91 clk driver
   - Use semicolons instead of commas in some places
   - Mark some variables const so they can move to RO memory"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (102 commits)
  clk: imx8mq: Fix usdhc parents order
  clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
  clk: Restrict CLK_HSDK to ARC_SOC_HSDK
  clk: at91: sam9x60: support only two programmable clocks
  clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
  clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
  clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
  clk: ingenic: Use readl_poll_timeout instead of custom loop
  clk: ingenic: Use to_clk_info() macro for all clocks
  clk: bcm2835: add missing release if devm_clk_hw_register fails
  clk: at91: clk-sam9x60-pll: remove unused variable
  clk: at91: clk-main: update key before writing AT91_CKGR_MOR
  clk: at91: remove the checking of parent_name
  clk: clk-prima2: fix return value check in prima2_clk_init()
  clk: mmp2: Fix the display clock divider base
  clk: pxa: Constify static struct clk_ops
  clk: baikal-t1: Mark Ethernet PLL as critical
  clk: qoriq: modify MAX_PLL_DIV to 32
  clk: axi-clkgen: Set power bits for fractional mode
  clk: axi-clkgen: Add support for fractional dividers
  ...
2020-10-22 12:53:28 -07:00
Stephen Boyd
5f56888fad Merge branches 'clk-ingenic', 'clk-at91', 'clk-kconfig', 'clk-imx', 'clk-qcom', 'clk-prima2' and 'clk-bcm' into clk-next
- Support qcom SM8150/SM8250 video and display clks
 - Change how qcom's display port clks work

* clk-ingenic:
  clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
  clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
  clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
  clk: ingenic: Use readl_poll_timeout instead of custom loop
  clk: ingenic: Use to_clk_info() macro for all clocks

* clk-at91:
  clk: at91: sam9x60: support only two programmable clocks
  clk: at91: clk-sam9x60-pll: remove unused variable
  clk: at91: clk-main: update key before writing AT91_CKGR_MOR
  clk: at91: remove the checking of parent_name

* clk-kconfig:
  clk: Restrict CLK_HSDK to ARC_SOC_HSDK

* clk-imx:
  clk: imx8mq: Fix usdhc parents order
  clk: imx: imx21: Remove clock driver
  clk: imx: gate2: Fix a few typos
  clk: imx: Fix and update kerneldoc
  clk: imx: fix i.MX7D peripheral clk mux flags
  clk: imx: fix composite peripheral flags
  clk: imx: Correct the memrepair clock on imx8mp
  clk: imx: Correct the root clk of media ldb on imx8mp
  clk: imx: vf610: Add CRC clock
  clk: imx: Explicitly include bits.h
  clk: imx8qxp: Support building i.MX8QXP clock driver as module
  clk: imx8m: Support module build
  clk: imx: Add clock configuration for ARMv7 platforms
  clk: imx: Support building i.MX common clock driver as module
  clk: composite: Export clk_hw_register_composite()
  clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits

* clk-qcom:
  clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
  clk: qcom: Add display clock controller driver for SM8150 and SM8250
  dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
  clk: qcom: add video clock controller driver for SM8250
  clk: qcom: add video clock controller driver for SM8150
  dt-bindings: clock: add SM8250 QCOM video clock bindings
  dt-bindings: clock: add SM8150 QCOM video clock bindings
  dt-bindings: clock: combine qcom,sdm845-videocc and qcom,sc7180-videocc
  clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs
  clk/qcom: fix spelling typo
  clk: qcom: gcc-sdm660: Fix wrong parent_map
  clk: qcom: dispcc: Update DP clk ops for phy design
  clk: qcom: gcc-msm8939: remove defined but not used variables
  clk: qcom: ipq8074: make pcie0_rchng_clk_src static

* clk-prima2:
  clk: clk-prima2: fix return value check in prima2_clk_init()

* clk-bcm:
  clk: bcm2835: add missing release if devm_clk_hw_register fails
  clk: bcm: rpi: Add register to control pixel bvb clk
2020-10-20 11:47:07 -07:00
Stephen Boyd
97f2f490c1 Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', 'clk-const' and 'clk-mmp2' into clk-next
* clk-semicolon:
  clk: meson: use semicolons rather than commas to separate statements
  clk: mvebu: ap80x-cpu: use semicolons rather than commas to separate statements
  clk: uniphier: use semicolons rather than commas to separate statements

* clk-axi-clkgen:
  clk: axi-clkgen: Set power bits for fractional mode
  clk: axi-clkgen: Add support for fractional dividers

* clk-qoriq:
  clk: qoriq: modify MAX_PLL_DIV to 32

* clk-baikal:
  clk: baikal-t1: Mark Ethernet PLL as critical

* clk-const:
  clk: pxa: Constify static struct clk_ops

* clk-mmp2:
  clk: mmp2: Fix the display clock divider base
2020-10-20 11:47:02 -07:00
Stephen Boyd
3ab9a54f76 Merge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and 'clk-mediatek' into clk-next
- Small non-critical fixes for TI clk driver
 - Support Mediatek MT8167 clks

* clk-simplify:
  clk: mediatek: fix platform_no_drv_owner.cocci warnings
  clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_init
  clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_init

* clk-ti:
  clk: ti: dra7: add missing clkctrl register for SHA2 instance
  clk: ti: clockdomain: fix static checker warning
  clk: ti: autoidle: add checks against NULL pointer reference
  clk: keystone: sci-clk: add 10% slack to set_rate
  clk: keystone: sci-clk: cache results of last query rate operation
  clk: keystone: sci-clk: fix parsing assigned-clock data during probe

* clk-tegra:
  clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate()

* clk-rockchip:
  clk: rockchip: Initialize hw to error to avoid undefined behavior
  clk: rockchip: rk3399: Support module build
  clk: rockchip: fix the clk config to support module build
  clk: rockchip: Export some clock common APIs for module drivers
  clk: rockchip: Export rockchip_register_softrst()
  clk: rockchip: Export rockchip_clk_register_ddrclk()
  clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
  clk: rockchip: rk3308: drop unused mux_timer_src_p

* clk-mediatek:
  clk: mediatek: Add MT8167 clock support
  dt-bindings: clock: mediatek: add bindings for MT8167 clocks
  clk: mediatek: add UART0 clock support
2020-10-20 11:46:47 -07:00
Stephen Boyd
9d3261628a Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner', 'clk-samsung', 'clk-doc' and 'clk-unused' into clk-next
- Remove various unused variables in clk drivers

* clk-renesas:
  clk: renesas: rcar-gen3: Update description for RZ/G2
  clk: renesas: cpg-mssr: Add support for R-Car V3U
  clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv
  clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
  dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0
  dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
  dt-bindings: power: Add r8a779a0 SYSC power domain definitions
  clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
  clk: renesas: r8a7742: Add clk entry for VSPR

* clk-amlogic:
  clk: meson: make shipped controller configurable
  clk: meson: g12a: mark fclk_div2 as critical
  clk: meson: axg-audio: fix g12a tdmout sclk inverter
  clk: meson: axg-audio: separate axg and g12a regmap tables
  clk: meson: add sclk-ws driver

* clk-allwinner:
  clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL
  clk: sunxi-ng: add support for the Allwinner A100 CCU
  dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU

* clk-samsung:
  clk: s2mps11: initialize driver via module_platform_driver
  clk: samsung: Use cached clk_hws instead of __clk_lookup() calls
  clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions
  clk: samsung: Add clk ID definitions for the CPU parent clocks
  clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks
  clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d
  clk: samsung: Keep top BPLL mux on Exynos542x enabled

* clk-doc:
  clk: davinci: add missing kerneldoc
  clk: fixed: add missing kerneldoc

* clk-unused:
  clk: socfpga: agilex: Remove unused variable 'cntr_mux'
  clk: si5341: drop unused 'err' variable
  clk: mmp: pxa1928: drop unused 'clk' variable
  clk: at91: drop unused at91sam9g45_pcr_layout
2020-10-20 11:46:34 -07:00
Abel Vesa
b159c63d82 clk: imx8mq: Fix usdhc parents order
According to the latest RM (see Table 5-1. Clock Root Table),
both usdhc root clocks have the parent order as follows:

000 - 25M_REF_CLK
001 - SYSTEM_PLL1_DIV2
010 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL3_CLK
101 - SYSTEM_PLL1_DIV3
110 - AUDIO_PLL2_CLK
111 - SYSTEM_PLL1_DIV8

So the audio_pll2_out and sys3_pll_out have to be swapped.

Fixes: b80522040c ("clk: imx: Add clock driver for i.MX8MQ CCM")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reported-by: Cosmin Stefan Stoica <cosmin.stoica@nxp.com>
Link: https://lore.kernel.org/r/1602753944-30757-1-git-send-email-abel.vesa@nxp.com
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-20 09:29:23 -07:00
Stephen Boyd
fda48bf5c8 clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
If the GDSC is enabled out of boot but doesn't have the retain ff bit
set we will get confusing results where the registers that are powered
by the GDSC lose their contents on the first power off of the GDSC but
thereafter they retain their contents. This is because gdsc_init() fails
to make sure the RETAIN_FF bit is set when it probes the GDSC the first
time and thus powering off the GDSC causes the register contents to be
reset. We do set the RETAIN_FF bit the next time we power on the GDSC,
see gdsc_enable(), so that subsequent GDSC power off's don't lose
register contents state.

Forcibly set the bit at device probe time so that the kernel's assumed
view of the GDSC is consistent with the state of the hardware. This
fixes a problem where the audio PLL doesn't work on sc7180 when the
bootloader leaves the lpass_core_hm GDSC enabled at boot (e.g. to make a
noise) but critically doesn't set the RETAIN_FF bit.

Cc: Douglas Anderson <dianders@chromium.org>
Cc: Taniya Das <tdas@codeaurora.org>
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Fixes: 173722995c ("clk: qcom: gdsc: Add support to enable retention of GSDCR")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20201017020137.1251319-1-sboyd@kernel.org
Reviewed-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org>
2020-10-20 09:28:55 -07:00
Geert Uytterhoeven
f6bade6875 clk: Restrict CLK_HSDK to ARC_SOC_HSDK
The HSDK PLL driver is only useful when building for an ARC HSDK
platform.
As ARC selects OF, the dependency on OF can just be replaced by a
dependency on ARC_SOC_HSDK.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200807094351.1046-1-geert+renesas@glider.be
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14 10:17:00 -07:00
Claudiu Beznea
fcedb589b5 clk: at91: sam9x60: support only two programmable clocks
According to datasheet (Chapter 29.16.13, PMC Programmable Clock Register)
there are only two programmable clocks on SAM9X60.

Fixes: 01e2113de9 ("clk: at91: add sam9x60 pmc driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1602686072-28296-1-git-send-email-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14 10:06:52 -07:00
Paul Cercueil
1a3c4dd4e1 clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
Clocks that don't have a divider are in our case all marked with the
CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation
should modify the value pointed to by parent_rate, in order to propagate
the rate change to the parent, as explained in the documentation of
clk_set_rate().

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-5-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13 20:04:50 -07:00
Paul Cercueil
2e4ee634f8 clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
The custom clocks have custom functions to round, get or set their rate.
Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-4-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13 20:04:50 -07:00
Paul Cercueil
3860dc599b clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
CLK_SET_RATE_GATE means that the clock must be gated when being
reclocked. This is not the case for the PLLs in Ingenic SoCs.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13 20:04:50 -07:00
Paul Cercueil
21534fe39c clk: ingenic: Use readl_poll_timeout instead of custom loop
Use the readl_poll_timeout() function instead of rolling our own
busy-wait loops. This makes the code simpler.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-2-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13 20:04:50 -07:00
Paul Cercueil
29c37341b5 clk: ingenic: Use to_clk_info() macro for all clocks
The to_clk_info() previously had a BUG_ON() to check that it was only
called for PLL clocks. Yet, all the other clocks were doing the exact
same thing the macro does, in-line.

Move the to_clk_info() macro to the top of the file, remove the
hardcoded BUG_ON(), and use it everywhere it makes sense.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13 20:04:50 -07:00
Navid Emamdoost
f6c992ca7d clk: bcm2835: add missing release if devm_clk_hw_register fails
In the implementation of bcm2835_register_pll(), the allocated pll is
leaked if devm_clk_hw_register() fails to register hw. Release pll if
devm_clk_hw_register() fails.

Signed-off-by: Navid Emamdoost <navid.emamdoost@gmail.com>
Link: https://lore.kernel.org/r/20200809231202.15811-1-navid.emamdoost@gmail.com
Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the audio domain clocks")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13 20:02:39 -07:00
Claudiu Beznea
c6968ac08d clk: at91: clk-sam9x60-pll: remove unused variable
Fix variable set but not used compilation warning.

Fixes: 43b1bb4a9b ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1598338751-20607-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13 19:59:01 -07:00
Claudiu Beznea
85d071e7f1 clk: at91: clk-main: update key before writing AT91_CKGR_MOR
SAMA5D2 datasheet specifies on chapter 33.22.8 (PMC Clock Generator
Main Oscillator Register) that writing any value other than
0x37 on KEY field aborts the write operation. Use the key when
selecting main clock parent.

Fixes: 27cb1c2083 ("clk: at91: rework main clk implementation")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1598338751-20607-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13 19:59:01 -07:00
Claudiu Beznea
eddfb2e1ee clk: at91: remove the checking of parent_name
There is no need to check parent_name variable while assigning it to
init.parent_names. parent_name variable is already checked at
the beginning of at91_clk_register_peripheral() function.

Fixes: 6114067e43 ("clk: at91: add PMC peripheral clocks")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1598338751-20607-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13 19:59:01 -07:00
Xu Wang
eff06bd5e5 clk: clk-prima2: fix return value check in prima2_clk_init()
In case of error, the function clk_register() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().

Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
Link: https://lore.kernel.org/r/20200921034522.9077-1-vulab@iscas.ac.cn
Acked-by: Barry Song <baohua@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13 19:54:30 -07:00