01d675f159 ARM: shmobile: rcar-gen2: Add watchdog support
58adf1ba0d ARM: shmobile: Add watchdog support
* SoC
- Identify R-Car V3H (r8a77980) and M3N (r8a77965)
- Enable R-Car Gen2 regulator quirk for Stout board with H3 (r8a7790) SoC
Marek Vaust says "Regulator setup is suboptimal on H2 Stout too. The
Stout newly has two DA9210 regulators, so the quirk is extended to
handle another DA9210 at i2c address 0x70."
- Add watchdog support
This is the SoC portion of the following solution. It is not yet
enabled in DT as it is not functional without clock dependencies
in place.
Fabrizio Castro says "this series has been around for some time as RFC,
and it has collected useful comments from the community along the way.
The solution proposed by this patch set works for most R-Car Gen2 and
RZ/G1 devices, but not all of them. We now know that for some R-Car
Gen2 early revisions there is no proper software fix. Anyway, no
product has been built around early revisions, but development boards
mounting early revisions (basically prototypes) are still out there.
As a result, this series isn't enabling the internal watchdog on R-Car
Gen2 boards, developers may enable it in board specific device trees if
needed. This series has been tested by me on the iwg20d, iwg22d,
Lager, Alt, and Koelsch boards.
The problem
===========
To deal with SMP on R-Car Gen2 and RZ/G1, we install a reset vector to
ICRAM1 and we program the [S]BAR registers so that when we turn ON the
non-boot CPUs they are redirected to the reset vector installed by Linux
in ICRAM1, and eventually they continue the execution to RAM, where the
SMP bring-up code will take care of the rest. The content of the [S]BAR
registers survives a watchdog triggered reset, and as such after the
watchdog fires the boot core will try and execute the SMP bring-up code
instead of jumping to the bootrom code.
The fix
=======
The main strategy for the solution is to let the reset vector decide if
it needs to jump to shmobile_boot_fn or to the bootrom code. In a
watchdog triggered reset scenario, since the [S]BAR registers keep their
values, the boot CPU will jump into the newly designed reset vector, the
assembly routine will eventually test WOVF (a bit in register RWTCSRA
that indicates if the watchdog counter has overflown, the value of this
bit gets retained in this scenario), and jump to the bootrom code which
will in turn load up the bootloader, etc. When bringing up SMP or using
CPU hotplug, the reset vector will jump to shmobile_boot_fn instead."
* R-Car Rst
- Add support for R-Car V3H (r8a77980) and V3H (r8a77980)
* R-Car SYSC
- Mark rcar_sysc_matches[] __initconst
Geert Uytterhoeven says "This frees another 1764 bytes
(arm32/shmobile_defconfig) or 1000 bytes (arm64/renesas_defconfig) of
memory after kernel init."
- Fix power area parents
Sergei Shtylyov says "According to the figure 9.2(b) of the R-Car
Series, 3rd Generation User’s Manual: Hardware Rev. 0.80 the A2IRn and
A2SCn power areas in R8A77970 have the A3IR area as a parent, thus the
SYSC driver has those parents wrong.."
- Add support for R-Car V3H (r8a77980) and V3H (r8a77980)
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlqr2U0ACgkQ189kaWo3
T76GQQ//TglmA64QnoynoYa7VR5VBvMoT4Hfd2LhUQaJ5dlqtnaIeipPIc/k5rlH
qsw5Jp7OlkNWAwchlIqkto+vfNhuxHItqvZoBnmrI2otEUvbaJ+9A2xAuhmYBxxH
awKoSTY4A+n8GFcCIOvYMzvRKVFUSIDSWYvYQSJtu6OyXZYI244qwcytgDyuHdRE
mS1nqdQkAcuxEdTLSwjct0puZTWMR41+NOM0B7qvVLDi2bnONUSS0ktLoEBiYO5D
Q7fpDOg6OZjIjVPYYb7hPSVw+jo+imyqgYdQ9CJu/r9j6Q7pn22NZ8MKWcTFsfYY
ZUhcJp1vHhTGMRupkgTi+oWSA7TFw1oxb1ZFCP1C5hL+mfryybVe5pBEwetOHg8A
DGb6OejvC1/amVArTco7JJ1Ul6Q2IU5UcvuOtmfT7UPNw05O/dIYjjV/BVfBHcGC
cDgVLq8Y6PGHjU2Jx1botuPdMSVsgZrQzbc8h7p02z9Klr9Drzh9+5oox5oxUlqb
A+60+OBHizY4g2/TCKvtPMWtEBt1Wjhayx/fF1EwD7/K16Wb2UFKizKbeZPTXHpH
KlltgVucDvqr/otJFBgS+Kg/7+ITq6hHrB3KCk4bjk+6qSXiZ93p58c4l7+A+JTB
S9q02YQC+cvy0StMrCpuc2R9n9EK0tmXFvv5hF8Ls938caGl6rI=
=S1q0
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc-for-v4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Pull "Renesas ARM Based SoC Updates for v4.17" from Simon Horman:
01d675f159 ARM: shmobile: rcar-gen2: Add watchdog support
58adf1ba0d ARM: shmobile: Add watchdog support
* SoC
- Identify R-Car V3H (r8a77980) and M3N (r8a77965)
- Enable R-Car Gen2 regulator quirk for Stout board with H3 (r8a7790) SoC
Marek Vaust says "Regulator setup is suboptimal on H2 Stout too. The
Stout newly has two DA9210 regulators, so the quirk is extended to
handle another DA9210 at i2c address 0x70."
- Add watchdog support
This is the SoC portion of the following solution. It is not yet
enabled in DT as it is not functional without clock dependencies
in place.
Fabrizio Castro says "this series has been around for some time as RFC,
and it has collected useful comments from the community along the way.
The solution proposed by this patch set works for most R-Car Gen2 and
RZ/G1 devices, but not all of them. We now know that for some R-Car
Gen2 early revisions there is no proper software fix. Anyway, no
product has been built around early revisions, but development boards
mounting early revisions (basically prototypes) are still out there.
As a result, this series isn't enabling the internal watchdog on R-Car
Gen2 boards, developers may enable it in board specific device trees if
needed. This series has been tested by me on the iwg20d, iwg22d,
Lager, Alt, and Koelsch boards.
The problem
===========
To deal with SMP on R-Car Gen2 and RZ/G1, we install a reset vector to
ICRAM1 and we program the [S]BAR registers so that when we turn ON the
non-boot CPUs they are redirected to the reset vector installed by Linux
in ICRAM1, and eventually they continue the execution to RAM, where the
SMP bring-up code will take care of the rest. The content of the [S]BAR
registers survives a watchdog triggered reset, and as such after the
watchdog fires the boot core will try and execute the SMP bring-up code
instead of jumping to the bootrom code.
The fix
=======
The main strategy for the solution is to let the reset vector decide if
it needs to jump to shmobile_boot_fn or to the bootrom code. In a
watchdog triggered reset scenario, since the [S]BAR registers keep their
values, the boot CPU will jump into the newly designed reset vector, the
assembly routine will eventually test WOVF (a bit in register RWTCSRA
that indicates if the watchdog counter has overflown, the value of this
bit gets retained in this scenario), and jump to the bootrom code which
will in turn load up the bootloader, etc. When bringing up SMP or using
CPU hotplug, the reset vector will jump to shmobile_boot_fn instead."
* R-Car Rst
- Add support for R-Car V3H (r8a77980) and V3H (r8a77980)
* R-Car SYSC
- Mark rcar_sysc_matches[] __initconst
Geert Uytterhoeven says "This frees another 1764 bytes
(arm32/shmobile_defconfig) or 1000 bytes (arm64/renesas_defconfig) of
memory after kernel init."
- Fix power area parents
Sergei Shtylyov says "According to the figure 9.2(b) of the R-Car
Series, 3rd Generation User’s Manual: Hardware Rev. 0.80 the A2IRn and
A2SCn power areas in R8A77970 have the A3IR area as a parent, thus the
SYSC driver has those parents wrong.."
- Add support for R-Car V3H (r8a77980) and V3H (r8a77980)
* tag 'renesas-soc-for-v4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: rcar-gen2: Add watchdog support
ARM: shmobile: Add watchdog support
ARM: shmobile: rcar-gen2: Fix error check in regulator quirk
soc: renesas: rcar-rst: Add support for R-Car M3-N
ARM: shmobile: stout: enable R-Car Gen2 regulator quirk
soc: renesas: rcar-sysc: Add R-Car M3-N support
soc: renesas: Identify R-Car M3-N
soc: renesas: rcar-sysc: add R8A77980 support
dt-bindings: power: add R8A77980 SYSC power domain definitions
soc: renesas: r8a77970-sysc: fix power area parents
soc: renesas: rcar-rst: Enable watchdog as reset trigger for Gen2
soc: renesas: rcar-rst: add R8A77980 support
soc: renesas: identify R-Car V3H
soc: renesas: rcar-sysc: Mark rcar_sysc_matches[] __initconst
This series of changes from Dave Gerlach adds the PM related
code to allow low-power suspend states. The code consists of
the SoC specific assembly code and a related PM driver.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlqdeI4RHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXPRoxAA3M1qhApgnJBrvCoVbOQbDsL/Jst5geJz
eQIQMjqzLTJQDd6+0SJVggjRhDYW2mKk+SYbpbzjVfmdJeKAIX3IZj9MUMstbRSD
g8YCzSpW9C2EuOHlDhDDd4U6pc7/pMmWHH87PMaj05Qfct+hcSpI7OB5RfntX0Os
mhQ6e3SxlM9EZikiW2BXXjjKmQHYmqkfSZHhjbiGtpEXTa/zq/fVM67NEjdez7/F
1Uy3Hefv895H0TU+P3TtzLmvcQQn4JrIXNqi4wWM7ATf6MN9d9cPMxZ9mdTweCgd
B0nSYgwwzXS2bNd7KhtghAXckGqLRL+0CifB0xw+jCExwL+aOQPwKdvbfnF2JVqe
R8MochWgDBUAVX8hYpYD+IJ6qeoWFfu4ZEwFeMaQ0M2T7I417SSRwtNF2P9YSYOj
b6dv8Fe54m8QhPJo2OPD/bbzo2wwNuLqJ9bqI3oy9yrMe5EEAzuhtqGBeg1B4WKB
zWB2TQYLLl4FVJsfxV7wgsO2fk9xzs1cn70JWqdWMQ1kUl7k0NorZhSVlXt5x+oH
gPfkWO2S7+Il/FKsOAdb+HeCklDyy/xh/B0VFErHvqXOK78j1IpcUh6I9lgg1GFs
OXioMaGE13p+yOKQHDGqeK42Qjw2F6cPdkCGm67Mte66IqBV0khLpwK8WwzlcEio
C5jhVOor2u8=
=hBzh
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.17/am-pm-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Pull "Add am335x and am437x PM code for v4.17" from Tony Lindgren:
This series of changes from Dave Gerlach adds the PM related
code to allow low-power suspend states. The code consists of
the SoC specific assembly code and a related PM driver.
* tag 'omap-for-v4.17/am-pm-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
soc: ti: Add pm33xx driver for basic suspend support
ARM: OMAP2+: pm33xx-core: Add platform code needed for PM
ARM: OMAP2+: Introduce low-level suspend code for AM43XX
ARM: OMAP2+: Introduce low-level suspend code for AM33XX
This is the first set of bugfixes for ARM SoCs, fixing a couple
of stability problems, mostly on TI OMAP and Rockchips platforms:
- OMAP2 hwmod clocks must be enabled in the correct order
- OMAP3 Wakeup from resume through PRM IRQ was unreliable
- One regression on OMAP5 caused by a kexec fix
- Rockchip ethernet needs some settings for stable operation on Rock64
- Rockchip based Chrombook Plus needs another clock setting for
stable display suspend/resume
- Rockchip based phyCORE-RK3288 was able to run at an invalid
CPU clock frequency
- Rockchip MMC link was sometimes unreliable
- Multiple fixes to avoid crashes in the Broadcom STB DPFE driver
Other minor changes include:
- Devicetree fixes for incorrect hardware description (rockchip,
omap, Gemini, amlogic)
- Some MAINTAINER file updates to correct email and git addresses
- Some fixes addressing 'make W=1' dtc warnings (broadcom, amlogic,
cavium, qualcomm, hisilicon, zx)
- Fixes for LTO-compilation (orion, davinci, clps711x)
- One fix for an incorrect Kconfig errata selection
- A memory leak in the OMAP timer driver
- A kernel data leak in OMAP1 debugfs files
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJalzTaAAoJEGCrR//JCVInBeQP/3wBXCnzfCkmSSliZHoNzgYB
XGkC+JIqw9AnHvn/ckvHMwUv8kQlbi7ImPXz1P8yafy3h2vHIdN2My0XYtRyQkNT
NoAxIXT+NiQx9sAoLGY8gWTN4Do63q1vw5SLmOEDD2GYzo1jao4s7J0mhFZopBLw
WkgHf8t4jRmoBDA4GEYcdJZS5shMydFDyb9CiiqNHVA4S4IL87XcPoJDpJmyVDZ4
vZVeccyhw0Xh0NJLzRIhVDGRN2pj1ayFFVodfRNTseRGf0QRexntiIyIHa2wOi1l
93IjJ3XgHuYEj0NNNpZiHV5OZxxRbQlTD/ji5L8j71lklVjIedJsJdWFUKiK53oh
ufQXTRZaVMmh4xcvihABSchg8vEXMqx4cZ/hj/+LIepDJM6GC39uGipg6enORVym
BuZpol8b1owABN461Bt2RfAVyXqJ7TRkdVy+RaP7RCsddLEcdKdI6HYi3aeDVmHQ
krvTrLQhRsDL4IHvi6rQDqyJMf5GDP4y7aInf7YzvJlbV2uU+M0ndiSHpGhw6vbG
brhc/n56U/waMPG8tOv9AB1+afARQOc4Fo9xg96PADA69SXn7Eq2dgf1D/ern8UQ
6KgNZ1hmmEHzkxsAXjEcStlmhpwk4lh4T0nSDbamsMRvZRNQaqmskMbmYYepIXKC
71k/Uwf4CQhMxe2aXIOo
=fcv0
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann:
"This is the first set of bugfixes for ARM SoCs, fixing a couple of
stability problems, mostly on TI OMAP and Rockchips platforms:
- OMAP2 hwmod clocks must be enabled in the correct order
- OMAP3 Wakeup from resume through PRM IRQ was unreliable
- one regression on OMAP5 caused by a kexec fix
- Rockchip ethernet needs some settings for stable operation on
Rock64
- Rockchip based Chrombook Plus needs another clock setting for
stable display suspend/resume
- Rockchip based phyCORE-RK3288 was able to run at an invalid CPU
clock frequency
- Rockchip MMC link was sometimes unreliable
- multiple fixes to avoid crashes in the Broadcom STB DPFE driver
Other minor changes include:
- Devicetree fixes for incorrect hardware description (rockchip,
omap, Gemini, amlogic)
- some MAINTAINER file updates to correct email and git addresses
- some fixes addressing 'make W=1' dtc warnings (broadcom, amlogic,
cavium, qualcomm, hisilicon, zx)
- fixes for LTO-compilation (orion, davinci, clps711x)
- one fix for an incorrect Kconfig errata selection
- a memory leak in the OMAP timer driver
- a kernel data leak in OMAP1 debugfs files"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits)
MAINTAINERS: update entries for ARM/STM32
ARM: dts: bcm283x: Move arm-pmu out of soc node
ARM: dts: bcm283x: Fix unit address of local_intc
ARM: dts: NSP: Fix amount of RAM on BCM958625HR
ARM: dts: Set D-Link DNS-313 SATA to muxmode 0
ARM: omap2: set CONFIG_LIRC=y in defconfig
ARM: dts: imx6dl: Include correct dtsi file for Engicam i.CoreM6 DualLite/Solo RQS
memory: brcmstb: dpfe: support new way of passing data from the DCPU
memory: brcmstb: dpfe: fix type declaration of variable "ret"
memory: brcmstb: dpfe: properly mask vendor error bits
ARM: BCM: dts: Remove leading 0x and 0s from bindings notation
ARM: orion: fix orion_ge00_switch_board_info initialization
ARM: davinci: mark spi_board_info arrays as const
ARM: clps711x: mark clps711x_compat as const
arm: zx: dts: Remove leading 0x and 0s from bindings notation
arm64: dts: Remove leading 0x and 0s from bindings notation
arm64: dts: cavium: fix PCI bus dtc warnings
MAINTAINERS: ARM: at91: update my email address
soc: imx: gpc: de-register power domains only if initialized
ARM: dts: rockchip: Fix DWMMC clocks
...
AM335x and AM437x support various low power modes as documented
in section 8.1.4.3 of the AM335x Technical Reference Manual and
section 6.4.3 of the AM437x Technical Reference Manual.
DeepSleep0 mode offers the lowest power mode with limited
wakeup sources without a system reboot and is mapped as
the suspend state in the kernel. In this state, MPU and
PER domains are turned off with the internal RAM held in
retention to facilitate the resume process. As part of
the boot process, the assembly code is copied over to OCMCRAM
so it can be executed to turn of the EMIF and put DDR into self
refresh.
Both platforms have a Cortex-M3 (WKUP_M3) which assists the MPU
in DeepSleep0 entry and exit. WKUP_M3 takes care
of the clockdomain and powerdomain transitions based on the
intended low power state. MPU needs to load the appropriate
WKUP_M3 binary onto the WKUP_M3 memory space before it can
leverage any of the PM features like DeepSleep. This loading
is handled by the remoteproc driver wkup_m3_rproc.
Communication with the WKUP_M3 is handled by a wkup_m3_ipc
driver that exposes the specific PM functionality to be used
the PM code.
In the current implementation when the suspend process
is initiated, MPU interrupts the WKUP_M3 to let it know about
the intent of entering DeepSleep0 and waits for an ACK. When
the ACK is received MPU continues with its suspend process
to suspend all the drivers and then jumps to assembly in
OCMC RAM. The assembly code puts the external RAM in self-refresh
mode, gates the MPU clock, and then finally executes the WFI
instruction. Execution of the WFI instruction with MPU clock gated
triggers another interrupt to the WKUP_M3 which then continues
with the power down sequence wherein the clockdomain and
powerdomain transition takes place. As part of the sleep sequence,
WKUP_M3 unmasks the interrupt lines for the wakeup sources. WFI
execution on WKUP_M3 causes the hardware to disable the main
oscillator of the SoC and from here system remains in sleep state
until a wake source brings the system into resume path.
When a wakeup event occurs, WKUP_M3 starts the power-up
sequence by switching on the power domains and finally
enabling the clock to MPU. Since the MPU gets powered down
as part of the sleep sequence in the resume path ROM code
starts executing. The ROM code detects a wakeup from sleep
and then jumps to the resume location in OCMC which was
populated in one of the IPC registers as part of the suspend
sequence.
Code is based on work by Vaibhav Bedia.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
On lkml suggestions were made to split up such trivial typo fixes into per subsystem
patches:
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -439,7 +439,7 @@ setup_uga32(void **uga_handle, unsigned long size, u32 *width, u32 *height)
struct efi_uga_draw_protocol *uga = NULL, *first_uga;
efi_guid_t uga_proto = EFI_UGA_PROTOCOL_GUID;
unsigned long nr_ugas;
- u32 *handles = (u32 *)uga_handle;;
+ u32 *handles = (u32 *)uga_handle;
efi_status_t status = EFI_INVALID_PARAMETER;
int i;
This patch is the result of the following script:
$ sed -i 's/;;$/;/g' $(git grep -E ';;$' | grep "\.[ch]:" | grep -vwE 'for|ia64' | cut -d: -f1 | sort | uniq)
... followed by manual review to make sure it's all good.
Splitting this up is just crazy talk, let's get over with this and just do it.
Reported-by: Pavel Machek <pavel@ucw.cz>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
If power domain information are missing in the device tree, no
power domains get initialized. However, imx_gpc_remove tries to
remove power domains always in the old DT binding case. Only
remove power domains when imx_gpc_probe initialized them in
first place.
Fixes: 721cabf6c6 ("soc: imx: move PGC handling to a new GPC driver")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for R-Car M3-N (R8A77965) power areas.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add support for R-Car V3H (R8A77980) SoC power areas to the R-Car SYSC
driver.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to the figure 9.2(b) of the R-Car Series, 3rd Generation User’s
Manual: Hardware Rev. 0.80 the A2IRn and A2SCn power areas in R8A77970 have
the A3IR area as a parent, thus the SYSC driver has those parents wrong...
Fixes: bab9b2a74f ("soc: renesas: rcar-sysc: add R8A77970 support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch allows for platform specific quirks as some of the SoC need
further customization for the watchdog to work properly, like for R-Car
Gen2 and for RZ/G.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add support for R-Car V3H (R8A77980) to the R-Car RST driver -- this driver
is needed for the clock driver to work.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add support for identifying the R-Car V3H (R8A77980) SoC.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
rcar_sysc_matches[] is used only by rcar_sysc_pd_init(), which is
__init. Hence mark rcar_sysc_matches[] __initconst.
This frees another 1764 bytes (arm32/shmobile_defconfig) or 1000 bytes
(arm64/renesas_defconfig) of memory after kernel init.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
A number of new drivers get added this time, along with many low-priority
bugfixes. The most interesting changes by subsystem are:
bus drivers:
- Updates to the Broadcom bus interface driver to support newer SoC types
- The TI OMAP sysc driver now supports updated DT bindings
memory controllers:
- A new driver for Tegra186 gets added
- A new driver for the ti-emif sram, to allow relocating
suspend/resume handlers there
SoC specific:
- A new driver for Qualcomm QMI, the interface to the modem on MSM SoCs
- A new driver for power domains on the actions S700 SoC
- A driver for the Xilinx Zynq VCU logicoreIP
reset controllers:
- A new driver for Amlogic Meson-AGX
- various bug fixes
tee subsystem:
- A new user interface got added to enable asynchronous communication
with the TEE supplicant.
- A new method of using user space memory for communication with
the TEE is added
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJac0fQAAoJEGCrR//JCVIntjEQALc6kflEGJc/FPundbx9V3F/
b+3+EX/uMnBnKsgZprz9ACPhx5eBH9QWja3A1zmIarb5c+q7zbBZDwhzUb8J8Yg8
xEb0im7Wx/GcKjUYZVKYBxtz9KjkXDzhrq8IAvPg6ShNcIy/8hq7ZO3iOkGsTDcy
/PyioWKC5g0dhJgtp91X1kgog5tuTaWOg39uUOqyEzwVu1vYVa4w+eeCzjEd6I//
68R/zDQ52+hWw6WZGoYOsNYzuriOflnJRnNpwuGhMhLNULBJfWnd4hkqGm4E+hFa
5dzW6vVAdIqjemFqPzCBT2WB4UG871aZX8DJ9HgnfX+g970nlsm1JY8Ck9MJNJum
aDkqZG41ArUYzDFWu8vJ2SKsue5lEZp6TEO2mLEVYrdOjOgedj0Zxqmq2DYeigxd
+ccOVgKJ9SsYw9ft1LkQ5BHCgOh3C7y9Kcg7oBnaEI5OTVvtf5PwEkT2cwbvgxYl
EVKLhlJ0Af+QXOW8E5JbNQETpYw52DMm6UKHiYn/JCGxB/8J0bgJzImDJI4Dtu2h
zqJITKJeTepqbfA5pmNfKa+20RhmsktdRCw2NN/QynY7EEtGjHAUVnlpZT2mrDco
0m62b7Erek/776vJN5ECzE5e6XCs2N0MDE6Anp121C5zEmig/SMBrUosMzP7Jnis
IDVC/QWkb3u85wK20Vc1
=yz0k
-----END PGP SIGNATURE-----
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"A number of new drivers get added this time, along with many
low-priority bugfixes. The most interesting changes by subsystem are:
bus drivers:
- Updates to the Broadcom bus interface driver to support newer SoC
types
- The TI OMAP sysc driver now supports updated DT bindings
memory controllers:
- A new driver for Tegra186 gets added
- A new driver for the ti-emif sram, to allow relocating
suspend/resume handlers there
SoC specific:
- A new driver for Qualcomm QMI, the interface to the modem on MSM
SoCs
- A new driver for power domains on the actions S700 SoC
- A driver for the Xilinx Zynq VCU logicoreIP
reset controllers:
- A new driver for Amlogic Meson-AGX
- various bug fixes
tee subsystem:
- A new user interface got added to enable asynchronous communication
with the TEE supplicant.
- A new method of using user space memory for communication with the
TEE is added"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (84 commits)
of: platform: fix OF node refcount leak
soc: fsl: guts: Add a NULL check for devm_kasprintf()
bus: ti-sysc: Fix smartreflex sysc mask
psci: add CPU_IDLE dependency
soc: xilinx: Fix Kconfig alignment
soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv
soc: xilinx: xlnx_vcu: Depends on HAS_IOMEM for xlnx_vcu
soc: bcm: brcmstb: Be multi-platform compatible
soc: brcmstb: biuctrl: exit without warning on non brcmstb platforms
Revert "soc: brcmstb: Only register SoC device on STB platforms"
bus: omap: add MODULE_LICENSE tags
soc: brcmstb: Only register SoC device on STB platforms
tee: shm: Potential NULL dereference calling tee_shm_register()
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver
soc: xilinx: Create folder structure for soc specific drivers
of: platform: populate /firmware/ node from of_platform_default_populate_init()
soc: samsung: Add SPDX license identifiers
soc: qcom: smp2p: Use common error handling code in qcom_smp2p_probe()
tee: shm: don't put_page on null shm->pages
...
This adds new SoC support and more error path handling to the guts
driver.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJaZm0uAAoJEIbcUA77rBVUHCIQAMQTD+kO2gUWhMsC2LOsU366
NKWiDU4xw48umFil56OLCEalIX/nBDZqL7PYpptFBDURIjychjj1J/M/oHra+EDj
S+/a53gBBNVb7rn9w+H8sfVbGCSK4Wv+S2L9KrIrZEzqFahSld9R5UAf63S4OZLp
zzrPqmsrXQI4JkHmJF1LAxPDoHIeaNI4HQiFnKuVQWEZYFh80r1x04pAh8A45mrN
0jZd+853VaCq8HQSUGeLNn6o7SCYZOdSun7wNrgLrc0ilM0JNeMKfm/A8uCB4C6p
yPJL5M+33k9at2plUNmA/gVw3pHoOt4Huwu+yGYbhyTVct8z2jL96ZrgG1niklG9
8fN8otbSUyvm2eTY+VHinoFtod2z+s7lXZc8+rGkfhLJDu1A6/6jRA1lwiubUKDf
mJ1JhBk6kJ7yDqanKsw6SSYA0ptCPpsxVlkNbWgc7TAgwWf/Soy1gfQQWqjuXaz0
jcFhHUPgeP9gEgxZMjqwwvnrxSG+sCRy3qHdkH3S/x06qbcU4rHCXLS8CeiDAy1M
pAN741ERND3tPFhfdnbpEe58rkhnvZcbF6nEkviaimQ5y11xlw0TvwX18pKkcwA2
u79KB6ZxxeIKBqZNR0DXb42uOW8xhCcXdglKYcfEYDUxRyfDHNUPphULbhpFTSp5
G0AefICjtKRsrxoZUaiK
=2hOy
-----END PGP SIGNATURE-----
Merge tag 'soc-fsl-for-4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/leo/linux into next/drivers
Pull "FSL/NXP SoC drivers updates for 4.16" from Li Yang:
This adds new SoC support and more error path handling to the guts
driver.
* tag 'soc-fsl-for-4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/leo/linux:
soc: fsl: guts: Add a NULL check for devm_kasprintf()
soc: fsl: support GUTS driver for ls1012a/ls1046a
devm_kasprintf() may fail, so we should better add a NULL check
and propagate an error on failure.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Currently clkoutdiv is being operated on by a logical && operator rather
than a bitwise & operator. This looks incorrect as these should be bit
flag operations.
Addresses-Coverity-ID: 1463959 ("Logical vs. bitwise operator")
Fixes: cee8113a29 ("soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver")
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Acked-by: Dhaval Shah <dshah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
xlnx_vcu driver uses devm_ioremap_nocache, which is included
only when HAS_IOMEM is enabled.
drivers/soc/xilinx/xlnx_vcu.o: In function `xvcu_probe':
xlnx_vcu.c:(.text+0x116): undefined reference to `devm_ioremap_nocache'
xlnx_vcu.c:(.text+0x1ae): undefined reference to `devm_ioremap_nocache'
Signed-off-by: Dhaval Shah <dshah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We were making a bunch of wrong assumptions that turned out to blow out
on non-Broadcom STB platforms:
- we would return -ENODEV from brcmstb_soc_device_early_init() if we
could not find the sun_top_ctrl device node, this is not an error
in the context of a multi-platform kernel
- we would still try to register the Broadcom STB SoC device, even if we
are not running on such a platform
While at it, also fix the sun_top_ctrl device_node leaks while we change
the flow of brcmstb_soc_device_init() and
brcmstb_soc_device_early_init().
Fixes: f780429adf ("soc: brcmstb: biuctrl: Move to early_initcall")
Signed-off-by: Thierry Reding <treding@nvidia.com>
[florian: Combine all of Thierry's patch in one go for easier review]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Currently if this driver is included, we get the following warning
on any platforms irrespective of whether it's brcmstb platform or not.
"
brcmstb: biuctrl: missing BIU control node
brcmstb: biuctrl: MCP: Unable to disable write pairing!
"
This patch allows to exit early without any warning messages on non
brcmstb platforms as it's meaningless for them.
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Gregory Fong <gregory.0xf0@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Fixes: f780429adf ("soc: brcmstb: biuctrl: Move to early_initcall")
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
[florian: Add fixes tag, make initcall non fatal]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This reverts commit 23a0d84799.
Patch has issues that's being addressed by the Florian and he will
follow up with a new patch to address the original issue.
Signed-off-by: Olof Johansson <olof@lixom.net>
After moving the SoC device initialization to an early initcall in
commit f780429adf ("soc: brcmstb: biuctrl: Move to early_initcall"),
the Broadcom STB SoC device is registered on all platforms if support
for the device is enabled in the kernel configuration.
This causes an additional SoC device to appear on platforms that already
register a native one. In case of Tegra the STB SoC device is registered
as soc0 (with totally meaningless content in the sysfs attributes) and
causes various scripts and programs to fail because they don't know how
to parse that data.
To fix this, duplicate the check from brcmstb_soc_device_early_init()
that already prevents the code from doing anything nonsensical on non-
STB platforms.
Fixes: f780429adf ("soc: brcmstb: biuctrl: Move to early_initcall")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Xilinx ZYNQMP logicoreIP Init driver is based on the new
LogiCoreIP design created. This driver provides the processing system
and programmable logic isolation. Set the frequency based on the clock
information get from the logicoreIP register set.
Signed-off-by: Dhaval Shah <dshah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
- Update i.MX GPC driver to support PCI power domain of i.MX6SX SoC.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJaTCqGAAoJEFBXWFqHsHzOavcH/1g0k3tN4MaOvf44lSDm5uCZ
WqCKLN01f8T02YegdcgVVc59wirJB6xKIYD86dQIiVC8gEfMOhvfEuv6qkPRHQOM
WVYJTIFFisEeypnXEHjD2SwN6/SskSGPMUDpfj0hveb0srLnCQou+5Ty8zpvmAdl
XEAP9mjK7s6ovfomfuxEY4iWxGRKbDXtwXqtvYTI3tpXwn/c6LXgdrg02xC/KAXp
sKXbS0NbYjBDHBd8hPcVVwujugw3UZHr/saYYf0rmC7WKr7074WylSWW08aKQ89u
Elv5fNeoAYrlnwpeoqzLqcgrvhCJcpx0HTVnYjmNIVLYRLAktYu6glR7icAdpb8=
=kB/f
-----END PGP SIGNATURE-----
Merge tag 'imx-drivers-4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/drivers
Pull "i.MX drivers update for 4.16" from Shawn Guo:
- Update i.MX GPC driver to support PCI power domain of i.MX6SX SoC.
* tag 'imx-drivers-4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: gpc: Add i.MX6SX PCI power domain
* rcar-sysc: Keep wakeup sources active during system suspend
Geert Uytterhoeven says "If an R-Car SYSC slave device is part of the
CPG/MSTP or CPG/MSSR Clock Domain and to be used as a wakeup source, it
must be kept active during system suspend.
Currently this is handled in device-specific drivers by explicitly
increasing the use count of the module clock when the device is
configured as a wakeup source. However, the proper way to prevent the
device from being stopped is to inform this requirement to the genpd
core, by setting the GENPD_FLAG_ACTIVE_WAKEUP flag.
Note that this will only affect devices configured as wakeup sources."
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlo81TEACgkQ189kaWo3
T76Lrw/+LccDaaNJppUYzGUSPQ0P6BYgmac8fv5A3qk63CzdemirAqhA3LdXNNEn
RW1VpVBeLPv1GMYdxvuS0HqvfBPk92hFFJXMyRsjS5PF4pSupHubBM2g34u7qcGg
7D6MxyZYlPxFPMyb3DIqNDKHbt+PMxeidtoMylNURBPJS3ERLo+RUeAco1SBTW2Q
hojrDBB7P5CGSNkfJ+VjYExYgZgfCfyzVyozMHmWUuPul3ZdfKfXf/ZhAp2BVAEN
ZTiccpZpSo6dZyYnMTEQ9Pd4eOlrBl3EfHdZcbeH+VzXou50KvzQ+6cWdHKMsc6w
bUvKxXy/uEiqq6Bs83AdUAb9UvCKM9bK8jLZXScmPHQUZWt+K2WemlrRPgtekKR1
VEGmABFwKEtcEzwXzkcG4fe1SxrJdPrBljwFk89KpqSAn4+TElqBAmo/F5V/ALj7
l2AuqcGMzazuSnGSVk6ha/BXqdP0IKbk6mq/UqO/ORNsOjaajtXcjuKHDowBzPN9
aHTLMPXRPWSvHGQEuxOggNHm0Cehjwni8t0pku3ndG8TNx2DsaG8L/rUTNUU/J2m
ynWuFBbzReB0epHBuXJMvWPd9AWX+kL12KouDvFbp0a4b5L1KSTka3oXlC88oXkl
CMKXS6VQJ8nda9Dev9Za19BnUQrgeHq0anD5Q9wVeWwauh8Uueg=
=0tvJ
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc2-for-v4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Second Round of Renesas ARM Based SoC Updates for v4.16
* rcar-sysc: Keep wakeup sources active during system suspend
Geert Uytterhoeven says "If an R-Car SYSC slave device is part of the
CPG/MSTP or CPG/MSSR Clock Domain and to be used as a wakeup source, it
must be kept active during system suspend.
Currently this is handled in device-specific drivers by explicitly
increasing the use count of the module clock when the device is
configured as a wakeup source. However, the proper way to prevent the
device from being stopped is to inform this requirement to the genpd
core, by setting the GENPD_FLAG_ACTIVE_WAKEUP flag.
Note that this will only affect devices configured as wakeup sources."
* tag 'renesas-soc2-for-v4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
soc: renesas: rcar-sysc: Keep wakeup sources active during system suspend
Signed-off-by: Olof Johansson <olof@lixom.net>
The SPS power domain driver is extended for S700 SoC.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJaPNqqAAoJEPou0S0+fgE/IVYP/i0VYqTyCSz6yDJJU4N02lvN
wp4k7QSLKgX2GcNScYEu7hwfooourZGW0xk+A5lk9sBwspYxw+uWcd0kFmlwkBbp
Dk7f0YjsjnC2ipWMv327RClC6BrgEigydbkDyaH7jAF/FXlgo0VJWkjI+ZcayU6j
ZchrqyGm20ASlkm6HD6cPY0GPu918cKr6XhOON2xE2lPuXRUVQd9XHkJAXXQFCQ2
oomavKzTtT0kH/4uEZnKGB0xyx9v8LzDTEVUkfZhXiOnN5Elh0Spmev0JlEnWTtn
6J9hSnxNcQov4klbg3oRDk9kXpD1yTXtpwy8mNvMGtKq9Y93WMsH2S+GwyElEtDM
EqxpOaREXnVOeJ04uMwZgXeLyQMn73qw+FFF02QU6VRU+j5gz7MTsif4BWx2gBAw
CygX6I+zq86VpIl7beVaSVEI49QYUF5ygJB1zT31IN6jZX1D1g5D7GBmzq1sPieE
uzzI6EH3LgrNJrVXe39PqCwzQIDtQHDYNo3je3sexDvTB6mUpSEMzZuJgpWnA7jS
TjrjNGwmUpL/FaMPRdBr4VUhgd1uQmYcC5lzAo5wOl40QzABsMObXPcf6uE/Myau
f+ZbI3HgmivLzOkoQct8bRpjzsXCFoXGW76kkxdmptY7PkeE6orjHwFMEPb6VUES
FBVr27/EoQc9dIf12c3V
=u1IY
-----END PGP SIGNATURE-----
Merge tag 'actions-drivers-for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/drivers
Actions Semi SoC drivers for v4.16
The SPS power domain driver is extended for S700 SoC.
* tag 'actions-drivers-for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions:
soc: actions: sps: Add S700
Signed-off-by: Olof Johansson <olof@lixom.net>
4.16, please pull the following:
- Arnd provides an update to the Raspberry Pi firmware interface and uses time64_t to
print the time to make it more future proof
- Florian provides a set of updates to make the Broadcom STB Bus Interface Unit code
work on newer ARM64-based chips, as well as perform the correct interface tuning
for these chips to reach the expected performance
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJaPE0dAAoJEIfQlpxEBwcEk/oQALjUzNWkipO31Ahx35r7kblW
4RC39ebaU31fR6yMOlKWQGh/uklHopcDuRQHAGR7IHg2MSr/uQ/xb7rgz4Qa1ZTD
gRPcT9rI2mNctiWLFoB3EaYmA0J3EOMJI1GMIvHPGc3WZ5Y4FHKICW3qK7mvGndc
obmiAU4mFyK31SKKm8k+TX6bzPsr1ZEm2tW9kRkWKfGk05DVD+KsKa5Xvn0USlS4
0jiXo+naHv5KtYXSuSc+Kg0qcCB3K2SFJVAOPgjTMzo498Vcv6mWLQPfGg3vDmCt
3rEiDhPoJJ6soAuG2OmHQCykTr0uwRZNhOc385JCKf8TP8CjV8aK71lJe0oFQgtg
nC67z+uVLJ3tXoI1Y0V0DQXCTNLKgsbU19p14S+rDM2MQ41yGzWoVdT9ZhEDEbyj
sDeC+d9DVQTuXqImqe16M3oZSsCWuMCRz0LG2uDhoTHMNmegU//nY6VhVR7ia0Ia
BIDCsbNf1KEDEUi1v5nPJSNC2Oyk/mVOPzl8xwMdw3VV4eYggC9aqljmwDWWCxV5
GNCGbP/0UgKG6iUadqK2HM+0syRWA5E3ypWg8VPtU6g+lZKYqnh6g23F4lJklE1U
WhKKK52OCRZ0w/ut2TWJmhpmn+CfR7VcVv9IS9zElBbyU/fg27Mkpu/Ty7bBx0my
kmCDHOGHZyl4jrKhwxGg
=RHHM
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-4.16/drivers' of http://github.com/Broadcom/stblinux into next/drivers
This pull request contains Broadcom ARM/ARM64 based SoCs drivers changes for
4.16, please pull the following:
- Arnd provides an update to the Raspberry Pi firmware interface and uses time64_t to
print the time to make it more future proof
- Florian provides a set of updates to make the Broadcom STB Bus Interface Unit code
work on newer ARM64-based chips, as well as perform the correct interface tuning
for these chips to reach the expected performance
* tag 'arm-soc/for-4.16/drivers' of http://github.com/Broadcom/stblinux:
soc: brcmstb: biuctrl: Move to early_initcall
soc: brcmstb: Split initialization
soc: brcmstb: biuctrl: Fine tune B53 MCP interface settings
soc: brcmstb: biuctrl: Wire-up new registers
soc: brcmstb: biuctrl: Prepare for saving/restoring other registers
soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUs
soc: brcmstb: Make CPU credit offset more parameterized
dt-bindings: arm: brcmstb: Correct BIUCTRL node documentation
dt-bindings: arm: Add entry for Broadcom Brahma-B53
firmware: raspberrypi: print time using time64_t
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds an SoC driver for the Gemini. Currently there
is only one thing not fitting into any other framework,
and that is the bus arbitration setting.
All Gemini vendor trees seem to be setting this register to
exactly the same arbitration so we just add a small code
snippet to do this at subsys_init() time before any other
drivers kick in.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Add a jump target so that a specific error message is stored only once
at the end of this function implementation.
* Replace two calls of the function "dev_err" by goto statements.
* Adjust two condition checks.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
i.MX6SX has a PCI power domain in PGC. Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
- add support for mt2701 scpsys driver
binding documentation
extend driver to allow the bus protection to overwrite the register
-----BEGIN PGP SIGNATURE-----
iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAlo7nMIXHG1hdHRoaWFz
LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00MF/Q/9GOX4n+FAPR8OXQcSn8X5L6Ep
RvUr3np4IFfLBXBReM6nR479+LOE5VLIk/eAad0Avsnbv3TZw38+nXN4vU3skLkr
byuri9SRaTXAs7/pxDDRredkm1Woo8H4Zo+LiNjTOv1ydlBV7NqJfqIMDyVgOpZN
1msE3Ug3w5FjnZiRZcCdDreXnk4FYlV4rbJFRQTG1zCENH7GARreyI5xWR59QUzB
PnGMHLqUE1FU2KyGoNwxNfnBHdYUHohV7DIC9NI6ucXjbmmbON3PCFPeuUn6jvdu
8qNGGfY6Wv+Vwyg1VKahI/dpI0Vy+n/8AA5lbSb+8Qe6ha+6xSDedN2Y6YNF4J1v
iuVFzG8GvUChMFuVYw8F0vsoR1r02uoErxzi9Qgav6uUGAMYOitPnjd2FJ21l2n+
+P46e6yd9Eq5z6ikmAvbF0qhK2XOWCjVzah2Cjv7frlqLsonVYOD52RMgIKndR/x
WTZCbPQhMR5LutiQMryIrtLsLe1i4AZP4zaeLnupfdijiXwo6dD7/k98CnqUJtQT
1HWrLQb2gdc8aWhqNsn5sg5Lss3hQWvPq6tgLxk/+HshR1/DoqIE4K8bqvaceI5r
meFT8R9y1XBwFu167I1uJIQyvQulrLs0B/VKg6unJM8AHpw326PckYEqHo0TOJUF
XWHFH4MdN1TwpGi9mww=
=5u17
-----END PGP SIGNATURE-----
Merge tag 'v4.15-next-soc' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/soc
Pull "arm: Updates for soc driver for v4.15-next" from Matthias Brugger:
- change kconfig entry for armv7 SoCs to be more generic
- add support for mt2701 scpsys driver
binding documentation
extend driver to allow the bus protection to overwrite the register
* tag 'v4.15-next-soc' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
soc: mediatek: add MT2712 scpsys support
soc: mediatek: add dependent clock jpgdec/audio for scpsys
soc: mediatek: extend bus protection API
dt-bindings: soc: add MT2712 power dt-bindings
ARM: mediatek: use more generic prompts for SoCs with ARMv7
Fuse and chip ID support for Tegra186 is added in this set of changes,
followed by some unification work for the PMC driver in order to avoid
code duplication between Tegra186 and prior chips.
This also contains a couple of fixes for reading fuses on Tegra20.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlo73FITHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoXFYD/9LdBMkXZdG8ftCyKhIrdmT8HoGCVMc
Hq1H4oY1DEwkUGf+98dP+E5M9OqH/s7VzCqzb5OSzkroVplvTVe6x40ZGdAVP6AN
SEsHIJSZ1gssuQdJVqh4mZcz4YdT33qlQ8Y64ur4m7GPwwz8nwWDLcDVufNlPpra
RrcqG+hDj85D61wP/QKmeUgow3eTLfW1rxV6Vu7mj9LrrKXt92qE6JAlGRmRfxxH
XmUa9GoXfHxBu2jGJHotL7TGwUTkSEGk7F78b1g8n9s38cohYNTbOjxdw1468nZY
Y5wwJUNZqY1bJJB6mCEDOqcufsKCZr6yGSvoHZUWC2NeXsOHSzqSZQD6bR9jDygH
TMaCSlYVOw4Rbj5WJPLvbFj5kyhuDx1ATR9xoVBkleX3npu+KtwzQaK8rRtUP81/
yXcSxt4BKAfLAMloR1ycw13yMXAzu7jZhZYCOT61GBsQ45AgCMy5XBwV9TBitIdN
+ScsZ+QZd31Lt6Sq4KEZZHqaKMWqFXezW9GeqmvOE+uVzfA8TLtO8ud5OeP5c6bU
c5oe4Oy3HmjG8HzQErdjr/eBAlONwEBKFw3o4GVNb0R9x20SysqlP91wKDfgBM9k
32ZWTF10QXxebY92WneEjLImJeU/U0iHkmNS4tpQC1Egi7tvqkGGh6HnXVt11hk9
cr4ElWaSu1cuaQ==
=3l9M
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.16-soc-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc
Pull "soc/tegra: Changes for v4.16-rc1" from Thierry Reding:
Fuse and chip ID support for Tegra186 is added in this set of changes,
followed by some unification work for the PMC driver in order to avoid
code duplication between Tegra186 and prior chips.
This also contains a couple of fixes for reading fuses on Tegra20.
* tag 'tegra-for-4.16-soc-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
soc/tegra: fuse: Explicitly request DMA channel from APB DMA driver
soc/tegra: fuse: Fix reading registers using DMA on Tegra20
soc/tegra: pmc: Consolidate Tegra186 support
soc/tegra: pmc: Parameterize driver
soc/tegra: fuse: Add Tegra186 chip ID support
soc/tegra: fuse: Warn if accessing unmapped registers
soc/tegra: fuse: Move register mapping check
soc/tegra: fuse: Add Tegra186 support
dt-bindings: misc: Add Tegra186 MISC registers bindings
Currently fuse driver requests DMA channel from an arbitrary DMA device,
it is not a problem since there is only one DMA provider for Tegra20 yet,
but it may become troublesome if another provider will appear.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
FUSE driver doesn't configure DMA channel properly, because of it DMA
transfer is never issued and tegra20_fuse_read() always return 0x0.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
* Identify R-Car M3-W ES1.1
Geert Uytterhoeven says "The Product Register of R-Car M3-W ES1.1
incorrectly identifies the SoC revision as ES2.0. Add a workaround to
fix this."
It is my understanding that this is likely to be forwards-compatibile.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlonu8cACgkQ189kaWo3
T76hcw//bUQJZvzI1VMIcfdu1KY47lu8GPGgPMyb2ULfuLcpRXG3AzFCzT5HJjBe
BBPoCISEhuh4M6bpWyDs0AVkvJUjrTmiy6FPS1mqllh8rp6xx6v5OM9OP3cPyNzS
ECY8TmPgij4oBbp5e0JvA+SnRp0biR750TXwIHytUtNe0o1R0kpyqo+OUtR79lTe
rQyX4CRrNQozmUTsCiTuWf972jHJW4IInbrEr6PU89MB/WrdAiS6TnKxtDprGMqe
5TzKGxd6UxuX/X7ZGte0+mTW5ur/Jgg2C4mQx6UD3Wp7iJn3geXsdxnwTA9dWi+0
iz8l10/EY2bPBYm3UbiclDuv68uxFy3h+2pTYbguIvHvRqIwwpQzt0/iIwpkoNGN
XDC6g4l4+B97opV+uoNJub2b64ev4gJQ3ugxfZMgQOKWA6FNjABmIpvlQKQzWylp
B5R5fXz/eyhbqtzGcb7Y/7kS+ezO+8pz8WdwGRAQKQ0B/cGHeS3aoA6JaOZXIeN1
nzVmKpeZfCiKGF16v8Ds6cz0QJcQWDHU/WMsPKS2KnHwd0ipp8DtR/F9PX+KNomv
LZiUyJ5ER9g1bVEPm1K2zyQ0LbIfpQsw0xHAD05BEKflep+eleYOFhja/iX4hs+9
n1wbz4GnhKFEG40lwq6Z0kwiKSupJrv9Wzbtb/Yv9SDOVD5Zj9M=
=eL6d
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Pull "Renesas ARM Based SoC Updates for v4.16" from Simon Horman:
* Identify R-Car M3-W ES1.1
Geert Uytterhoeven says "The Product Register of R-Car M3-W ES1.1
incorrectly identifies the SoC revision as ES2.0. Add a workaround to
fix this."
It is my understanding that this is likely to be forwards-compatibile.
* tag 'renesas-soc-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
soc: renesas: Identify R-Car M3-W ES1.1
There are dependent clock jpgdec/audio in scpsys on MT2712,
and will exist three dependent clocks on MT2712 VDEC.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
MT2712 add "set/clear" bus control register to each control register set
instead of providing only one "enable" control register, we could avoid
the read-modify-write racing by declaring "bus_prot_reg_update" as "false"
in scp_soc_data or declaring as "true" to use the legacy update method.
By improving the mtk-infracfg bus protection implementation to
support set/clear bus protection control method by IC configuration.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Being called during early_initcall() is early enough that it occurs
before SMP initialization, which is all we care about for the Bus
Interface Unit configuration.
This solves lack of BIU initialization on ARM64 platforms where we do
not have an anchor where to put the BIU initialization (since there are
no machine descriptors).
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
We may need access to family_id and product_id fairly early on boot for
other parts of the code (e.g: biuctrl.c), so split the initialization
between an early_init() and an arch_initcall() which allows us to do
that.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
