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57b17ae71f
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3 Commits

Author SHA1 Message Date
Thierry Reding
57b17ae71f gpu: host1x: mipi: Registers are 32 bits wide 
On 64-bit platforms an unsigned long would be 64 bit and cause
unnecessary casting when being passed to writel() or returned from
readl(). Make register values 32 bits wide to avoid that.

Signed-off-by: Thierry Reding <treding@nvidia.com>
 2014-11-13 16:11:48 +01:00
Thierry Reding
aef03d3fa5 gpu: host1x: Fix more sparse warnings 
Include the linux/host1x.h and dev.h headers so that function prototypes
are visible to keep sparse from suggesting that their implementations be
made static.

Signed-off-by: Thierry Reding <treding@nvidia.com>
 2013-12-19 09:29:51 +01:00
Thierry Reding
4de6a2d6ac gpu: host1x: Add MIPI pad calibration support 
This driver adds support to perform calibration of the MIPI pads for CSI
and DSI.

Signed-off-by: Thierry Reding <treding@nvidia.com>
 2013-12-19 09:29:43 +01:00