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Commit Graph

5617 Commits

Author SHA1 Message Date
Taniya Das
96dc791d0b clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs
The RCG CFG/M/N/D register base could be at a different offset than
the CMD register, so introduce a cfg_offset to identify the offset
with respect to the CMD RCGR register.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:18:12 -08:00
Vinod Koul
fe6b580ec6 clk: qcom: remove empty lines in clk-rcg.h
Remove the redundant empty lines crept in.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:18:11 -08:00
Gabriel Fernandez
97621d22df clk: stm32mp1: fix bit width of hse_rtc divider
Fix the bit width of the hse rtc divider because it's off by one.

Fixes: 2c87c9d331 ("clk: stm32mp1: add RTC clock")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:22 -08:00
Gabriel Fernandez
f9b76fd24d clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag
The divisor of ethptp_k and ck_hse_rtc clocks is: 'value register
plus one'.
Then CLK_DIVIDER_ALLOW_ZERO flag has no effect and is useless here.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:21 -08:00
Gabriel Fernandez
d3f2e33c87 clk: stm32mp1: fix HSI divider flag
The divider of HSI (clk-hsi-div) is power of two divider.

Fixes: 9bee94e7b7 ("clk: stm32mp1: Introduce STM32MP1 clock driver")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:21 -08:00
Gabriel Fernandez
140fc4e406 clk: stm32mp1: fix mcu divider table
index 8: ck_mcu is divided by 256 (not 512)

Fixes: e51d297e9a ("clk: stm32mp1: add Sub System clocks")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:20 -08:00
Gabriel Fernandez
c488b24f86 clk: stm32mp1: set ck_csi as critical clock
ck_csi is used for IO compensation so it should be
considered as "always-on" and kept on.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:19 -08:00
Gabriel Fernandez
72cfd1ad10 clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks
STM32MP1 clock IP offers lots of Kernel clocks that are shared
by multiple IP's at the same time.
Then boot loader applies a clock tree that allows to use all IP's
at same time and with the maximum of performance.
Not change parents on a change rate on kernel clocks ensures
the integrity of the system.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:18 -08:00
Gabriel Fernandez
749c9e553e clk: stm32mp1: parent clocks update
Fixes parent clock for axi, fdcan, sai and adc12 clocks.

Fixes: e51d297e9a ("clk: stm32mp1: add Sub System clocks")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:13:06 -08:00
Tony Lindgren
5ae51d67ae clk: clk-twl6040: Fix imprecise external abort for pdmclk
I noticed that modprobe clk-twl6040 can fail after a cold boot with:
abe_cm:clk:0010:0: failed to enable
...
Unhandled fault: imprecise external abort (0x1406) at 0xbe896b20

WARNING: CPU: 1 PID: 29 at drivers/clk/clk.c:828 clk_core_disable_lock+0x18/0x24
...
(clk_core_disable_lock) from [<c0123534>] (_disable_clocks+0x18/0x90)
(_disable_clocks) from [<c0124040>] (_idle+0x17c/0x244)
(_idle) from [<c0125ad4>] (omap_hwmod_idle+0x24/0x44)
(omap_hwmod_idle) from [<c053a038>] (sysc_runtime_suspend+0x48/0x108)
(sysc_runtime_suspend) from [<c06084c4>] (__rpm_callback+0x144/0x1d8)
(__rpm_callback) from [<c0608578>] (rpm_callback+0x20/0x80)
(rpm_callback) from [<c0607034>] (rpm_suspend+0x120/0x694)
(rpm_suspend) from [<c0607a78>] (__pm_runtime_idle+0x60/0x84)
(__pm_runtime_idle) from [<c053aaf0>] (sysc_probe+0x874/0xf2c)
(sysc_probe) from [<c05fecd4>] (platform_drv_probe+0x48/0x98)

After searching around for a similar issue, I came across an earlier fix
that never got merged upstream in the Android tree for glass-omap-xrr02.
There is patch "MFD: twl6040-codec: Implement PDMCLK cold temp errata"
by Misael Lopez Cruz <misael.lopez@ti.com>.

Based on my observations, this fix is also needed when cold booting
devices, and not just for deeper idle modes. Since we now have a clock
driver for pdmclk, let's fix the issue in twl6040_pdmclk_prepare().

Cc: Misael Lopez Cruz <misael.lopez@ti.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:11:23 -08:00
Thomas Petazzoni
c0189feead clk: clk-gpio: add support for sleeping GPIOs in gpio-gate-clk
The current implementation of gpio-gate-clk enables/disables the clock
using the GPIO in the ->enable() and ->disable() clock callbacks. This
requires the GPIO to be configurable in atomic contexts. While it is
the case for most memory-mapped GPIO controllers, it is not the case
for GPIO expanders on I2C or SPI.

This commit extends the gpio-gate-clk to check whether the GPIO calls
require sleeping or not. If sleeping is not required, the current
implementation based on ->enable()/->disable() is kept. However, if
sleeping is needed, we instead implement the logic in the ->prepare()
and ->unprepare() hooks. Thanks to this, a gate clock connected to a
GPIO on a GPIO expander can be controlled with the existing driver.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
[sboyd@kernel.org: Mark clk ops static]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 14:05:25 -08:00
David Dai
04053f4d23 clk: qcom: clk-rpmh: Add IPA clock support
The clk-rpmh driver only supports on and off RPMh clock resources. Let's
extend the driver by adding support for clocks that are managed by a
different type of RPMh resource known as Bus Clock Manager(BCM). The BCM
is a configurable shared resource aggregator that scales performance
based on a set of frequency points. The Qualcomm IP Accelerator (IPA)
clock is an example of a resource that is managed by the BCM and this a
requirement from the IPA driver in order to scale its core clock.

Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:57:55 -08:00
Lubomir Rintel
0ea8cbc15d clk: mmp2: separate LCDC peripheral clk form the display clock
These are in fact two clocks, they shouldn't be exposed as one. One is
required for accessing LCD controller registers (peripheral clock), while
other (AXI clock) can be optionally used as a pixel clock source for the
panel.

LCDC can alternatively use different clocks than the Display 1 AXI clock
for generating the pixel clock: the second AXI clock (fixed in this
commit too), the HDMI PLL, or the AXI bus clock.

They should really be controlled independently.

Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:52:02 -08:00
Kunihiko Hayashi
521282237b clk: uniphier: Fix update register for CPU-gear
Need to set the update bit in UNIPHIER_CLK_CPUGEAR_UPD to update
the CPU-gear value.

Fixes: d08f1f0d59 ("clk: uniphier: add CPU-gear change (cpufreq) support")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:50:23 -08:00
Gustavo A. R. Silva
0612fe604d clk: samsung: s3c2443: Mark expected switch fall-through
In preparation to enabling -Wimplicit-fallthrough, mark switch
cases where we are expecting to fall through.

This patch fixes the following warnings:

drivers/clk/samsung/clk-s3c2443.c: In function ‘s3c2443_common_clk_init’:
drivers/clk/samsung/clk-s3c2443.c:390:3: warning: this statement may fall through [-Wimplicit-fallthrough=]
   samsung_clk_register_alias(ctx, s3c2450_aliases,
   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     ARRAY_SIZE(s3c2450_aliases));
     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk-s3c2443.c:393:2: note: here
  case S3C2416:
  ^~~~

Warning level 3 was used: -Wimplicit-fallthrough=3

Notice that, in this particular case,  the code comment is modified
in accordance with what GCC is expecting to find.

This patch is part of the ongoing efforts to enable
-Wimplicit-fallthrough.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:43:49 -08:00
Krzysztof Kozlowski
785c9f411e clk: samsung: exynos5: Fix kfree() of const memory on setting driver_override
Platform driver driver_override field should not be initialized from
const memory because the core later kfree() it.  If driver_override is
manually set later through sysfs, kfree() of old value leads to:

    $ echo "new_value" > /sys/bus/platform/drivers/.../driver_override

    kernel BUG at ../mm/slub.c:3960!
    Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
    ...
    (kfree) from [<c058e8c0>] (platform_set_driver_override+0x84/0xac)
    (platform_set_driver_override) from [<c058e908>] (driver_override_store+0x20/0x34)
    (driver_override_store) from [<c031f778>] (kernfs_fop_write+0x100/0x1dc)
    (kernfs_fop_write) from [<c0296de8>] (__vfs_write+0x2c/0x17c)
    (__vfs_write) from [<c02970c4>] (vfs_write+0xa4/0x188)
    (vfs_write) from [<c02972e8>] (ksys_write+0x4c/0xac)
    (ksys_write) from [<c0101000>] (ret_fast_syscall+0x0/0x28)

The clk-exynos5-subcmu driver uses override only for the purpose of
creating meaningful names for children devices (matching names of power
domains, e.g. DISP, MFC).  The driver_override was not developed for
this purpose so just switch to default names of devices to fix the
issue.

Fixes: b06a532bf1 ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:33:00 -08:00
Krzysztof Kozlowski
5f0b6216ea clk: samsung: exynos5: Fix possible NULL pointer exception on platform_device_alloc() failure
During initialization of subdevices if platform_device_alloc() failed,
returned NULL pointer will be later dereferenced.  Add proper error
paths to exynos5_clk_register_subcmu().  The return value of this
function is still ignored because at this stage of init there is nothing
we can do.

Fixes: b06a532bf1 ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:32:50 -08:00
Fabrizio Castro
e61b30bb34 clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLK
Enum LAST_DT_CORE_CLK needs updating as R8A774C0_CLK_CANFD
was recently added and it's the core clock with the highest
index.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Fixes: 2a6efbc6da ("clk: renesas: r8a774c0: Add missing CANFD clock")
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 13:09:52 -08:00
Abel Vesa
db27e40b27 clk: imx8mq: Add the missing ARM clock
Add the ARM clock as imx_clk_cpu type.
Will be used by cpufreq.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:56:52 -08:00
Abel Vesa
ad18bbf369 clk: imx: imx8mq: Fix the rate propagation for arm pll
The arm pll bypass needs to propagate the rate upwards
in order for the cpufreq to work.

Fixes: b80522040c ("clk: imx: Add clock driver for i.MX8MQ CCM")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:56:52 -08:00
Fabio Estevam
202ce5afe5 clk: imx8mq: Add support for the CLKO1 clock
Add the entry for the CLKO1 clock.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:56:52 -08:00
Fabio Estevam
0bfed63baf clk: imx8mq: Fix the CLKO2 source select list
The CLKO2 clock source select list is the following as per the i.MX8M
Reference Manual:

000 - 25M_REF_CLK
001 - SYSTEM_PLL2_DIV5
010 - SYSTEM_PLL1_DIV2
011 - SYSTEM_PLL2_DIV6
100 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL1_CLK
111 - 32K_REF_CLK

However, in imx8mq_clko2_sels[] only the first four entries are correct.

Fix it by adding the missing "sys3_pll2_out" entry in order to match
the description from the manual.

Fixes: b80522040c ("clk: imx: Add clock driver for i.MX8MQ CCM")
Reported-by: Rogerio Pimentel <rogerio.silva@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:17 -08:00
Carlo Caione
81bf81e7d3 clk: imx8mq: Add missing M4 clocks
The clocks list is missing the clocks for the M4 core.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Bai Ping
ba5625c3e2 clk: imx: Add clock driver support for imx8mm
Add clock driver support for i.MX8MM SOC.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Bai Ping
8646d4dcc7 clk: imx: Add PLLs driver for imx8mm soc
New PLLs are introduced on i.MX8M Mini SOC.
PLL1416X is Integer PLL, PLL1443X is a Frac PLL.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Michael Grzeschik
9b15cffbf2 clk: imx5: add imx5_SCC2_IPG_GATE
This adds the missing clock for the SCC2 peripheral unit.

Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Aisheng Dong
666aed2d13 clk: imx: scu: add set parent support
Add clk scu set parents support.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@kernel.org: Remove le32_to_cpu() on get_parent op]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Aisheng Dong
cd67d32727 clk: imx: scu: add fallback compatible string support
SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs.
Make the driver support "fsl,scu-clk" fallback compatible string
to allow other SoCs to reuse the common part.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Abel Vesa
402564aee0 clk: imx8mq: Make parent names arrays const pointers
The arrays containing the mux selectors need to be of const pointer
to const char.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Abel Vesa
470663e078 clk: imx: Make parents const pointer in mux wrappers
The parents needs to be pointer to const pointer to const char.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Abel Vesa
65a6b7c5f3 clk: imx: Make parent_names const pointer in composite-8m
The parent_names needs to be pointer to const pointer to const char.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21 12:41:16 -08:00
Alexandre Belloni
65a91e2e59 clk: at91: fix masterck name
The master clock is actually named masterck earlier in the driver. Having
"mck" in the parent list means that it can never be selected.

Fixes: 1eabdc2f9d ("clk: at91: add at91sam9x5 PMCs driver")
Fixes: a2038077de ("clk: at91: add sama5d2 PMC driver")
Fixes: 084b696bb5 ("clk: at91: add sama5d4 pmc driver")
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: <stable@vger.kernel.org> # v4.20+
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-20 11:40:21 -08:00
Alexandre Belloni
1b328a2e09 clk: at91: fix at91sam9x5 peripheral clock number
nck() looks at the last id in an array and unfortunately,
at91sam9x35_periphck has a sentinel, hence the id is 0 and the calculated
number of peripheral clocks is 1 instead of a maximum of 31.

Fixes: 1eabdc2f9d ("clk: at91: add at91sam9x5 PMCs driver")
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: <stable@vger.kernel.org> # v4.20+
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-20 11:34:24 -08:00
Wei Yongjun
bb8727096c clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static
Fixes the following sparse warning:

drivers/clk/tegra/clk-tegra124-dfll-fcpu.c:244:18: warning:
 symbol 'tegra210_cpu_cvb_tables' was not declared. Should it be static?

Fixes: 2b2dbc2f94 ("clk: tegra: dfll: add CVB tables for Tegra210")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-18 11:16:22 +01:00
Arnd Bergmann
7e5c4c26c7 clk: tegra: Changes for v5.1-rc1
This contains a couple of prerequisite patches to enable CPU frequency
 scaling on Tegra210.
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Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

clk: tegra: Changes for v5.1-rc1

This contains a couple of prerequisite patches to enable CPU frequency
scaling on Tegra210.

* tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210
  clk: tegra: dfll: add CVB tables for Tegra210
  clk: tegra: dfll: round down voltages based on alignment
  clk: tegra: dfll: support PWM regulator control
  clk: tegra: dfll: CVB calculation alignment with the regulator
  clk: tegra: dfll: registration for multiple SoCs

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15 17:31:41 +01:00
Andreas Kemnade
fddf4e29a6 clk: ti: check clock type before doing autoidle ops
Code might use autoidle api with clocks not being omap2 clocks,
so check if clock type is really omap2.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-02-15 16:47:55 +02:00
Andreas Kemnade
d277ce2d3a clk: ti: add a usecount for autoidle
Multiple users might deny autoidle on a clock. So we should have some
counting here, also according to the comment in  _setup_iclk_autoidle().
Also setting autoidle regs is not atomic, so there is another reason
for locking.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-02-15 16:47:55 +02:00
Tero Kristo
ead478250b clk: ti: generalize the init sequence of clk_hw_omap clocks
Add a generic API for initializing clocks of clk_hw_omap type clocks,
and convert the whole TI clock driver suite to use this for registering
the clocks. Also, get rid of the now redundant API for adding the clocks
to the OMAP HW clocks list; instead this is used directly from the
register API.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
2019-02-15 16:46:22 +02:00
Tero Kristo
8aa09cf322 clk: ti: remove usage of CLK_IS_BASIC
Remove the usage of CLK_IS_BASIC flag completely from TI clock driver.
In most cases, the use is completely redundant, but in some cases
we need to use the new API to check if the clock is an OMAP clock or not.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
2019-02-15 16:46:22 +02:00
Tero Kristo
7fd79ee78a clk: ti: add new API for checking if a provided clock is an OMAP clock
omap2_clk_is_hw_omap can now be used to verify if the provided clk_hw
is an omap HW clock or not. This is done to replace the usage of CLK_IS_BASIC
flag within the TI clock drivers.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
2019-02-15 16:46:21 +02:00
Tero Kristo
77b773aea5 clk: ti: move clk_hw_omap list handling under generic part of the driver
Currently the clk_hw_omap list is handled under the autoidle code, but
it should be accessible generically. Add a few APIs towards this, and
update the autoidle code to use the generic implementations.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Keerthy <j-keerthy@ti.com>
2019-02-15 16:46:21 +02:00
Stephen Boyd
05c3ae7aa1 Allwinner clock fixes for 5.0
Two fixes for clock indices, one for the A31 and one for the V3s.
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Merge tag 'sunxi-clk-fixes-for-5.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

Pull Allwinner clock fixes from Maxime Ripard:

Two fixes for clock indices, one for the A31 and one for the V3s.

* tag 'sunxi-clk-fixes-for-5.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi: A31: Fix wrong AHB gate number
  clk: sunxi-ng: v3s: Fix TCON reset de-assert bit
2019-02-13 09:01:21 -08:00
Martin Blumenstingl
c5f09e6bd8 clk: meson: meson8b: fix the naming of the APB clocks
Fix a typo in the APB clock names by renaming them from "abp" to "apb".
No functional changes.

Fixes: a7d19b05ce ("clk: meson: meson8b: add the CPU clock post divider clocks")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190210222603.6404-2-martin.blumenstingl@googlemail.com
2019-02-13 09:51:09 +01:00
Neil Armstrong
042f01bb7f clk: meson: Add G12A AO Clock + Reset Controller
Add the Amlogic G12A AO Clock and Reset controller driver handling
generation of Always-On clocks :
- AO Clocks and Reset for Always-On modules
- 32K Generation for USB and CEC
- SAR ADC controller clock

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190212162859.20743-3-narmstrong@baylibre.com
2019-02-13 09:49:32 +01:00
Matti Vaittinen
d3236214e7 clk: clk-st: avoid clkdev lookup leak at remove
Use devm based clkdev lookup registration to avoid leaking lookup
structures.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06 10:35:04 -08:00
Matti Vaittinen
8144e1e8ca clk: clk-max77686: Clean clkdev lookup leak and use devm
clk-max77686 never clean clkdev lookup at remove. This can cause
oops if clk-max77686 is removed and inserted again. Fix leak by
using new devm clkdev lookup registration. Simplify also error
path by using new devm_of_clk_add_hw_provider.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06 10:35:03 -08:00
Matti Vaittinen
3eee6c7d11 clkdev: add managed clkdev lookup registration
Clkdev registration lacks of managed registration functions and it
seems few drivers do not drop clkdev lookups at exit. Add
devm_clk_hw_register_clkdev and devm_clk_release_clkdev to ease lookup
releasing at exit.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06 10:35:02 -08:00
Phil Edworthy
60b8f0ddf1 clk: Add (devm_)clk_get_optional() functions
This adds clk_get_optional() and devm_clk_get_optional() functions to get
optional clocks.

They behave the same as (devm_)clk_get() except where there is no clock
producer. In this case, instead of returning -ENOENT, the function
returns NULL. This makes error checking simpler and allows
clk_prepare_enable, etc to be called on the returned reference
without additional checks.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Russell King <linux@armlinux.org.uk>
[sboyd@kernel.org: Document in devres.txt]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06 10:33:10 -08:00
Phil Edworthy
5c56dfe63b clk: Add comment about __of_clk_get_by_name() error values
It's not immediately obvious from the code that failure to get a
clock provider can return either -ENOENT or -EINVAL. Therefore, add
a comment to highlight this.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Russell King <linux@armlinux.org.uk>
[sboyd@kernel.org: Fix comment to be proper C with ==]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-06 10:32:42 -08:00
Peter De Schrijver
8bf9437a4e clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210
Tegra210 has a DFLL as well and can share the majority of the code with
the Tegra124 implementation. So build the same code for both platforms.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06 14:29:37 +01:00
Joseph Lo
2b2dbc2f94 clk: tegra: dfll: add CVB tables for Tegra210
Add CVB tables with different chip characterization, so that we can
generate the customize OPP table that suitable for different chips with
different SKUs.

The parameter 'tune_high_min_millivolts' is first time introduced in
this patch, which didn't use in the DFLL driver for clock and voltage
tuning before. It will be used later when DFLL in high voltage range.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06 14:29:23 +01:00
Joseph Lo
f7ebf8874c clk: tegra: dfll: round down voltages based on alignment
When generating the OPP table, the voltages are round down with the
alignment from the regulator. The alignment should be applied for
voltages look up as well.

Based on the work of Penny Chiu <pchiu@nvidia.com>.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06 14:29:08 +01:00
Joseph Lo
36541f0499 clk: tegra: dfll: support PWM regulator control
The DFLL hardware supports two modes (I2C and PWM) for voltage control
when requesting a frequency. In this patch, we introduce PWM mode support.

To support that, we re-organize the LUT for unifying the table for both
cases of I2C and PWM mode. And generate that based on regulator info.
For the PWM-based regulator, we get this info from DT. And do the same as
the case of I2C LUT, which can help to map the PMIC voltage ID and voltages
that the regulator supported.

The other parts are the support code for initializing the DFLL hardware
to support PWM mode. Also, the register debugfs file is slightly
reworked to only show the i2c registers when I2C mode is in use.

Based on the work of Peter De Schrijver <pdeschrijver@nvidia.com>.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06 14:28:55 +01:00
Joseph Lo
b3cf8d0695 clk: tegra: dfll: CVB calculation alignment with the regulator
The CVB table contains calibration data for the CPU DFLL based on
process characterization. The regulator step and offset parameters depend
on the regulator supplying vdd-cpu, not on the specific Tegra SKU.

When using a PWM controlled regulator, the voltage step and offset are
determined by the regulator type in use. This is specified in DT. When
using an I2C controlled regulator, we can retrieve them from CPU regulator
Then pass this information to the CVB table calculation function.

Based on the work done of "Peter De Schrijver <pdeschrijver@nvidia.com>"
and "Alex Frid <afrid@nvidia.com>".

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06 14:28:41 +01:00
Peter De Schrijver
b0dcfb78dc clk: tegra: dfll: registration for multiple SoCs
In a future patch, support for the DFLL in Tegra210 will be introduced.
This requires support for more than 1 set of CVB and CPU max frequency
tables.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-06 14:28:25 +01:00
Paul Cercueil
b7e29924a1 clk: ingenic: jz4740: Fix gating of UDC clock
The UDC clock is gated when the bit is cleared, not when it is set.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Fixes: 2b555a4b9c ("clk: ingenic: Add missing flag for UDC clock")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-05 13:32:26 -08:00
Weiyi Lu
51ff86dd10 clk: mediatek: update clock driver of MT2712
According to 3rd ECO design change,
1. Add new fixed factor clock of audio.
2. Add the parent clocks for audio clock mux.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-05 13:28:04 -08:00
Biju Das
d1de227de8 clk: renesas: r8a774c0: Add TMU clock
This patch adds the TMU clocks to the R8A774C0 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-02-05 10:40:05 +01:00
Sergei Shtylyov
94e3935b57 clk: renesas: r8a77980: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the R-Car V3H (R8A77980) CPG/MSSR
driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-02-05 10:40:05 +01:00
Sergei Shtylyov
db4a0073cc clk: renesas: rcar-gen3: Add RPC clocks
The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all
the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field
is different between SoCs; it makes sense to support the most common case
of this encoding in the R-Car gen3 CPG driver...

After adding the RPCSRC clock, we can add the RPC[D2] clocks derived from
it and controlled by the RPCCKCR register on all the R-Car gen3 SoCs except
V3M (R8A77970); the composite clock driver seems handy for this task, using
the spinlock added in the previous patch...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-02-05 10:40:05 +01:00
Jerome Brunet
6682bd4d44 clk: meson: factorise meson64 peripheral clock controller drivers
The function used to probe the peripheral clock controller of the arm64
amlogic SoCs is mostly the same. We now have 3 of those controllers so
it is time to factorize things a bit.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201145345.6795-5-jbrunet@baylibre.com
2019-02-04 09:52:11 +01:00
Jian Hu
085a4ea93d clk: meson: g12a: add peripheral clock controller
Add the peripheral clock controller found in the g12a SoC family

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com
2019-02-04 09:52:11 +01:00
Jerome Brunet
8eed1db1ad clk: meson: pll: update driver for the g12a
The g12a use fractional parameter of 17 useful bits. At the moment, this
parameter in encoded using u16 value. Use this opportunity to switch all
the pll to parameter to unsigned int. This should save us some annoying
trouble shooting when and m and n field eventually grow as well.

This patch also introduce pll multiplier range. On the g12a, the hifi and
gp0 plls are able to lock as long as the following condition is met:
55 <= m/n <= 255.

The param table describing this would be huge which is a waste of memory.
Using ranges, we can save memory. Ranges also help find the best pll
parameter significantly faster since we don't have to try all the possible
settings.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[jbrunet: fixed fix pll settings calculation with arm32]
Link: https://lkml.kernel.org/r/20190201145345.6795-2-jbrunet@baylibre.com
2019-02-04 09:51:37 +01:00
Jerome Brunet
889c2b7ec4 clk: meson: rework and clean drivers dependencies
Initially, the meson clock directory only hosted 2 controllers drivers,
for meson8 and gxbb. At the time, both used the same set of clock drivers
so managing the dependencies was not a big concern.

Since this ancient time, entropy did its job, controllers with different
requirement and specific clock drivers have been added. Unfortunately, we
did not do a great job at managing the dependencies between the
controllers and the different clock drivers. Some drivers, such as
clk-phase or vid-pll-div, are compiled even if they are useless on the
target (meson8). As we are adding new controllers, we need to be able to
pick a driver w/o pulling the whole thing.

The patch aims to clean things up by:
* providing a dedicated CONFIG_ for each clock drivers
* allowing clock drivers to be compiled as a modules, if possible
* stating explicitly which drivers are required by each controller.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201125841.26785-5-jbrunet@baylibre.com
2019-02-02 17:43:32 +01:00
Jerome Brunet
cb78ba7629 clk: meson: axg-audio does not require syscon
The axg audio clock controller uses regmap mmio, not syscon.

Fixes: 1cd5018175 ("clk: meson: axg: add the audio clock controller driver")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201125841.26785-4-jbrunet@baylibre.com
2019-02-02 17:43:08 +01:00
Jerome Brunet
6e47b53073 clk: meson: use CONFIG_ARCH_MESON to enter meson clk directory
Use CONFIG_ARCH_MESON to let make enter the meson clock directory.
As part of a rework, CONFIG_COMMON_CLK_AMLOGIC is about to be removed.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201125841.26785-3-jbrunet@baylibre.com
2019-02-02 17:42:50 +01:00
Jerome Brunet
12aa377bf8 clk: export some clk_hw function symbols for module drivers
clk-provider.h provides clk_hw_is_prepared(), clk_hw_is_enabled() and
clk_hw_is_prepared() but these symbols are not exported for the
modules which prevents a clock driver using them to be compiled as
a module. Export them to fix the problem.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190201125841.26785-2-jbrunet@baylibre.com
2019-02-02 17:42:02 +01:00
Kamil Konieczny
81faa30df9 clk: samsung: exynos5433: Add selected IMEM clocks
This patch adds clocks required for the Exynos5433 SoC Slim Security
SubSystem (SlimSSS) IP block.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com>
[s.nawrocki@samsung.com: edited commit description]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-02-01 14:36:47 +01:00
Kamil Konieczny
b80a40c659 clk: samsung: exynos5433: Fix name typo in sssx
Fix typo in sssx name, there should be three letters 's'.

Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-02-01 14:36:47 +01:00
Kamil Konieczny
4e16c9ef2a clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocks
This fixes typos in CLK_ACLK_IMEM_200 and CLK_ACLK_IMEM_266 clock definition,
leading to incorrect parent clock assignment.

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com>
[s.nawrocki@samsung.com: edited commit description]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-02-01 14:36:47 +01:00
Andre Przywara
ee0b27a3a4
clk: sunxi: A31: Fix wrong AHB gate number
According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.

Fix the gate bit definitions in the clock driver.

Fixes: c6e6c96d8f ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-28 09:26:32 +01:00
Sergei Shtylyov
875e8f6b01 clk: renesas: rcar-gen3: Add spinlock
Protect the CPG register read-modify-write sequence with a spinlock.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-01-25 11:26:22 +01:00
Sergei Shtylyov
8cb8f16c62 clk: renesas: rcar-gen3: Factor out cpg_reg_modify()
There's quite often repeated sequence of a CPG register read-modify-write,
so it seems worth factoring it out into a function -- this saves 68 bytes
of the object code (AArch64 gcc 4.8.5) and simplifies protecting all such
sequences with a spinlock in the next patch...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-01-25 11:26:22 +01:00
Chen-Yu Tsai
108a459ef4
clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it
The PLL-MIPI clock is somewhat special as it has its own LDOs which
need to be turned on for this PLL to actually work and output a clock
signal.

Add the 2 LDO enable bits to the gate bits.

Fixes: 5690879d93 ("clk: sunxi-ng: Add A23 CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-25 10:43:44 +01:00
Matteo Croce
463a554baa clk: samsung: fix typo
Fix spelling mistake: "lenght" -> "length"

Signed-off-by: Matteo Croce <mcroce@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 14:17:53 -08:00
Taniya Das
9ff1a3b491 clk: qcom: gcc: Use active only source for CPUSS clocks
The clocks of the CPUSS such as "gcc_cpuss_ahb_clk_src" is a CRITICAL
clock and needs to vote on the active only source of XO, so as to keep
the vote as long as CPUSS is active. Similar rbcpr_clk_src is also has
the same requirement.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Fixes: 06391eddb6 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 11:41:48 -08:00
Gustavo A. R. Silva
921e88a4f9 clk: imx: imx7ulp: use struct_size() in kzalloc()
One of the more common cases of allocation size calculations is finding
the size of a structure that has a zero-sized array at the end, along
with memory for some number of elements for that array. For example:

struct foo {
    int stuff;
    void *entry[];
};

instance = kzalloc(sizeof(struct foo) + sizeof(void *) * count, GFP_KERNEL);

Instead of leaving these open-coded and prone to type mistakes, we can
now use the new struct_size() helper:

instance = kzalloc(struct_size(instance, entry, count), GFP_KERNEL);

This issue was detected with the help of Coccinelle.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 11:37:46 -08:00
Stephen Boyd
a30a67be7b clk: socfpga: Don't have get_parent for single parent ops
This driver creates a gate clk with the possibility to have multiple
parents. That can cause problems if the common clk framework tries to
call the get_parent() op and gets back a number that's larger than the
number of parents the clk says it supports in
clk_init_data::num_parents. Let's duplicate the clk_ops structure each
time this function is called and drop the get/set parent ops when there
is only one parent. This allows the framework to consider a number
larger than clk_init_data::num_parents as an error condition of the
get_parent() clk op, clearing the way for proper code.

Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 11:36:25 -08:00
Dan Carpenter
303aef8b84 clk: ti: Fix error handling in ti_clk_parse_divider_data()
The ti_clk_parse_divider_data() function is only called from
_get_div_table_from_setup().  That function doesn't look at the return
value but instead looks at the "*table" pointer.  In this case, if the
kcalloc() fails then *table is NULL (which means success).  It should
instead be an error pointer.

The ti_clk_parse_divider_data() function has two callers.  One checks
for errors and the other doesn't.  I have fixed it so now both handle
errors.

Fixes: 4f6be5655d ("clk: ti: divider: add driver internal API for parsing divider data")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 11:23:32 -08:00
Abel Vesa
a64a9c088b clk: imx: Fix fractional clock set rate computation
Before multiplying by PLL_FRAC_DENOM, the temp64 needs to be
 temp64 = rate * 2 - divfi * parent_rate * 8, instead of:
 temp64 = (rate * 2 - divfi) * parent_rate

Fixes: 6209624b9a ("clk: imx: Add fractional PLL output clock")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 11:17:28 -08:00
Derek Basehore
ede7785847 clk: Remove global clk traversal on fetch parent index
It's not required to traverse the entire clk tree when the parents array
contains a NULL value. We already have the parent clk_core pointer, so
we can just compare the parent->name and parent_names[i] pointers.

This can be a substantial power improvement in cases where the parent
clk isn't known and that clk is never registered, because a mux having
an unregistered parent name may traverse the clk tree on every
clk_set_rate() call in clk_mux_determine_rate_flags(). This can happen
hundreds of times a second for CPU clks.

This patch is the combination of reverting commit 470b5e2f97 ("clk:
simplify clk_fetch_parent_index() function") and optimizing the
resulting code to never call __clk_lookup() because we already have the
clk_core pointer we're looking for. That optimization went unnoticed
even after commit da0f0b2c3a ("clk: Correct lookup logic in
clk_fetch_parent_index()") tried to optimize this path.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
[sboyd@kernel.org: More description in commit text]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 11:13:28 -08:00
Lubomir Rintel
0acb69e7b9 Revert "clk: mmp2: add SP clock"
It seems that the kernel has no business managing this clock: once the SP
clock is disabled, it's not sufficient to just enable in order to bring the
SP core back up. Just let the firmware keep it enabled and don't expose it
to drivers.

This reverts commit fc27c2394d.

Link: https://lore.kernel.org/lkml/154783267051.169631.3197836544646625747@swboyd.mtv.corp.google.com/
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24 10:55:32 -08:00
Geert Uytterhoeven
d9286d9743 clk: renesas: r8a774c0: Correct parent clock of DU
According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
the parent clock of the DU module clocks on RZ/G2E is S1D1.

Fixes: 906e0a4a6d ("clk: renesas: cpg-mssr: Add r8a774c0 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-01-24 16:01:08 +01:00
Paul Kocialkowski
5c59801f70
clk: sunxi-ng: v3s: Fix TCON reset de-assert bit
According to the datasheet and the reference code from Allwinner, the
bit used to de-assert the TCON reset is bit 4, not bit 3.

Fix it in the V3s CCU driver.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-22 10:03:04 +01:00
Fabrizio Castro
9d034e151b clk: renesas: r8a774a1: Add missing CANFD clock
This patch adds the missing CANFD clock to the r8a774a1 specific
clock driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-01-21 14:01:57 +01:00
Fabrizio Castro
2a6efbc6da clk: renesas: r8a774c0: Add missing CANFD clock
This patch adds the missing CANFD clock to the r8a774c0 specific
clock driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-01-21 13:50:40 +01:00
Jerome Brunet
439a6bb5bf clk: meson: ao-clkc: claim clock controller input clocks from DT
Instead of relying on a fixed names for the differents input clocks
of the controller, get them through DT.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190116175435.4990-4-jbrunet@baylibre.com
2019-01-18 10:51:39 +01:00
Jerome Brunet
6e73dac707 clk: meson: axg: claim clock controller input clock from DT
Instead of relying on a fixed name for the xtal clock, claim the
controller input clock trough DT.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190116175435.4990-3-jbrunet@baylibre.com
2019-01-18 10:51:14 +01:00
Jerome Brunet
c0e6f5bf76 clk: meson: gxbb: claim clock controller input clock from DT
Instead of relying on a fixed name for the xtal clock, claim the
controller input clock trough DT.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190116175435.4990-2-jbrunet@baylibre.com
2019-01-18 10:49:26 +01:00
Dinh Nguyen
b488517b28 clk: socfpga: stratix10: fix naming convention for the fixed-clocks
The fixed clocks in the DTS file have a hyphen, but the clock driver has
the fixed clocks using underbar. Thus the clock driver cannot detect the
other fixed clocks correctly. Change the fixed clock names to a hyphen.

Fixes: 07afb8db73 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-15 12:58:38 -08:00
Dinh Nguyen
c0a636e4cc clk: socfpga: stratix10: fix rate calculation for pll clocks
The main PLL calculation has a mistake. We should be using the
multiplying the VCO frequency, not the parent clock frequency.

Fixes: 07afb8db73 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-11 15:41:02 -08:00
Marc Gonzalez
83b4c14796 clk: qcom: Select QCOM_GDSC with MSM_GCC_8998
If QCOM_GDSC is disabled, gdsc_register() returns -ENOSYS, which causes
gcc_msm8998_probe() to fail. Select QCOM_GDSC to solve the problem.

gcc-msm8998: probe of 100000.clock-controller failed with error -38

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Fixes: b5f5f525c5 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-11 10:39:15 -08:00
Alexander Shiyan
31cc9e0968 clk: clps711x: Remove board support
Since board support for the CLPS711X platform was removed,
remove the board support from the clk-clps711x driver.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 12:50:21 -08:00
Michał Mirosław
77977b8004 clk: at91: enable AUDIOPLL as source for PCKx on SAMA5D2
Datasheet for SAMA5D2x mentions 6 sources for PCKx, the last being AUDIOPLL.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 11:49:35 -08:00
Jeffrey Hugo
6131dc8121 clk: qcom: smd: Add support for MSM8998 rpm clocks
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.

Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 11:46:42 -08:00
Jan Kotas
50cc4caf53 clk: Add Fixed MMIO clock driver
This patch adds a driver for Fixed MMIO clock.
The driver reads a clock frequency value from a single 32-bit memory
mapped register and registers it as a fixed rate clock.

It can be enabled with COMMON_CLK_FIXED_MMIO Kconfig option.

Signed-off-by: Jan Kotas <jank@cadence.com>
[sboyd@kernel.org: Make of_fixed_mmio_clk_setup() static, use clk_hw
based APIs]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 11:41:19 -08:00
Jeffrey Hugo
5f2420ed21 clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998
The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by
the phy during init.  The clock needs to be enabled during the init
sequence, but may not be fully active until after the init sequence is
complete.  This causes a catch-22 if the clock status is checked during
enable.  As a result, skip the checks to avoid the troubling situation.

Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:57:29 -08:00
Jeffrey Hugo
0c8ff62504 clk: qcom: Add missing freq for usb30_master_clk on 8998
The usb30_master_clk supports a 60Mhz frequency, but that is missing from
the table of supported frequencies.  Add it.

Fixes: b5f5f525c5 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver)
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:57:26 -08:00
Jeffrey Hugo
26fe27d920 clk: qcom: Add CLK_SET_RATE_PARENT for 8998 branch clocks
A branch clock is basically a clock that can be gated for power savings,
but is also what devices/drivers consume.  Configuring a branch clock's
rate needs to be done at the source, so for all branch clocks which have
a defined parent, set CLK_SET_RATE_PARENT so that clk_set_rate() calls on
branch clocks can do what is expected.  This is important as most drivers
do not check the resulting clock rate after a successful clk_set_rate()
call, thus the driver may get out of sync with the actual hardware state
and weird issues might crop up.  This has been observed with issues
getting SDHCI to reliably support "fast" cards such as SDR104.

Fixes: 4807c71cc6 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:57:22 -08:00
Marek Vasut
2137a109a5 clk: vc5: Abort clock configuration without upstream clock
In case the upstream clock are not set, which can happen in case the
VC5 has no valid upstream clock, the $src variable is used uninited
by regmap_update_bits(). Check for this condition and return -EINVAL
in such case.

Note that in case the VC5 has no valid upstream clock, the VC5 can
not operate correctly. That is a hardware property of the VC5. The
internal oscilator present in some VC5 models is also considered
upstream clock.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-renesas-soc@vger.kernel.org
[sboyd@kernel.org: Added comment about probe preventing this from
happening in the first place]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09 10:53:58 -08:00