On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks
(modelled as NKMP with no K) and have fixed post-dividers.
Add fixed post divider support to the NKMP style clocks.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
When parent rate is 24MHz and multiplier N >= 180, intermediate clock
rate doesn't fit in 32 bit variable anymore.
Because of that, introduce function for calculating clock rate which
uses 64 bit variable for intermediate result.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Currently, if one of the factors isn't present, bit 0 gets always set to
1. For example, A83T has NMP PLLs modelled as NKMP PLL without K. Since
K is not specified, it's offset, width and shift is 0. Driver assumes
that lowest value possible is 1, otherwise we would get division by 0.
That situation causes that bit 0 is always set, which may change wanted
clock rate.
Fix that by masking every factor according to it's specified width.
Factors with width set to 0 won't have any influence to final register
value.
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
A few minor bug and comment fixes, plus some fixes for the PRCM CCU driver
merged in the prior pull request
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY+G2RAAoJEBx+YmzsjxAgIgoP/jkK2DQ7SfrS60dFSSu8zllD
wm2mBmcmU+qnkMkc5YWls/5Wfq37K4TZrA1/ZJUr9QsWj89iafmmHQVpWV3/2LpK
3afV9FjRRZONhy9ThRj+DCZg9WSvo73VSNrOXiZKTEVufi8crKCcG2g59p86KyfO
obTE7Lrl72wqRE+j+KNnIBiCj+rVE6vGrGY5p2ZE/N8VecveJ8Zje03lNL1Jyj+Z
+rLkQCk4j2DKAKUaaIf+NMQ7L5iT7ePkFPP/yFa3/mpd1Emqp5Kq3cIDxV4Zh+c/
DwtMBqGbabSvHFeokK9IvEYuTdQidREN/R7uWSLgcWcr1om6es7FD41pVF0FIaAN
AYgRfIR3RTOXFbPJt8YQrvV/Xg7yQRweEqlKI6sAC4lVI9yzKQAdAoXTM50AotYS
jB0inoNXg07oQxXrcBaFlcKwsIFOS8k9YWH6NXbofi9/FBswuafgXcZxXKoaNDDU
K+q2bMG2qlMKTgDV44B8ylbdQISCIrPfreqGkYLRfmZx6iPq79nwdd2Wp+GDZ8sk
jX+a8UFVdP9194Xk9ZGA/BGIgRTz1OeJtQH2mWmLheGoQjL2lcdriCtUQ+35Yuzd
caONPr38gvmoixKaWdlqwdurmWvEy8xMvN+r+G9BM855yZMh4ue372xQbGTG4h+d
sOU4mINfk9z8cZ5UgMdx
=Gi2w
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into HEAD
Pull Allwinner clock changes, take 2 from Maxime Ripard:
A few minor bug and comment fixes, plus some fixes for the PRCM CCU driver
merged in the prior pull request
* tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code
clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch
clk: sunxi-ng: use 1 as fallback for minimum multiplier
clk: sunxi-ng: fix PRCM CCU CLK_NUMBER value
clk: sunxi-ng: fix PRCM CCU ir clk parent
In commit 2beaa601c8 ("clk: sunxi-ng: Implement minimum for
multipliers"), the multiplier minimums in the set_rate callback
for NM and NKMP style clocks were not updated.
This patch fixes them to match their round_rate callbacks.
Fixes: 2beaa601c8 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
A zero multiplier does not make sense for clocks.
Use 1 as the minimum when a multiplier minimum isn't specified.
Fixes: 2beaa601c8 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
In commit e66f81bbd7 ("clk: sunxi-ng: Implement factors offsets"), the
final formula of NKMP clocks' recalc_rate is refactored; however, the
refactored formula broke the calculation due to some C language operand
priority problem -- the priority of operand >> is lower than * and /,
makes the formula being parsed as "(parent_rate * n * k) >> (p / m)", but
it should be "(parent_rate * n * k >> p) / m".
Add the pair of parentheses to fix up this issue. This pair of
parentheses used to exist in the old formula.
Fixes: e66f81bbd7 ("clk: sunxi-ng: Implement factors offsets")
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Some multipliers have a maximum rate that is lower than what the register
width allows to. Add a field in the multiplier structure to allow CCU
driver to set that maximum.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The factors we've seen so far all had an offset of one. However, on the
earlier Allwinner SoCs, some factors could have no offset at all, meaning
that the value computed to reach the rate we want to use was the one we had
to program in the registers.
Implement an additional field for the factors that can have such an offset
(linears, not based on a power of two) to specify that offset.
This offset is not linked to the extremums that can be specified in those
structures too. The minimum and maximum are representing the range of
values we can use to try to compute the best rate. The offset comes later
on when we want to set the best value in the registers.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Allow the CCU drivers to specify a multiplier for their clocks.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Modify the current clocks we have to be able to specify the minimum for
each clocks we support, just like we support the max.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
While the rational library works great, it doesn't really allow us to add
more constraints, like the minimum.
Remove that in order to be able to deal with the constraints we'll need.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Some dividers might have a maximum value that is lower than the width of
the register.
Add a field to _ccu_div to handle those case properly. If the field is set
to 0, the code will assume that the maximum value is the maximum one that
can be used with the field register width.
Otherwise, we'll use whatever value has been set.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Introduce support for clocks that use a combination of two linear
multipliers (N and K factors), one linear divider (M) and one power of two
divider (P).
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-13-maxime.ripard@free-electrons.com
