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Author SHA1 Message Date
Alban Bedel
1da2f213cf dt-bindings: Misc fix for the ATH79 DDR controllers 
Fix a few typos and reword the description of the
'#qca,ddr-wb-channel-cells' property.

Signed-off-by: Alban Bedel <albeu@free.fr>
CC: trivial@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
 2015-12-09 15:30:55 -06:00
Alban Bedel
d25b4f65bf DEVICETREE: Add bindings for the ATH79 DDR controllers 
The DDR controller of the ARxxx and AR9xxx families provides an
interface to flush the FIFO between various devices and the DDR.
This is mainly used by the IRQ controller to flush the FIFO before
running the interrupt handler of such devices.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2015-06-21 21:54:02 +02:00