3 Commits

Author	SHA1	Message	Date
Seungwon Jeon	f7b7868ced	PCI: designware: Drop "addr" arg from dw_pcie_readl_rc()/dw_pcie_writel_rc() ... The "dbi_addr" argument to dw_pcie_readl_rc() and dw_pcie_writel_rc() is redundant and misleading because we always have the "struct pcie_port" and we always want to use the address from there. This patch removes the argument and changes the callers to match. No functional change. [bhelgaas: changelog] Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com>	2013-08-29 13:38:12 -06:00
Jingoo Han	4b1ced841b	PCI: exynos: Split into Synopsys part and Exynos part ... Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys Designware part; other parts are Exynos specific. Also, the Synopsys Designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys Designware part and Exynos specific part. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com>	2013-08-12 12:18:20 -06:00
Jingoo Han	340cba6092	pci: Add PCIe driver for Samsung Exynos ... Exynos5440 has a PCIe controller which can be used as Root Complex. This driver supports a PCIe controller as Root Complex mode. Signed-off-by: Surendranath Gurivireddy Balla <suren.reddy@samsung.com> Signed-off-by: Siva Reddy Kallam <siva.kallam@samsung.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2013-06-26 20:14:59 +02:00