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Commit Graph

10 Commits

Author SHA1 Message Date
Aditya Pakki
906b40b246 dmaengine: stm32-mdma: Add a check on read_u32_array
In stm32_mdma_probe, after reading the property "st,ahb-addr-masks", the
second call is not checked for failure. This time of check to time of use
case of "count" error is sent upstream.

Signed-off-by: Aditya Pakki <pakki001@umn.edu>
Acked-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-01-07 09:52:24 +05:30
Huang Shijie
42f604b651 dmaengine: stm32-mdma: use dmaenginem_async_device_register to simplify the code
Use dmaenginem_async_device_register to simplify the code:
	remove dma_async_device_unregister.

Acked-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Huang Shijie <sjhuang@iluvatar.ai>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-08-29 21:43:17 +05:30
Benjamin Gaignard
90ec93cb6b dmaengine: stm32: replace "%p" with "%pK"
The format specifier "%p" can leak kernel addresses.
Use "%pK" instead.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-09 23:01:57 +05:30
Colin Ian King
d317d32b4f dmaengine: stm32-mdma: fix spelling mistake: "avalaible" -> "available"
Trivial fix to spelling mistake in dev_err error message text and make
channel plural.

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-05-02 09:57:37 +05:30
Pierre-Yves MORDRET
bbb5a4e1e7 dmaengine: stm32-mdma: Fix incomplete Hw descriptors allocator
Only 1 Hw Descriptor is allocated. Loop over required Hw descriptor for
proper allocation.

Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-04-25 14:39:53 +05:30
Pierre-Yves MORDRET
ee6de9ac52 dmaengine: stm32-mdma: align TLEN and buffer length on burst
Both buffer Transfer Length (TLEN if any) and transfer size have to be
aligned on burst size (burst beats*bus width).

Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-04-25 14:39:53 +05:30
Pierre-Yves MORDRET
d83f4131c2 dmaengine: stm32_mdma: activate pack/unpack feature
If source and destination bus width differs pack/unpack MDMA
feature has to be activated for alignment.
This pack/unpack feature implies to have both source/destination address
and buffer length aligned on bus width.

Fixes: a4ffb13c89 ("dmaengine: Add STM32 MDMA driver")
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-11-08 10:49:53 +05:30
Colin Ian King
f2fd4d9f32 dmaengine: stm32: remove redundant initialization of hwdesc
hwdesc is being initialized to desc->hwdesc but this is never read
as hwdesc is overwritten in a for-loop.  Remove the redundant
initialization and move the declaration of hwdesc into the for-loop.

Cleans up clang warning:
Value stored to 'hwdesc' during its initialization is never read

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Acked-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-10-12 19:34:41 +05:30
Vinod Koul
38502f232e dmaengine: stm32: use %p format specfier for pointer
Pointer print was using explict cast and printing as %x which causes below
warn on some arch's so print using %p format specfier.

Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-10-08 20:28:15 +05:30
Pierre-Yves MORDRET
a4ffb13c89 dmaengine: Add STM32 MDMA driver
This patch adds the driver for the STM32 MDMA controller.

Master Direct memory access (MDMA) is used in order to provide high-speed
data transfer between memory and memory or between peripherals and memory.

MDMA controller provides a master AXI interface for main memory and
peripheral registers access (system access port) and a master AHB
interface only for Cortex-M7 TCM memory access (TCM access port).

MDMA works in conjunction with the standard DMA controllers (DMA1 or DMA2).
It offers up to 64 channels, each dedicated to managing memory access
requests from one of the DMA stream memory buffer or other peripherals
(w/ integrated FIFO).

Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-10-08 14:45:34 +05:30