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Commit Graph

34 Commits

Author SHA1 Message Date
Philipp Zabel
cdbeb315ed reset: socfpga: declare socfpga_reset_init in a header file
Avoid declaring extern functions in c files. To make sure function
definition and usage don't get out of sync, declare socfpga_reset_init
in a common header.

Suggested-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
2019-01-28 11:16:04 +01:00
Dinh Nguyen
b3ca9888f3 reset: socfpga: add an early reset driver for SoCFPGA
Create a separate reset driver that uses the reset operations in
reset-simple. The reset driver for the SoCFPGA platform needs to
register early in order to be able bring online timers that needed
early in the kernel bootup.

We do not need this early reset driver for Stratix10, because on
arm64, Linux does not need the timers are that in reset. Linux is
able to run just fine with the internal armv8 timer. Thus, we use
a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform.
The Stratix10 platform will continue to use the reset-simple platform
driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use
the early reset driver.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
[p.zabel@pengutronix.de: fixed socfpga of_device_id in reset-simple]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2019-01-07 16:38:50 +01:00
Clément Péron
48e2bab90d ARM: socfpga: Clean unused functions
These functions are unused externally, removed them and declare
the one used locally as static.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28 09:19:21 -06:00
Thor Thayer
c5fb04cc96 ARM: socfpga: Initialize Arria10 OCRAM ECC on startup
Initialize ECC for Arria10 On-Chip RAM on machine startup. The OCRAM
memory must be initialized before data is stored in memory otherwise the
ECC will fail on reads. The previous check-in

  2364d423a7 ("ARM: socfpga: Enable Arria10 OCRAM ECC on startup")

added the OCRAM enable and initialization code but was not called on
startup.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1460394094-23326-1-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2016-04-23 19:22:22 +02:00
Thor Thayer
ff6fd1478c ARM: socfpga: Enable Arria10 L2 cache ECC on startup
Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be
enabled before data is stored in memory otherwise the ECC will fail on
reads.

Use DT_MACHINE to select Arria10 L2 cache function.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1458576106-24505-9-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2016-03-29 10:42:34 +02:00
Thor Thayer
7cc5a5d3cd ARM: socfpga: Enable OCRAM ECC on startup
Enable ECC for On-Chip RAM on machine startup. The ECC has to be enabled
before data is stored in memory otherwise the ECC will fail on reads.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: dougthompson@xmission.com
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-doc@vger.kernel.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: mark.rutland@arm.com
Cc: m.chehab@samsung.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: Russell King <linux@arm.linux.org.uk>
Cc: tthayer.linux@gmail.com
Cc: tthayer@opensource.altera.com
Link: http://lkml.kernel.org/r/1455132384-17108-4-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2016-02-11 12:34:38 +01:00
Thor Thayer
4d1138380e ARM: socfpga: Enable L2 cache ECC on startup
Enable ECC for L2 cache on machine startup. The ECC has to be enabled
before data is stored in memory otherwise the ECC will fail on reads.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-doc@vger.kernel.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: mark.rutland@arm.com
Cc: m.chehab@samsung.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: Russell King <linux@arm.linux.org.uk>
Link: http://lkml.kernel.org/r/1455132384-17108-3-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2016-02-11 12:32:11 +01:00
Dinh Nguyen
cd871d517d ARM: socfpga: add reset for the Arria 10 platform
Since the Arria10's reset register offset is different from the Cyclone/Arria 5,
it's best to add a new DT_MACHINE_START() for the Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: use altera_a10_dt_match for the A10 machine desc
2015-07-20 15:44:43 -05:00
Alan Tull
44fd8c7d40 ARM: socfpga: support suspend to ram
Add code that requests that the sdr controller go into
self-refresh mode.  This code is run from ocram.

Suspend-to-RAM and EDAC support are mutually exclusive on
SOCFPGA.  If the EDAC is enabled, it will prevent the
platform from going into suspend.

Example of how to request to suspend to ram:
 $ echo enabled > \
/sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup

 $ echo -n mem > /sys/power/state

Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-10 16:02:11 -07:00
Dinh Nguyen
5f763ef80d ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
Convert cyclone5/arria5 to use CPU_METHOD_OF_DECLARE for smp operations.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-10 15:35:34 -07:00
Dinh Nguyen
122694a0c7 ARM: socfpga: use of_iomap to map the SCU
Use of_iomap to map the "arm,cortex-a9-scu". By doing this, we can remove
map_io in socfpga.c.

Also, we can remove socfpga_smp_init_cpus, as arm_dt_init_cpu_maps is
already doing the CPU mapping.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-13 08:41:35 -05:00
Dinh Nguyen
65ce7a37ec ARM: socfpga: remove the need to map uart_io_desc
All the necessary debug uart mapping is already being done in
debug_ll_io_init, there's no need for it here.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:59:53 -05:00
Russell King
cee9b8d6b8 ARM: socfpga: make sure socfpga_cpu1start_addr is properly flushed
Make sure socfpga_cpu1start_addr is properly flushed from it's cache line so
that secondary cpu's can see it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-04 13:03:17 -06:00
Dinh Nguyen
3a4356c0c0 arm: socfpga: fix fetching cpu1start_addr for SMP
When CPU1 is brought out of reset, it's MMU is not turned on yet, so it will
only be able to use physical addresses. For systems with that have the
MMU page configured for 0xC0000000, 0x80000000, or 0x40000000
"BIC 0x40000000" will work just fine, as it was just converting the
virtual address of &cpu1start_addr into a physical address, ie. 0xC0000000
became 0x80000000. So for systems where the SDRAM controller was able to do a
wrap-around access, this was working fine, as it was just dropping the MSB,
but for systems where out of bounds memory access is not allowed, this would
not allow CPU1 to correctly fetch &cpu1start_addr.

This patch fixes the secondary_trampoline code to correctly fetch the
physical address of cpu1start_addr directly. The patch will subtract the
correct PAGE_OFFSET from &cpu1start_addr. And since on this platform, the
physical memory will always start at 0x0, subtracting PAGE_OFFSET from
&cpu1start_addr will allow CPU1 to correctly fetch the value of cpu1start_addr.

While at it, change the name of cpu1start_addr to socfpga_cpu1start_addr
to avoid any future naming collisions for multiplatform image.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v4: Updated commit log to correctly lay out the usage of PAGE_OFFSET and
    add comments to the same effect.
v3: Used PAGE_OFFSET to get the physical address
v2: Correctly get the physical address instead of just a BIC hack.
2014-10-21 14:04:14 -05:00
Russell King
8b5c18f056 ARM: l2c: socfpga: convert to generic l2c OF initialisation
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:50:04 +01:00
Russell King
d453ef752c ARM: l2c: remove unnecessary UL-suffix to mask values
They're u32, they're not unsigned long.  The UL suffix is not required
here.

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-22 16:38:43 +01:00
Dinh Nguyen
77f1057777 clk: socfpga: Remove socfpga_init_clocks
The only thing that socfpga_init_clocks was doing is setting up the smp_twd clk.
Now that twd-timer's clock phandle is populated in the DTS, we can remove
this function.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-02-18 14:08:09 -08:00
Dinh Nguyen
6a7e71221d clk: socfpga: Map the clk manager base address in the clock driver
The clk manager's base address was being mapped in SOCFPGA's arch code and
being extern'ed out to the clock driver. This method is not correct, and the
arch code was not really doing anything with that clk manager anyways.

This patch moves the mapping of the clk manager's base address in the clock
driver itself. Cleans up CLK_OF_DECLARE() into a single registration of all
the clocks.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
v2: Use a static declaration for the clk_mgr_base_addr. Clean up the
    CLK_OF_DECLARE() as suggested by Arnd.
2014-02-18 14:08:07 -08:00
Sebastian Hesselbarth
dc8105817f ARM: socfpga: remove custom .init_time hook
With arch/arm calling of_clk_init(NULL) from time_init(), we can now
remove custom .init_time hooks.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
2013-09-29 21:09:41 +02:00
Sebastian Hesselbarth
8e7b25f1aa ARM: socfgpa: prepare for arch-wide .init_time callback
Current socfpga board init calls of_clk_init() from .machine_init. To
allow consolidation of DT driven .time_init, move of_clock_init() to
a temporary .time_init that will be removed when arch-wide callback is
available.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
2013-09-29 21:07:14 +02:00
Robin Holt
7b6d864b48 reboot: arm: change reboot_mode to use enum reboot_mode
Preparing to move the parsing of reboot= to generic kernel code forces
the change in reboot_mode handling to use the enum.

[akpm@linux-foundation.org: fix arch/arm/mach-socfpga/socfpga.c]
Signed-off-by: Robin Holt <holt@sgi.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Russ Anderson <rja@sgi.com>
Cc: Robin Holt <holt@sgi.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-07-09 10:33:29 -07:00
Heiko Stuebner
1002148899 clocksource: dw_apb_timer_of: use clocksource_of_init
dw_apb_timer_init used to search the devicetree for matching timer
devices, making calls to it from board files necessary.

Change the dw_apb_timer_init to work with CLOCKSOURCE_OF_DECLARE.
With this change the function gets called once for each timer node
and tracks these number of calls to attach clockevent and clocksource
devices to the nodes.

Also remove the calls to dw_apb_timer_init from all previous users, as
clocksource_of_init is the default for init_time now.

Tested on the upcoming rk3066 code.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
2013-06-12 13:47:38 +02:00
Dinh Nguyen
56c5c13f70 ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries
With this patch, the socfpga clk driver is able to query the clock and clock
rates appropriately.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-14 20:18:13 -07:00
Dinh Nguyen
5c04b57fe3 ARM: socfpga: Enable soft reset
Enable a cold or warm reset to the HW from userspace.

Also fix a few sparse errors:

warning: symbol 'sys_manager_base_addr' was not declared. Should it be static?
warning: symbol 'rst_manager_base_addr' was not declared. Should it be static?

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-14 20:17:33 -07:00
Olof Johansson
1c75c42100 Merge branch 'socfpga/hw' into next/soc
From Dinh Nguyen, this is a series of patches introducing support for
socfpga hardware (Altera Cyclone5). It also includes a cleanup that
moves some of the ARMv7 cache maintenance functions to a common location,
since three other platforms aready implemented it separately.

* socfpga/hw:
  arm: socfpga: Add SMP support for actual socfpga harware
  arm: Add v7_invalidate_l1 to cache-v7.S
  arm: socfpga: Add entries to enable make dtbs socfpga
  arm: socfpga: Add new device tree source for actual socfpga HW

Trivial conflict in arch/arm/mach-tegra/headsmp.S.

Signed-off-by: Olof Johansson <olof@lixom.net>
2013-02-11 19:37:51 -08:00
Dinh Nguyen
d6dd735f4b arm: socfpga: Add SMP support for actual socfpga harware
Because the CPU1 start address is different for socfpga-vt and
socfpga-cyclone5, we add code to use the correct CPU1 start addr.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Pavel Machek <pavel@denx.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-02-11 19:37:26 -08:00
Dinh Nguyen
c2ad284412 arm: socfpga: Add new device tree source for actual socfpga HW
Up to this point, support for socfpga has only been on a virtual
platform. Now that actual hardware is available, we add the appropriate
device tree source files.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Tested-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Pavel Machek <pavel@denx.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-02-11 19:37:19 -08:00
Olof Johansson
f8060f5446 Initial irqchip init infrastructure and GIC and VIC clean-ups
This creates irqchip initialization infrastructure from Thomas
 Petazzoni. The VIC and GIC irqchip code is moved to drivers/irqchips
 and adapted to use the new infrastructure. All DT enabled platforms
 using GIC and VIC are converted over to use the new irqchip_init.
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Merge tag 'gic-vic-to-irqchip' of git://sources.calxeda.com/kernel/linux into next/cleanup

From Rob Herring:

Initial irqchip init infrastructure and GIC and VIC clean-ups

This creates irqchip initialization infrastructure from Thomas
Petazzoni. The VIC and GIC irqchip code is moved to drivers/irqchips
and adapted to use the new infrastructure. All DT enabled platforms
using GIC and VIC are converted over to use the new irqchip_init.

* tag 'gic-vic-to-irqchip' of git://sources.calxeda.com/kernel/linux:
  irqchip: Move ARM vic.h to include/linux/irqchip/arm-vic.h
  ARM: picoxcell: use common irqchip_init function
  ARM: spear: use common irqchip_init function
  irqchip: Move ARM VIC to drivers/irqchip
  ARM: samsung: remove unused tick.h
  ARM: remove unneeded vic.h includes
  ARM: remove mach .handle_irq for VIC users
  ARM: VIC: set handle_arch_irq in VIC initialization
  ARM: VIC: shrink down vic.h
  irqchip: Move ARM gic.h to include/linux/irqchip/arm-gic.h
  ARM: use common irqchip_init for GIC init
  irqchip: Move ARM GIC to drivers/irqchip
  ARM: remove mach .handle_irq for GIC users
  ARM: GIC: set handle_arch_irq in GIC initialization
  ARM: GIC: remove direct use of gic_raise_softirq
  ARM: GIC: remove assembly ifdefs from gic.h
  ARM: mach-ux500: use SGI0 to wake up the other core
  arm: add set_handle_irq() to register the parent IRQ controller handler function
  irqchip: add basic infrastructure
  irqchip: add to the directories part of the IRQ subsystem in MAINTAINERS

Fixed up massive merge conflicts with the timer cleanup due to adjacent changes:

Signed-off-by: Olof Johansson <olof@lixom.net>

Conflicts:
	arch/arm/mach-bcm/board_bcm.c
	arch/arm/mach-cns3xxx/cns3420vb.c
	arch/arm/mach-ep93xx/adssphere.c
	arch/arm/mach-ep93xx/edb93xx.c
	arch/arm/mach-ep93xx/gesbc9312.c
	arch/arm/mach-ep93xx/micro9.c
	arch/arm/mach-ep93xx/simone.c
	arch/arm/mach-ep93xx/snappercl15.c
	arch/arm/mach-ep93xx/ts72xx.c
	arch/arm/mach-ep93xx/vision_ep9307.c
	arch/arm/mach-highbank/highbank.c
	arch/arm/mach-imx/mach-imx6q.c
	arch/arm/mach-msm/board-dt-8960.c
	arch/arm/mach-netx/nxdb500.c
	arch/arm/mach-netx/nxdkn.c
	arch/arm/mach-netx/nxeb500hmi.c
	arch/arm/mach-nomadik/board-nhk8815.c
	arch/arm/mach-picoxcell/common.c
	arch/arm/mach-realview/realview_eb.c
	arch/arm/mach-realview/realview_pb1176.c
	arch/arm/mach-realview/realview_pb11mp.c
	arch/arm/mach-realview/realview_pba8.c
	arch/arm/mach-realview/realview_pbx.c
	arch/arm/mach-socfpga/socfpga.c
	arch/arm/mach-spear13xx/spear1310.c
	arch/arm/mach-spear13xx/spear1340.c
	arch/arm/mach-spear13xx/spear13xx.c
	arch/arm/mach-spear3xx/spear300.c
	arch/arm/mach-spear3xx/spear310.c
	arch/arm/mach-spear3xx/spear320.c
	arch/arm/mach-spear3xx/spear3xx.c
	arch/arm/mach-spear6xx/spear6xx.c
	arch/arm/mach-tegra/board-dt-tegra20.c
	arch/arm/mach-tegra/board-dt-tegra30.c
	arch/arm/mach-u300/core.c
	arch/arm/mach-ux500/board-mop500.c
	arch/arm/mach-ux500/cpu-db8500.c
	arch/arm/mach-versatile/versatile_ab.c
	arch/arm/mach-versatile/versatile_dt.c
	arch/arm/mach-versatile/versatile_pb.c
	arch/arm/mach-vexpress/v2m.c
	include/asm-generic/vmlinux.lds.h
2013-01-14 19:55:03 -08:00
Rob Herring
0529e315bb ARM: use common irqchip_init for GIC init
Convert all GIC DT initialization over to use common irqchip_init
function.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
2013-01-12 10:47:32 -06:00
Rob Herring
1d5cc604f4 ARM: remove mach .handle_irq for GIC users
Now that the GIC initialization sets up the handle_arch_irq pointer, we
can remove it for all machines and make it static.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Anton Vorontsov <avorontsov@mvista.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2013-01-12 10:47:20 -06:00
Stephen Warren
6bb27d7349 ARM: delete struct sys_timer
Now that the only field in struct sys_timer is .init, delete the struct,
and replace the machine descriptor .timer field with the initialization
function itself.

This will enable moving timer drivers into drivers/clocksource without
having to place a public prototype of each struct sys_timer object into
include/linux; the intent is to create a single of_clocksource_init()
function that determines which timer driver to initialize by scanning
the device dtree, much like the proposed irqchip_init() at:
http://www.spinics.net/lists/arm-kernel/msg203686.html

Includes mach-omap2 fixes from Igor Grinberg.

Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-12-24 09:36:38 -07:00
Pavel Machek
ef21b491bf socfpga: map uart into virtual address space so that early_printk() works
Early printk code needs UART to be mapped early during
boot. early_printk() is left there during the start-up; it is useful
as our emulators are fairly slow.

Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
[olof: removed redundant newlines]
Signed-off-by: Olof Johansson <olof@lixom.net>
2012-11-05 09:17:20 -08:00
Dinh Nguyen
9c4566a117 ARM: socfpga: Enable SMP for socfpga
Enable SMP for the SOCFPGA platform.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-10-26 14:59:39 +02:00
Dinh Nguyen
66314223aa ARM: socfpga: initial support for Altera's SOCFPGA platform
Adding core definitions for Altera's SOCFPGA ARM platform.
Mininum support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-07-19 10:39:00 +02:00