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Commit Graph

7093 Commits

Author SHA1 Message Date
Stefan Agner
2c4e80e067 clk: meson: g12a: mark fclk_div2 as critical
On Amlogic Meson G12b platform, similar to fclk_div3, the fclk_div2
seems to be necessary for the system to operate correctly as well.

Typically, the clock also gets chosen by the eMMC peripheral. This
probably masked the problem so far. However, when booting from a SD
card the clock seems to get disabled which leads to a system freeze.

Let's mark this clock as critical, fixing boot from SD card on G12b
platforms.

Fixes: 085a4ea93d ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/577e0129e8ee93972d92f13187ff4e4286182f67.1598629915.git.stefan@agner.ch
2020-08-29 16:16:18 +02:00
Jernej Skrabec
a3ba99a24b
clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL
Audio cores need specific clock rates which can't be simply obtained by
adjusting integer multipliers and dividers. HW for such cases supports
delta-sigma modulation which enables fractional multipliers.

Port H3 delta-sigma table to R40. They have identical audio PLLs.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200825131049.1277596-1-jernej.skrabec@siol.net
2020-08-25 16:42:55 +02:00
Yangtao Li
fb038ce4db
clk: sunxi-ng: add support for the Allwinner A100 CCU
Add support for a100 in the sunxi-ng CCU framework.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1eb41bf6c966a0e54820200650d27a5d4f2ac160.1595572867.git.frank@allwinnertech.com
2020-08-25 10:52:18 +02:00
Krzysztof Kozlowski
0b8056106c clk: imx: vf610: Add CRC clock
Add the clock for CRC block allowing it to be enabled by consumers.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-23 10:08:35 +08:00
Anson Huang
7d6b5e4f24 clk: imx: Explicitly include bits.h
It is better to explicitly include the required header file rather
then get it through some recursive include.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22 20:36:57 +08:00
Anson Huang
e0d0d4d86c clk: imx8qxp: Support building i.MX8QXP clock driver as module
Change configuration to "tristate", add module author, description and
license to support building i.MX8QXP clock drivers as module.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22 12:38:29 +08:00
Anson Huang
9a976cd278 clk: imx8m: Support module build
Change configuration to "tristate", add module author, description
and license to support building i.MX8M SoCs clock driver as module.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22 12:38:26 +08:00
Anson Huang
f1f018dc03 clk: imx: Add clock configuration for ARMv7 platforms
Add CONFIG_CLK_xxx for i.MX ARMv7 platforms, and use it as build option
instead of CONFIG_SOC_xxx, the CONFIG_CLK_xxx will be selected by default
according to CONFIG_SOC_xxx.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22 12:38:23 +08:00
Anson Huang
870ed5e22a clk: imx: Support building i.MX common clock driver as module
There are more and more requirements of building SoC specific drivers
as modules, add support for building i.MX common clock driver as module
to meet the requirement.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22 12:38:20 +08:00
Anson Huang
d7d7518fdc clk: composite: Export clk_hw_register_composite()
Export clk_hw_register_composite() to support user built as module.

ERROR: modpost: "clk_hw_register_composite" [drivers/clk/imx/mxc-clk.ko]
undefined!

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22 12:38:06 +08:00
Anson Huang
0d03f02926 clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits
Use readl_relaxed() instead of __raw_readl(), and use BIT(x)
instead of (1 << X) to fix below build warning reported by kernel
test robot:

drivers/clk/imx/clk-imx6sl.c:149:49: warning: Shifting signed 32-bit
value by 31 bits is undefined behaviour [shiftTooManyBitsSigned]
     while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22 12:37:18 +08:00
Krzysztof Kozlowski
b84e23f513 ARM: s3c24xx: pass pointer to clk driver via platform data
Passing pointers directly as platform data is fragile and undocumented.
Better to create a platform data structure which explicitly documents
what is passed to the driver.

Suggested-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200806182059.2431-6-krzk@kernel.org
2020-08-19 20:58:10 +02:00
Arnd Bergmann
346f183cc1 ARM: s3c24xx: make S3C24XX_MISCCR access indirect
The clk driver uses both a function call into an exported
platform file and a direct register access to a hardcoded
virtual address for accessing the MISCCR register, both
become are a problem for a multiplatform kernel because
of the header file dependency.

Make this an indirect function call through platform data
instead.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200806182059.2431-5-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-08-19 20:58:05 +02:00
Nathan Chancellor
e9c006bc78 clk: rockchip: Fix initialization of mux_pll_src_4plls_p
A new warning in Clang points out that the initialization of
mux_pll_src_4plls_p appears incorrect:

../drivers/clk/rockchip/clk-rk3228.c:140:58: warning: suspicious
concatenation of string literals in an array initialization; did you
mean to separate the elements with a comma? [-Wstring-concatenation]
PNAME(mux_pll_src_4plls_p)      = { "cpll", "gpll", "hdmiphy" "usb480m" };
                                                              ^
                                                             ,
../drivers/clk/rockchip/clk-rk3228.c:140:48: note: place parentheses
around the string literal to silence warning
PNAME(mux_pll_src_4plls_p)      = { "cpll", "gpll", "hdmiphy" "usb480m" };
                                                    ^
1 warning generated.

Given the name of the variable and the same variable name in rv1108, it
seems that this should have been four distinct elements. Fix it up by
adding the comma as suggested.

Fixes: 307a2e9ac5 ("clk: rockchip: add clock controller for rk3228")
Link: https://github.com/ClangBuiltLinux/linux/issues/1123
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Link: https://lore.kernel.org/r/20200810044020.2063350-1-natechancellor@gmail.com
Reviewed-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-08-18 20:09:02 -07:00
Christophe JAILLET
3dabfa2bda clk: davinci: Use the correct size when allocating memory
'sizeof(*pllen)' should be used in place of 'sizeof(*pllout)' to avoid a
small over-allocation.

Fixes: 2d17269151 ("clk: davinci: New driver for davinci PLL clocks")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/20200809144959.747986-1-christophe.jaillet@wanadoo.fr
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-08-18 20:08:23 -07:00
Krzysztof Kozlowski
16b17fcf77 clk: samsung: s3c24xx: declare s3c24xx_common_clk_init() in shared header
The s3c2410_common_clk_init() and others are defined and used by the
clk-s3c24xx driver and also used in the mach-s3c24xx machine code.  Move
the declaration to a header to fix W=1 build warnings:

    drivers/clk/samsung/clk-s3c2410.c:320:13: warning: no previous prototype for 's3c2410_common_clk_init' [-Wmissing-prototypes]
      320 | void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
    drivers/clk/samsung/clk-s3c2412.c:205:13: warning: no previous prototype for 's3c2412_common_clk_init' [-Wmissing-prototypes]
      205 | void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
    drivers/clk/samsung/clk-s3c2443.c:341:13: warning: no previous prototype for 's3c2443_common_clk_init' [-Wmissing-prototypes]
      341 | void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2020-08-17 18:54:33 +02:00
Krzysztof Kozlowski
c2fe8ebb33 clk: samsung: s3c64xx: declare s3c64xx_clk_init() in shared header
The s3c64xx_clk_init() is defined and used by the clk-s3c64xx driver and
also used in the mach-s3c64xx machine code.  Move the declaration to a
header to fix W=1 build warning:

    drivers/clk/samsung/clk-s3c64xx.c:391:13: warning: no previous prototype for 's3c64xx_clk_init' [-Wmissing-prototypes]
      391 | void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2020-08-17 18:54:33 +02:00
Jerome Brunet
4fd433fd45 clk: meson: axg-audio: fix g12a tdmout sclk inverter
Fix the tdmout inverter of the g12a and following SoC families.
This inverter is special and needs two bits to be the inverse of each other
for the inverter to operate properly.

Fixes: 075001385c ("clk: meson: axg-audio: add g12a support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200729154359.1983085-4-jbrunet@baylibre.com
2020-08-17 15:58:12 +02:00
Jerome Brunet
cdabb1ffc7 clk: meson: axg-audio: separate axg and g12a regmap tables
There are more differences than what we initially thought.
Let's keeps things clear and separate the axg and g12a regmap tables of the
audio clock controller.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200729154359.1983085-3-jbrunet@baylibre.com
2020-08-17 15:58:09 +02:00
Jerome Brunet
7b70689b07 clk: meson: add sclk-ws driver
This is yet another simple but odd driver for the audio block of the g12a
and sm1 SoC families.

For TDMOUT's sclk to be properly inverted, bit 29 of
AUDIO_CLK_TDMOUT_x_CTRL should be the inverse of bit 28.
IOW bit28 == !bit29 at all times

This setting is automatically applied on axg and the manual setting was
added on g12a.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200729154359.1983085-2-jbrunet@baylibre.com
2020-08-17 15:58:02 +02:00
Linus Torvalds
341323fa0e More ACPI updates for 5.9-rc1
Add new hardware support to the ACPI driver for AMD SoCs, the x86 clk
 driver and the Designware i2c driver (changes from Akshu Agrawal and
 Pu Wen).
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Merge tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

Pull more ACPI updates from Rafael Wysocki:
 "Add new hardware support to the ACPI driver for AMD SoCs, the x86 clk
  driver and the Designware i2c driver (changes from Akshu Agrawal and
  Pu Wen)"

* tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm:
  clk: x86: Support RV architecture
  ACPI: APD: Add a fmw property is_raven
  clk: x86: Change name from ST to FCH
  ACPI: APD: Change name from ST to FCH
  i2c: designware: Add device HID for Hygon I2C controller
2020-08-15 08:18:22 -07:00
Linus Torvalds
fded091988 pwm: Changes for v5.9-rc1
The majority of this batch is conversion of the PWM period and duty
 cycle to 64-bit unsigned integers, which is required so that some types
 of hardware can generate the full range of signals that they're capable
 of. The remainder is mostly minor fixes and cleanups.
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Merge tag 'pwm/for-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
 "The majority of this batch is conversion of the PWM period and duty
  cycle to 64-bit unsigned integers, which is required so that some
  types of hardware can generate the full range of signals that they're
  capable of.

  The remainder is mostly minor fixes and cleanups"

* tag 'pwm/for-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
  pwm: bcm-iproc: handle clk_get_rate() return
  pwm: Replace HTTP links with HTTPS ones
  pwm: omap-dmtimer: Repair pwm_omap_dmtimer_chip's broken kerneldoc header
  pwm: mediatek: Provide missing kerneldoc description for 'soc' arg
  pwm: bcm-kona: Remove impossible comparison when validating duty cycle
  pwm: bcm-iproc: Remove impossible comparison when validating duty cycle
  pwm: iqs620a: Use lowercase hexadecimal literals for consistency
  pwm: Convert period and duty cycle to u64
  clk: pwm: Use 64-bit division function
  backlight: pwm_bl: Use 64-bit division function
  pwm: sun4i: Use nsecs_to_jiffies to avoid a division
  pwm: sifive: Use 64-bit division macro
  pwm: iqs620a: Use 64-bit division
  pwm: imx27: Use 64-bit division macro
  pwm: imx-tpm: Use 64-bit division macro
  pwm: clps711x: Use 64-bit division macro
  hwmon: pwm-fan: Use 64-bit division macro
  drm/i915: Use 64-bit division macro
2020-08-14 16:00:09 -07:00
Linus Torvalds
05a5b5d8a2 Here's some more updates that missed the last pull request because I
happened to tag the tree at an earlier point in the history of clk-next.
 I must have fat fingered it and checked out an older version of clk-next
 on this second computer I'm using.
 
 This time it actually includes more code for Qualcomm SoCs, the AT91
 major updates, and some Rockchip SoC clk driver updates as well. I've
 corrected this flow so this shouldn't happen again.
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull more clk updates from Stephen Boyd:
 "Here's some more updates that missed the last pull request because I
  happened to tag the tree at an earlier point in the history of
  clk-next. I must have fat fingered it and checked out an older version
  of clk-next on this second computer I'm using.

  This time it actually includes more code for Qualcomm SoCs, the AT91
  major updates, and some Rockchip SoC clk driver updates as well. I've
  corrected this flow so this shouldn't happen again"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (83 commits)
  clk: bcm2835: Do not use prediv with bcm2711's PLLs
  clk: drop unused function __clk_get_flags
  clk: hsdk: Fix bad dependency on IOMEM
  dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180
  clk: mmp: avoid missing prototype warning
  clk: sparx5: Add Sparx5 SoC DPLL clock driver
  dt-bindings: clock: sparx5: Add bindings include file
  clk: qoriq: add LS1021A core pll mux options
  clk: clk-atlas6: fix return value check in atlas6_clk_init()
  clk: tegra: pll: Improve PLLM enable-state detection
  clk: X1000: Add support for calculat REFCLK of USB PHY.
  clk: JZ4780: Reformat the code to align it.
  clk: JZ4780: Add functions for enable and disable USB PHY.
  clk: Ingenic: Add RTC related clocks for Ingenic SoCs.
  dt-bindings: clock: Add tabs to align code.
  dt-bindings: clock: Add RTC related clocks for Ingenic SoCs.
  clk: davinci: Use fallthrough pseudo-keyword
  clk: imx: Use fallthrough pseudo-keyword
  clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk
  clk: qcom: gcc-sdm660: Add missing modem reset
  ...
2020-08-12 12:19:49 -07:00
Linus Torvalds
30185b69a2 It looks like a smaller batch of clk updates this time around. In the core
framework we just have some minor tweaks and a debugfs feature, so not much to
 see there. The driver updates are fairly well split between AT91 and Qualcomm
 clk support. Adding those two drivers together equals about 50% of the
 diffstat. Otherwise, the big amount of work this time was on supporting
 Broadcom's Raspberry Pi firmware clks. See below for some more highlights.
 
 Core:
  - Document clk_hw_round_rate() so it gets some more use
  - Remove unused __clk_get_flags()
  - Add a prepare/enable debugfs feature similar to rate setting
 
 New Drivers:
  - Add support for SAMA7G5 SoC clks
  - Enable CPU clks on Qualcomm IPQ6018 SoCs
  - Enable CPU clks on Qualcomm MSM8996 SoCs
  - GPU clk support for Qualcomm SM8150 and SM8250 SoCs
  - Audio clks on Qualcomm SC7180 SoCs
  - Microchip Sparx5 DPLL clk
  - Add support for the new Renesas RZ/G2H (R8A774E1) SoC
 
 Updates:
  - Make defines for bcm63xx-gate clks to use in DT
  - Support BCM2711 SoC firmware clks
  - Add HDMI clks for BCM2711 SoCs
  - Add RTC related clks on Ingenic SoCs
  - Support USB PHY clks on Ingenic SoCs
  - Support gate clks on BCM6318 SoCs
  - RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs
  - Use poll_timeout functions in Rockchip clk driver
  - Support Rockchip rk3288w SoC variant
  - Mark mac_lbtest critical on Rockchip rk3188
  - Add CAAM clock support for i.MX vf610 driver
  - Add MU root clock support for i.MX imx8mp driver
  - Amlogic g12: add neural network accelerator clock sources
  - Amlogic meson8: remove critical flag for main PLL divider
  - Amlogic meson8: add video decoder clock gates
  - Convert one more Renesas DT binding to json-schema
  - Enhance critical clock handling on Renesas platforms to only consider
    clocks that were enabled at boot time
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "It looks like a smaller batch of clk updates this time around.

  In the core framework we just have some minor tweaks and a debugfs
  feature, so not much to see there. The driver updates are fairly well
  split between AT91 and Qualcomm clk support. Adding those two drivers
  together equals about 50% of the diffstat.

  Otherwise, the big amount of work this time was on supporting
  Broadcom's Raspberry Pi firmware clks.

  Highlights:

  Core:
   - Document clk_hw_round_rate() so it gets some more use
   - Remove unused __clk_get_flags()
   - Add a prepare/enable debugfs feature similar to rate setting

  New Drivers:
   - Add support for SAMA7G5 SoC clks
   - Enable CPU clks on Qualcomm IPQ6018 SoCs
   - Enable CPU clks on Qualcomm MSM8996 SoCs
   - GPU clk support for Qualcomm SM8150 and SM8250 SoCs
   - Audio clks on Qualcomm SC7180 SoCs
   - Microchip Sparx5 DPLL clk
   - Add support for the new Renesas RZ/G2H (R8A774E1) SoC

  Updates:
   - Make defines for bcm63xx-gate clks to use in DT
   - Support BCM2711 SoC firmware clks
   - Add HDMI clks for BCM2711 SoCs
   - Add RTC related clks on Ingenic SoCs
   - Support USB PHY clks on Ingenic SoCs
   - Support gate clks on BCM6318 SoCs
   - RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs
   - Use poll_timeout functions in Rockchip clk driver
   - Support Rockchip rk3288w SoC variant
   - Mark mac_lbtest critical on Rockchip rk3188
   - Add CAAM clock support for i.MX vf610 driver
   - Add MU root clock support for i.MX imx8mp driver
   - Amlogic g12: add neural network accelerator clock sources
   - Amlogic meson8: remove critical flag for main PLL divider
   - Amlogic meson8: add video decoder clock gates
   - Convert one more Renesas DT binding to json-schema
   - Enhance critical clock handling on Renesas platforms to only
     consider clocks that were enabled at boot time"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (79 commits)
  clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845
  ipq806x: gcc: add support for child probe
  clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static
  clk: qcom: ipq8074: Add correct index for PCIe clocks
  clk: <linux/clk-provider.h>: drop a duplicated word
  clk: renesas: cpg-mssr: Add r8a774e1 support
  dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1
  clk: Drop duplicate selection in Kconfig
  clk: qcom: smd: Add support for MSM8992/4 rpm clocks
  clk: qcom: ipq8074: Add missing clocks for pcie
  dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe
  Replace HTTP links with HTTPS ones: Common CLK framework
  clk: qcom: Add CPU clock driver for msm8996
  dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996
  soc: qcom: Separate kryo l2 accessors from PMU driver
  clk: meson: meson8b: add the vclk2_en gate clock
  clk: meson: meson8b: add the vclk_en gate clock
  clk: qcom: Fix return value check in apss_ipq6018_probe()
  clk: bcm: dvp: Add missing module informations
  clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
  ...
2020-08-07 13:35:51 -07:00
Akshu Agrawal
19fe87fd85 clk: x86: Support RV architecture
There is minor difference between previous family of SoC and
the current one. Which is the there is only 48Mh fixed clk.
There is no mux and no option to select another freq as there in previous.

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-08-07 20:12:00 +02:00
Akshu Agrawal
d9b77361c1 clk: x86: Change name from ST to FCH
AMD SoC general pupose clk is present in new platforms with
minor differences. We can reuse the same clk driver for other
platforms. Hence, changing name from ST(SoC) to FCH(IP)

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-08-07 20:11:59 +02:00
Akshu Agrawal
d58669b093 ACPI: APD: Change name from ST to FCH
AMD SoC general pupose clk is present in new platforms with
same MMIO mappings. We can reuse the same clk handler support
for other platforms. Hence, changing name from ST(SoC) to FCH(IP)

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-08-07 20:11:59 +02:00
Linus Torvalds
99ea1521a0 Remove uninitialized_var() macro for v5.9-rc1
- Clean up non-trivial uses of uninitialized_var()
 - Update documentation and checkpatch for uninitialized_var() removal
 - Treewide removal of uninitialized_var()
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Merge tag 'uninit-macro-v5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux

Pull uninitialized_var() macro removal from Kees Cook:
 "This is long overdue, and has hidden too many bugs over the years. The
  series has several "by hand" fixes, and then a trivial treewide
  replacement.

   - Clean up non-trivial uses of uninitialized_var()

   - Update documentation and checkpatch for uninitialized_var() removal

   - Treewide removal of uninitialized_var()"

* tag 'uninit-macro-v5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux:
  compiler: Remove uninitialized_var() macro
  treewide: Remove uninitialized_var() usage
  checkpatch: Remove awareness of uninitialized_var() macro
  mm/debug_vm_pgtable: Remove uninitialized_var() usage
  f2fs: Eliminate usage of uninitialized_var() macro
  media: sur40: Remove uninitialized_var() usage
  KVM: PPC: Book3S PR: Remove uninitialized_var() usage
  clk: spear: Remove uninitialized_var() usage
  clk: st: Remove uninitialized_var() usage
  spi: davinci: Remove uninitialized_var() usage
  ide: Remove uninitialized_var() usage
  rtlwifi: rtl8192cu: Remove uninitialized_var() usage
  b43: Remove uninitialized_var() usage
  drbd: Remove uninitialized_var() usage
  x86/mm/numa: Remove uninitialized_var() usage
  docs: deprecated.rst: Add uninitialized_var()
2020-08-04 13:49:43 -07:00
Linus Torvalds
822ef14e9d ARM: SoC driver updates for v5.9
A couple of subsystems have their own subsystem maintainers but choose
 to have the code merged through the soc tree as upstream, as the code
 tends to be used across multiple SoCs or has SoC specific drivers itself:
 
  - memory controllers:
      Krzysztof Kozlowski takes ownership of the drivers/memory
      subsystem and its drivers, starting out with a set of cleanup
      patches.
      A larger driver for the Tegra memory controller that was accidentally
      missed for v5.8 is now added.
 
  - reset controllers:
      Only minor updates to drivers/reset this time
 
  - firmware:
      The "turris mox" firmware driver gains support for signed firmware blobs
      The tegra firmware driver gets extended to export some debug information
      Various updates to i.MX firmware drivers, mostly cosmetic
 
  - ARM SCMI/SCPI:
      A new mechanism for platform notifications is added, among a number
      of minor changes.
 
  - optee:
      Probing of the TEE bus is rewritten to better support detection of
      devices that depend on the tee-supplicant user space.
      A new firmware based trusted platform module (fTPM) driver is added
      based on OP-TEE
 
  - SoC attributes:
      A new driver is added to provide a generic soc_device for identifying
      a machine through the SMCCC ARCH_SOC_ID firmware interface rather than
      by probing SoC family specific registers.
      The series also contains some cleanups to the common soc_device code.
 
 There are also a number of updates to SoC specific drivers,
 the main ones are:
 
  - Mediatek cmdq driver gains a few in-kernel interfaces
 
  - Minor updates to Qualcomm RPMh, socinfo, rpm drivers, mostly adding
    support for additional SoC variants
 
  - The Qualcomm GENI core code gains interconnect path voting and
    performance level support, and integrating this into a number of
    device drivers.
 
  - A new driver for Samsung Exynos5800 voltage coupler for
 
  - Renesas RZ/G2H (R8A774E1) SoC support gets added to a couple of SoC
    specific device drivers
 
  - Updates to the TI K3 Ring Accelerator driver
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Merge tag 'arm-drivers-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "A couple of subsystems have their own subsystem maintainers but choose
  to have the code merged through the soc tree as upstream, as the code
  tends to be used across multiple SoCs or has SoC specific drivers
  itself:

   - memory controllers:

     Krzysztof Kozlowski takes ownership of the drivers/memory subsystem
     and its drivers, starting out with a set of cleanup patches.

     A larger driver for the Tegra memory controller that was
     accidentally missed for v5.8 is now added.

   - reset controllers:

     Only minor updates to drivers/reset this time

   - firmware:

     The "turris mox" firmware driver gains support for signed firmware
     blobs The tegra firmware driver gets extended to export some debug
     information Various updates to i.MX firmware drivers, mostly
     cosmetic

   - ARM SCMI/SCPI:

     A new mechanism for platform notifications is added, among a number
     of minor changes.

   - optee:

     Probing of the TEE bus is rewritten to better support detection of
     devices that depend on the tee-supplicant user space. A new
     firmware based trusted platform module (fTPM) driver is added based
     on OP-TEE

   - SoC attributes:

     A new driver is added to provide a generic soc_device for
     identifying a machine through the SMCCC ARCH_SOC_ID firmware
     interface rather than by probing SoC family specific registers.

     The series also contains some cleanups to the common soc_device
     code.

  There are also a number of updates to SoC specific drivers, the main
  ones are:

   - Mediatek cmdq driver gains a few in-kernel interfaces

   - Minor updates to Qualcomm RPMh, socinfo, rpm drivers, mostly adding
     support for additional SoC variants

   - The Qualcomm GENI core code gains interconnect path voting and
     performance level support, and integrating this into a number of
     device drivers.

   - A new driver for Samsung Exynos5800 voltage coupler for

   - Renesas RZ/G2H (R8A774E1) SoC support gets added to a couple of SoC
     specific device drivers

   - Updates to the TI K3 Ring Accelerator driver"

* tag 'arm-drivers-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (164 commits)
  soc: qcom: geni: Fix unused label warning
  soc: qcom: smd-rpm: Fix kerneldoc
  memory: jz4780_nemc: Only request IO memory the driver will use
  soc: qcom: pdr: Reorder the PD state indication ack
  MAINTAINERS: Add Git repository for memory controller drivers
  memory: brcmstb_dpfe: Fix language typo
  memory: samsung: exynos5422-dmc: Correct white space issues
  memory: samsung: exynos-srom: Correct alignment
  memory: pl172: Enclose macro argument usage in parenthesis
  memory: of: Correct kerneldoc
  memory: omap-gpmc: Fix language typo
  memory: omap-gpmc: Correct white space issues
  memory: omap-gpmc: Use 'unsigned int' for consistency
  memory: omap-gpmc: Enclose macro argument usage in parenthesis
  memory: omap-gpmc: Correct kerneldoc
  memory: mvebu-devbus: Align with open parenthesis
  memory: mvebu-devbus: Add missing braces to all arms of if statement
  memory: bt1-l2-ctl: Add blank lines after declarations
  soc: TI knav_qmss: make symbol 'knav_acc_range_ops' static
  firmware: ti_sci: Replace HTTP links with HTTPS ones
  ...
2020-08-03 19:30:59 -07:00
Linus Torvalds
2f3fbfdaf7 ARM: SoC DT changes for 5.9
As usual, there are many patches addressing minor issues in existing
 DTS files, such as DTC warnings, or adding support for additional
 peripherals.
 
 There are three added SoCs in existing product families:
 
  - Amazon:
     Alpine v3 is a 16-core Cortex-A72 SoC from Amazon's Annapurna Labs,
     otherwise known as AL73400 or first-generation Graviton, and following
     the already supported Cortex-A1`5 and Cortex-A57 based Alpine chips.
     This one is added together with the official Evaluation platform.
 
  - Qualcomm:
     The Snapdragon SDM630 platform is a family of mid-range mobile phone
     chips from 2017 based on Cortex-A53 or Kryo 260 CPUs.
     A total of five end-user products are added based on these, all
     Android phones from Sony: Xperia 10, 10 Plus, XA2, XA2 Plus and
     XA2 Ultra.
 
  - Renesas:
     RZ/G2H (r8a774e1) is currently the top model in the Renesas RZ/G
     family, and apparently closely related to the RZ/G2N and RZ/G2M
     models we already support but has a faster GPU and additional
     on-chip peripherals.
     It is added along with the HopeRun HiHope RZ/G2H development board
 
 A small number of new boards for already supported SoCs also debut:
 
  - Allwinner sunxi:
     Only one new machine, revision v1.2 of the Pine64 PinePhone
     (non-Android) smartphone, containing minor changes compared to
     earlier versions.
 
  - Amlogic Meson:
     WeTek Core2 is an Amlogic S912 (GXM) based Set-top-box
 
  - Aspeed:
     EthanolX is AMD's EPYC data center rerence platform, using an
     ASpeed AST2600 baseboard management controller.
 
  - Mediatek:
     Lenovo IdeaPad Duet 10.1" (kukui/krane) is a new Chromebook
     based on the MT8183 (Helio P60t) SoC.
 
  - Nvidia Tegra:
     ASUS Google Nexus 7 and Acer Iconia Tab A500 are two Android
     tablets from around 2012 using Tegra 3 and Tegra 2, respectively.
     Thanks to PostmarketOS, these can now run mainline kernels
     and become useful again.
 
     The Jetson Xavier NX Developer Kit uses a SoM and carrier board
     for the Tegra194, their latest 64-bit chip based on Carmel CPU
     cores and Volta graphics.
 
  - NXP i.MX:
     Five new boards based on the 32-bit i.MX6 series are added:
     The MYiR MYS-6ULX single-board computer, and four different
     models of industrial computers from Protonic.
 
  - Qualcomm:
     MikroTik RouterBoard 3011 is a rackmounted router based on the
     32-bit IPQ8064 networking SoC
     Three older phones get added, the Snapdragon 808 (msm8992) based
     Xiaomi Libra (Mi 4C) and Microsoft Lumia 950, originally running
     Windows Phone, and the Snapdragon 810 (msm8994) based Sony
     Xperia Z5.
 
  - Renesas:
     In addition to the HiHope RZ/G2H board mentioned above, we gain
     support for board versions 3.0 and 4.0 of the earlier RZ/G2M and
     RZ/G2N reference boards.
     Beacon EmbeddedWorks adds another SoM+Carrier development board
     for RZ/G2M.
 
  - Rockchips:
     Radxa Rock Pi N8 development board and the VMARC RK3288 SoM it
     is based on, using the high-end 32-bit rk3288 SoC.
 
 Notable updates to existing platforms are usually for added on-chip
 peripherals, including:
 
  - ASpeed AST2xxx (various)
 
  - Allwinner (cpufreq, thermal, Pinephone touchscreen)
 
  - Amlogic Meson (audio, gpu dvdfs, board updates)
 
  - Arm Versatile
 
  - Broadcom (board updates for switch ports, Raspberry pi clock updates)
 
  - Hisilicon (various)
 
  - Intel/Altera SoCFPGA (various)
 
  - Marvell Armada 7xxx/8xxx (smmu)
 
  - Marvell MMP (GPU on mmp2/mmp3)
 
  - Mediatek mt8183 (USB, pericfg)
 
  - NXP Layerscape (VPU, thermal, DSPI)
 
  - NXP i.MX (VPU, bindings, board updates)
 
  - Nvidia Tegra194 (GPU)
 
  - Qualcomm (GPU, Interconnect, ...)
 
  - Renesas R-Car (SPI, IPMMU, board updates)
 
  - STMicroelectronics STM32 (various)
 
  - Samsung Exynos (various)
 
  - Socionext Uniphier (updates to serial, and pcie)
 
  - TI K3 (serdes, usb3, audio, sd, chipid)
 
  - TI OMAP (IPU/DSP remoteproc changes, dropping platform data)
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC DT updates from Arnd Bergmann:
 "As usual, there are many patches addressing minor issues in existing
  DTS files, such as DTC warnings, or adding support for additional
  peripherals.

  There are three added SoCs in existing product families:

   - Amazon:

     Alpine v3 is a 16-core Cortex-A72 SoC from Amazon's Annapurna Labs,
     otherwise known as AL73400 or first-generation Graviton, and
     following the already supported Cortex-A1`5 and Cortex-A57 based
     Alpine chips. This one is added together with the official
     Evaluation platform.

   - Qualcomm:

     The Snapdragon SDM630 platform is a family of mid-range mobile
     phone chips from 2017 based on Cortex-A53 or Kryo 260 CPUs. A total
     of five end-user products are added based on these, all Android
     phones from Sony: Xperia 10, 10 Plus, XA2, XA2 Plus and XA2 Ultra.

   - Renesas:

     RZ/G2H (r8a774e1) is currently the top model in the Renesas RZ/G
     family, and apparently closely related to the RZ/G2N and RZ/G2M
     models we already support but has a faster GPU and additional
     on-chip peripherals. It is added along with the HopeRun HiHope
     RZ/G2H development board

  A small number of new boards for already supported SoCs also debut:

   - Allwinner sunxi:

     Only one new machine, revision v1.2 of the Pine64 PinePhone
     (non-Android) smartphone, containing minor changes compared to
     earlier versions.

   - Amlogic Meson:

     WeTek Core2 is an Amlogic S912 (GXM) based Set-top-box

   - Aspeed:

     EthanolX is AMD's EPYC data center rerence platform, using an
     ASpeed AST2600 baseboard management controller.

   - Mediatek:

     Lenovo IdeaPad Duet 10.1" (kukui/krane) is a new Chromebook based
     on the MT8183 (Helio P60t) SoC.

   - Nvidia Tegra:

     ASUS Google Nexus 7 and Acer Iconia Tab A500 are two Android
     tablets from around 2012 using Tegra 3 and Tegra 2, respectively.
     Thanks to PostmarketOS, these can now run mainline kernels and
     become useful again.

     The Jetson Xavier NX Developer Kit uses a SoM and carrier board for
     the Tegra194, their latest 64-bit chip based on Carmel CPU cores
     and Volta graphics.

   - NXP i.MX:

     Five new boards based on the 32-bit i.MX6 series are added: The
     MYiR MYS-6ULX single-board computer, and four different models of
     industrial computers from Protonic.

   - Qualcomm:

     MikroTik RouterBoard 3011 is a rackmounted router based on the
     32-bit IPQ8064 networking SoC

     Three older phones get added, the Snapdragon 808 (msm8992) based
     Xiaomi Libra (Mi 4C) and Microsoft Lumia 950, originally running
     Windows Phone, and the Snapdragon 810 (msm8994) based Sony Xperia
     Z5.

   - Renesas:

     In addition to the HiHope RZ/G2H board mentioned above, we gain
     support for board versions 3.0 and 4.0 of the earlier RZ/G2M and
     RZ/G2N reference boards. Beacon EmbeddedWorks adds another
     SoM+Carrier development board for RZ/G2M.

   - Rockchips:

     Radxa Rock Pi N8 development board and the VMARC RK3288 SoM it is
     based on, using the high-end 32-bit rk3288 SoC.

  Notable updates to existing platforms are usually for added on-chip
  peripherals, including:

   - ASpeed AST2xxx (various)

   - Allwinner (cpufreq, thermal, Pinephone touchscreen)

   - Amlogic Meson (audio, gpu dvdfs, board updates)

   - Arm Versatile

   - Broadcom (board updates for switch ports, Raspberry pi clock updates)

   - Hisilicon (various)

   - Intel/Altera SoCFPGA (various)

   - Marvell Armada 7xxx/8xxx (smmu)

   - Marvell MMP (GPU on mmp2/mmp3)

   - Mediatek mt8183 (USB, pericfg)

   - NXP Layerscape (VPU, thermal, DSPI)

   - NXP i.MX (VPU, bindings, board updates)

   - Nvidia Tegra194 (GPU)

   - Qualcomm (GPU, Interconnect, ...)

   - Renesas R-Car (SPI, IPMMU, board updates)

   - STMicroelectronics STM32 (various)

   - Samsung Exynos (various)

   - Socionext Uniphier (updates to serial, and pcie)

   - TI K3 (serdes, usb3, audio, sd, chipid)

   - TI OMAP (IPU/DSP remoteproc changes, dropping platform data)"

* tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (605 commits)
  arm64: dts: meson: odroid-n2: add jack audio output support
  arm64: dts: meson: odroid-n2: enable audio loopback
  ARM: dts: berlin: Align L2 cache-controller nodename with dtschema
  arm64: dts: qcom: Add Microsoft Lumia 950 (Talkman) device tree
  arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree
  arm64: dts: qcom: msm8992: Add RPMCC node
  arm64: dts: qcom: msm8992: Add PSCI support.
  arm64: dts: qcom: msm8992: Add PMU node
  arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodes
  arm64: dts: qcom: msm8992: Add SPMI PMIC arbiter device
  arm64: dts: qcom: msm8992: Add a SCM node
  arm64: dts: qcom: msm8992: Add a proper CPU map
  arm64: dts: qcom: bullhead: Move UART pinctrl to SoC
  arm64: dts: qcom: bullhead: Add qcom,msm-id
  arm64: dts: qcom: msm8992: Fix SDHCI1
  arm64: dts: qcom: msm8992: Modernize the DTS style
  arm64: dts: qcom: Add support for Sony Xperia Z5 (SoMC Sumire-RoW)
  arm64: dts: qcom: Move msm8994-smd-rpm contents to lg-bullhead.
  arm64: dts: qcom: msm8994: Add support for SMD RPM
  arm64: dts: qcom: msm8992: Add a label to rpm-requests
  ...
2020-08-03 19:19:34 -07:00
Stephen Boyd
dd9c697a94 Merge branches 'clk-microchip', 'clk-mmp', 'clk-unused' and 'clk-at91' into clk-next
- Add support for SAMA7G5 SoC clks
 - Microchip Sparx5 DPLL clk

* clk-microchip:
  clk: sparx5: Add Sparx5 SoC DPLL clock driver
  dt-bindings: clock: sparx5: Add bindings include file

* clk-mmp:
  clk: mmp: avoid missing prototype warning

* clk-unused:
  clk: drop unused function __clk_get_flags

* clk-at91:
  clk: at91: sama7g5: add clock support for sama7g5
  clk: at91: clk-utmi: add utmi support for sama7g5
  clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs
  clk: at91: add macro for pll ids mask
  clk: at91: clk-programmable: add mux_table option
  clk: at91: clk-peripheral: add support for changeable parent rate
  clk: at91: clk-master: add master clock support for SAMA7G5
  clk: at91: clk-generated: add mux_table option
  clk: at91: clk-generated: pass the id of changeable parent at registration
  clk: at91: replace conditional operator with double logical not
  clk: at91: sckc: register slow_rc with accuracy option
  clk: at91: sam9x60: fix main rc oscillator frequency
  clk: at91: sam9x60-pll: use frac when setting frequency
  clk: at91: sam9x60-pll: check fcore against ranges
  clk: at91: sam9x60-pll: use logical or for range check
  clk: at91: clk-sam9x60-pll: fix mul mask
  clk: at91: clk-generated: check best_rate against ranges
  clk: at91: clk-generated: continue if __clk_determine_rate() returns error
  clk: at91: fix possible dead lock in new drivers
2020-08-03 15:07:18 -07:00
Stephen Boyd
1a91e318c0 Merge branches 'clk-fallthru', 'clk-ingenic', 'clk-tegra', 'clk-sirf' and 'clk-qoriq' into clk-next
- Add RTC related clks on Ingenic SoCs
 - Support USB PHY clks on Ingenic SoCs

* clk-fallthru:
  clk: davinci: Use fallthrough pseudo-keyword
  clk: imx: Use fallthrough pseudo-keyword

* clk-ingenic:
  clk: X1000: Add support for calculat REFCLK of USB PHY.
  clk: JZ4780: Reformat the code to align it.
  clk: JZ4780: Add functions for enable and disable USB PHY.
  clk: Ingenic: Add RTC related clocks for Ingenic SoCs.
  dt-bindings: clock: Add tabs to align code.
  dt-bindings: clock: Add RTC related clocks for Ingenic SoCs.

* clk-tegra:
  clk: tegra: pll: Improve PLLM enable-state detection

* clk-sirf:
  clk: clk-atlas6: fix return value check in atlas6_clk_init()

* clk-qoriq:
  clk: qoriq: add LS1021A core pll mux options
2020-08-03 15:07:08 -07:00
Stephen Boyd
53e07424ec Merge branches 'clk-actions', 'clk-rockchip', 'clk-iproc', 'clk-intel' and 'clk-debugfs' into clk-next
- RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs

* clk-actions:
  MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs
  clk: actions: Add Actions S500 SoC Reset Management Unit support
  dt-bindings: reset: Add binding constants for Actions S500 RMU
  clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC
  dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC
  clk: actions: Fix h_clk for Actions S500 SoC

* clk-rockchip:
  clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks
  clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328"
  clk: rockchip: use separate compatibles for rk3288w-cru
  dt-bindings: clocks: add rk3288w variant compatible
  clk: rockchip: Handle clock tree for rk3288w variant
  clk: rockchip: convert rk3036 pll type to use internal lock status
  clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeout
  clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeout

* clk-iproc:
  clk: iproc: round clock rate to the closest

* clk-intel:
  clk: intel: Avoid unnecessary memset by improving code
  clk: intel: Improve locking in the driver
  clk: intel: Use devm_clk_hw_register() instead of clk_hw_register()

* clk-debugfs:
  clk: Add support for enabling/disabling clocks from debugfs
2020-08-03 15:06:53 -07:00
Stephen Boyd
987106e5f2 Merge branches 'clk-https', 'clk-renesas', 'clk-kconfig', 'clk-amlogic' and 'clk-imx' into clk-next
* clk-https:
  Replace HTTP links with HTTPS ones: Common CLK framework

* clk-renesas:
  clk: renesas: cpg-mssr: Add r8a774e1 support
  dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1
  clk: renesas: Add r8a774e1 CPG Core Clock Definitions
  dt-bindings: power: Add r8a774e1 SYSC power domain definitions
  clk: renesas: rzg2: Mark RWDT clocks as critical
  clk: renesas: rcar-gen3: Mark RWDT clocks as critical
  clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot
  dt-bindings: clock: renesas: cpg: Convert to json-schema

* clk-kconfig:
  clk: hsdk: Fix bad dependency on IOMEM
  clk: Specify IOMEM dependency for HSDK pll driver
  clk: Drop duplicate selection in Kconfig
  clk: AST2600: Add mux for EMMC clock
  clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER

* clk-amlogic:
  clk: meson: meson8b: add the vclk2_en gate clock
  clk: meson: meson8b: add the vclk_en gate clock
  clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
  clk: meson: g12a: Add support for NNA CLK source clocks
  dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs

* clk-imx:
  clk: imx: vf610: add CAAM clock
  clk: imx8mp: add mu root clk
2020-08-03 15:06:45 -07:00
Stephen Boyd
c63e2a7af3 Merge branches 'clk-socfpga', 'clk-doc', 'clk-qcom', 'clk-vc5' and 'clk-bcm' into clk-next
- Enable CPU clks on Qualcomm IPQ6018 SoCs
 - Enable CPU clks on Qualcomm MSM8996 SoCs
 - GPU clk support for Qualcomm SM8150 and SM8250 SoCs
 - Audio clks on Qualcomm SC7180 SoCs
 - Make defines for bcm63xx-gate clks to use in DT
 - Support gate clks on BCM6318 SoCs
 - Add HDMI clks for BCM2711 SoCs
 - Support BCM2711 SoC firmware clks

* clk-socfpga:
  clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
  clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
  dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK

* clk-doc:
  clk: Clean up kernel-doc errors
  clk: <linux/clk-provider.h>: drop a duplicated word
  clk: add function documentation for clk_hw_round_rate()

* clk-qcom: (38 commits)
  dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180
  clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk
  clk: qcom: gcc-sdm660: Add missing modem reset
  clk: qcom: lpass: Add support for LPASS clock controller for SC7180
  clk: qcom: gcc: Add support for GCC LPASS clock for SC7180
  dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
  clk: qcom: gdsc: Add support to enable retention of GSDCR
  clk: qcom: Export gdsc_gx_do_nothing_enable() to modules
  clk: qcom: Add graphics clock controller driver for SM8250
  clk: qcom: Add graphics clock controller driver for SM8150
  clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers
  dt-bindings: clock: add SM8250 QCOM Graphics clock bindings
  dt-bindings: clock: add SM8150 QCOM Graphics clock bindings
  dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc
  clk: qcom: gcc: remove unnecessary vco_table from SM8150
  clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll
  clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid
  clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL
  clk: qcom: gcc: fix sm8150 GPU and NPU clocks
  dt-bindings: clock: Fix qcom,msm8996-apcc yaml syntax
  ...

* clk-vc5:
  clk: vc5: use a dedicated struct to describe the output drivers
  dt-bindings: clk: versaclock5: convert to yaml
  MAINTAINERS: take over IDT VersaClock 5 clock driver
  dt-bindings: clk: versaclock5: fix 'idt' prefix typos
  clk: vc5: Add memory check to prevent oops
  clk: vc5: fix use of memory after it has been kfree'd
  clk: vc5: Enable addition output configurations of the Versaclock
  dt: Add additional option bindings for IDT VersaClock
  clk: vc5: Allow Versaclock driver to support multiple instances

* clk-bcm: (44 commits)
  clk: bcm2835: Do not use prediv with bcm2711's PLLs
  dt-bindings: arm: bcm: Add a select to the RPI Firmware binding
  clk: bcm: dvp: Add missing module informations
  clk: bcm: rpi: Remove the quirks for the CPU clock
  clk: bcm2835: Don't cache the PLLB rate
  clk: bcm2835: Allow custom CCF flags for the PLLs
  Revert "clk: bcm2835: remove pllb"
  clk: bcm: rpi: Give firmware clocks a name
  clk: bcm: rpi: Discover the firmware clocks
  clk: bcm: rpi: Add an enum for the firmware clocks
  clk: bcm: rpi: Add DT provider for the clocks
  clk: bcm: rpi: Make the PLLB registration function return a clk_hw
  clk: bcm: rpi: Split pllb clock hooks
  clk: bcm: rpi: Rename is_prepared function
  clk: bcm: rpi: Pass the clocks data to the firmware function
  clk: bcm: rpi: Add clock id to data
  clk: bcm: rpi: Create a data structure for the clocks
  clk: bcm: rpi: Use CCF boundaries instead of rolling our own
  clk: bcm: rpi: Make sure the clkdev lookup is removed
  clk: bcm: rpi: Switch to clk_hw_register_clkdev
  ...
2020-08-03 15:06:16 -07:00
Nicolas Saenz Julienne
f34e4651ce clk: bcm2835: Do not use prediv with bcm2711's PLLs
Contrary to previous SoCs, bcm2711 doesn't have a prescaler in the PLL
feedback loop. Bypass it by zeroing fb_prediv_mask when running on
bcm2711.

Note that, since the prediv configuration bits were re-purposed, this
was triggering miscalculations on all clocks hanging from the VPU clock,
notably the aux UART, making its output unintelligible.

Fixes: 42de9ad400 ("clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support")
Reported-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Link: https://lore.kernel.org/r/20200730182619.23246-1-nsaenzjulienne@suse.de
Tested-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-08-03 14:26:20 -07:00
Julia Lawall
6cfde88418 clk: drop unused function __clk_get_flags
The function __clk_get_flags has not been used since the April 2019
commit a348f05361 ("ARM: omap2+: hwmod: drop CLK_IS_BASIC
flag usage").  Other uses were removed in June 2015, eg by
commit 98d8a60ecc ("clk: Convert __clk_get_flags() to
clk_hw_get_flags()"), which shows how clk_hw_get_flags can easily
be used instead.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/1596272022-14173-1-git-send-email-Julia.Lawall@inria.fr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-08-03 13:53:34 -07:00
Geert Uytterhoeven
bd8548d0dc clk: hsdk: Fix bad dependency on IOMEM
CONFIG_IOMEM does not exist.  The correct symbol to depend on is
CONFIG_HAS_IOMEM.

Fixes: 1e7468bd9d ("clk: Specify IOMEM dependency for HSDK pll driver")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200803084835.21838-1-geert+renesas@glider.be
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-08-03 13:52:48 -07:00
Stephen Boyd
ba857b2122 Merge branch 'clk-fixes' into clk-kconfig
Need to merge this up to get the IOMEM dependency patch on top that is
broken and fixed in the next commit.

* clk-fixes:
  clk: Specify IOMEM dependency for HSDK pll driver
  clk: AST2600: Add mux for EMMC clock
  clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER
2020-08-03 13:52:05 -07:00
Arnd Bergmann
4aeccdf067 clk: mmp: avoid missing prototype warning
The kernel test robot points out two harmless warnings in the
mmp clk drivers:

drivers/clk/mmp/clk-pxa168.c:68:13: warning: no previous prototype for 'pxa168_clk_init' [-Wmissing-prototypes]
drivers/clk/mmp/clk-pxa910.c:66:13: warning: no previous prototype for 'pxa910_clk_init' [-Wmissing-prototypes]

Fix these by including corresponding header file.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20200729113456.4072290-1-arnd@arndb.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-29 12:52:40 -07:00
Lars Povlsen
53727eb6b3 clk: sparx5: Add Sparx5 SoC DPLL clock driver
This adds a device driver for the Sparx5 SoC DPLL clock

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200727084211.6632-9-lars.povlsen@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-28 18:17:56 -07:00
Michael Krummsdorf
92df3a9bf3 clk: qoriq: add LS1021A core pll mux options
This allows to clock the cores with 1 GHz, 500 MHz and 250 MHz.

Signed-off-by: Michael Krummsdorf <michael.krummsdorf@tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/20200610113837.27117-1-matthias.schiffer@ew.tq-group.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27 18:25:17 -07:00
Xu Wang
12b90b4085 clk: clk-atlas6: fix return value check in atlas6_clk_init()
In case of error, the function clk_register() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().

Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
Link: https://lore.kernel.org/r/20200713032143.21362-1-vulab@iscas.ac.cn
Acked-by: Barry Song <baohua@kernel.org>
Fixes: 7bf21bc81f ("clk: sirf: re-arch to make the codes support both prima2 and atlas6")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27 18:22:26 -07:00
Dmitry Osipenko
fa64023763 clk: tegra: pll: Improve PLLM enable-state detection
Power Management Controller (PMC) can override the PLLM clock settings,
including the enable-state. Although PMC could only act as a second level
gate, meaning that PLLM needs to be enabled by the Clock and Reset
Controller (CaR) anyways if we want it to be enabled. Hence, when PLLM is
overridden by PMC, it needs to be enabled by CaR and ungated by PMC in
order to be functional. Please note that this patch doesn't fix any known
problem, and thus, it's merely a minor improvement.

Link: https://lore.kernel.org/linux-arm-kernel/20191210120909.GA2703785@ulmo/T/
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20200709172057.13951-1-digetx@gmail.com
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27 18:21:17 -07:00
周琰杰 (Zhou Yanjie)
810797c145 clk: X1000: Add support for calculat REFCLK of USB PHY.
Add functions for calculat the rate of REFCLK, which is needed by
USB PHY in Ingenic X1000 SoC.

Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20200630163852.47267-4-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27 18:18:14 -07:00
周琰杰 (Zhou Yanjie)
beb61eb068 clk: JZ4780: Reformat the code to align it.
Reformat the code (add one level of indentation before the values),
to align the code in the macro definition section.

Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20200630163852.47267-3-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27 18:18:14 -07:00
周琰杰 (Zhou Yanjie)
dcd062a88e clk: JZ4780: Add functions for enable and disable USB PHY.
Add new functions to "jz4780_otg_phy_ops" to enable or disable the
USB PHY in the JZ4780 SoC.

Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20200630163852.47267-2-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27 18:18:14 -07:00
周琰杰 (Zhou Yanjie)
82df5b7329 clk: Ingenic: Add RTC related clocks for Ingenic SoCs.
The RTC unit in the Ingenic SoCs has two clock sources, one
is from an external 32.768kHz clock, and the other is from an
external 24MHz/48MHz main clock that is divided by 512. The
choice of these two clocks is controlled by the ERCS bit in
the OPCR register. The RNG unit will also use this clock.

Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/20200725051136.58220-4-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27 18:17:52 -07:00
Gustavo A. R. Silva
7a346a37e4 clk: davinci: Use fallthrough pseudo-keyword
Replace the existing /* fall through */ comments and its variants with
the new pseudo-keyword macro fallthrough[1].

[1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through

Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Link: https://lore.kernel.org/r/20200727201122.GA2593@embeddedor
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27 15:21:31 -07:00
Gustavo A. R. Silva
d388e18f63 clk: imx: Use fallthrough pseudo-keyword
Replace the existing /* fall through */ comments and its variants with
the new pseudo-keyword macro fallthrough[1].

[1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through

Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Link: https://lore.kernel.org/r/20200727200922.GA2326@embeddedor
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27 15:21:19 -07:00
Konrad Dybcio
3386af51d3 clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk
Add missing halt_check, hwcg_reg and hwcg_bit properties.
These were likely omitted when porting the driver upstream.

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200726111215.22361-9-konradybcio@gmail.com
Fixes: f2a76a2955 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27 15:16:39 -07:00
Konrad Dybcio
b538304da7 clk: qcom: gcc-sdm660: Add missing modem reset
This will be required in order to support the
modem upstream.

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200726111215.22361-2-konradybcio@gmail.com
Fixes: f2a76a2955 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27 15:16:17 -07:00
Taniya Das
edab812d80 clk: qcom: lpass: Add support for LPASS clock controller for SC7180
The Low Power Audio subsystem clocks are required for Audio client
to be able to request for the clocks and power domains.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1595606878-2664-5-git-send-email-tdas@codeaurora.org
[sboyd@kernel.org: Drop unused ret in probe function]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 13:09:43 -07:00
Taniya Das
47110b6aa5 clk: qcom: gcc: Add support for GCC LPASS clock for SC7180
Add the GCC lpass clock which is required to access the LPASS core
clocks.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1595606878-2664-4-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 13:08:06 -07:00
Taniya Das
173722995c clk: qcom: gdsc: Add support to enable retention of GSDCR
Add support for the RETAIN_FF_ENABLE feature which enables the
usage of retention registers. These registers maintain their
state after disabling and re-enabling a GDSC.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1595606878-2664-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 13:04:48 -07:00
Stephen Boyd
6378cfdcc3 clk: Clean up kernel-doc errors
Two things aren't documented causing kernel-doc to fail when checking
the core clk.c file. Fix them so that this file is clean.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200622090935.213833-1-sboyd@kernel.org
2020-07-24 02:41:52 -07:00
Stephen Boyd
413d84b88b clk: qcom: Export gdsc_gx_do_nothing_enable() to modules
A clk driver can be a module but the gdsc code is in the common module.
Export this symbol so that allmodconfig builds keep working.

Cc: Jonathan Marek <jonathan@marek.ca>
Fixes: 0638226dd0 ("clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200724094025.3261266-1-sboyd@kernel.org
2020-07-24 02:41:26 -07:00
Claudiu Beznea
cb783bbbcf clk: at91: sama7g5: add clock support for sama7g5
Add clock support for SAMA7G5.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-19-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:19:09 -07:00
Claudiu Beznea
ef396df992 clk: at91: clk-utmi: add utmi support for sama7g5
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-18-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:19:08 -07:00
Claudiu Beznea
43b1bb4a9b clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs
Some of the SAMA7G5 PLLs support multiple outputs (e.g. AUDIO PLL).
For these, split the PLL clock in two: fractional clock and
divider clock. In case PLLs supports multiple outputs (since these
outputs are dividers (with different settings) sharing the same
fractional part), it will register one fractional clock and multiple
divider clocks (dividers sharing the fractional clock).

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-17-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:19:08 -07:00
Claudiu Beznea
c57aaaa28c clk: at91: clk-programmable: add mux_table option
Add mux table option. This is necessary for IP versions that has
gaps in the range of available clock sources (e.g. SAMA7G5).

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-15-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:19:08 -07:00
Claudiu Beznea
b4c115c761 clk: at91: clk-peripheral: add support for changeable parent rate
Some peripheral clocks on SAMA7G5 supports requesting parent to change
its rate (image related clocks: csi, csi2dc, isc). Add support
so that if registered with this option the clock rate to be
requested from parent.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-14-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:19:08 -07:00
Claudiu Beznea
75c88143f3 clk: at91: clk-master: add master clock support for SAMA7G5
Add master clock support (MCK1..4) for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems. One of them
feeds image subsystem and is changeable based on image subsystem
needs.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-13-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:19:08 -07:00
Claudiu Beznea
22a1dfe93b clk: at91: clk-generated: add mux_table option
Add mux table option. This is necessary for IP versions that has
gaps in the range of available clock sources (e.g. SAMA7G5).

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-12-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:19:08 -07:00
Claudiu Beznea
64c9247b9e clk: at91: clk-generated: pass the id of changeable parent at registration
Pass the ID of changeable parent at registration. This will allow
the scalability of this clock driver with regards to the changeable
parent ID for versions of this IP where changeable parent is not the
last one in the parents list (e.g. SAMA7G5). With this the clock flags
are set to zero in case we have no changeable parent. Also in
clk_generated_best_diff() the *best_diff variable is check against
tmp_diff variable using ">=" operator instead of ">" so that in case
the requested frequency could be obtained using fix parents + gck
dividers but the clock also supports changeable parent to be able
to force the usage of the changeable parent.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-11-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:19:08 -07:00
Claudiu Beznea
42324d953b clk: at91: replace conditional operator with double logical not
Replace conditional operator with double logical not as code
may be simpler to read.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-10-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:19:08 -07:00
Claudiu Beznea
e1e3e7008a clk: at91: sckc: register slow_rc with accuracy option
Chapter 57.7.5 of SAM9X60 datasheet specifies that the maximum drift of
this oscillator is +- 3KHz. Use that value and the formula at [1]
or the calculator at [2] to compute the PPB value.

[1] https://www.everythingrf.com/rf-calculators/ppm-to-hz-calculator
[2] https://www.changpuak.ch/electronics/ppm_to_Hz_converter.php

Fixes: 04bcc4275e ("clk: at91: sckc: add support for SAM9X60")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-9-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:19:08 -07:00
Claudiu Beznea
172e7ddeea clk: at91: sam9x60: fix main rc oscillator frequency
Main RC oscillator frequency is 12MHz according to datasheet
(chapter 27.2).

Fixes: 01e2113de9 ("clk: at91: add sam9x60 pmc driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1595403506-8209-8-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:19:03 -07:00
Claudiu Beznea
35d06f7478 clk: at91: sam9x60-pll: use frac when setting frequency
In commit a436c2a447 ("clk: at91: add sam9x60 PLL driver")
the fractional part of PLL wasn't set on registers but it was
calculated and taken into account for determining div and mul
(see sam9x60_pll_get_best_div_mul()).

Fixes: a436c2a447 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-7-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:18:47 -07:00
Claudiu Beznea
390227dca8 clk: at91: sam9x60-pll: check fcore against ranges
According to datasheet the range of 600-1200MHz is for the
frequency generated by the fractional part of the PLL (namely
Fcorepllck according to datasheet). With this in mind the output
range of the PLL itself (fractional + div), taking into account
that the divider is 8 bits wide, is 600/256-1200Hz=2.3-1200MHz.

Fixes: a436c2a447 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-6-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:18:47 -07:00
Claudiu Beznea
1bef0986b1 clk: at91: sam9x60-pll: use logical or for range check
Use logical or for range check. In case bestrate is not in
characteristics->output[0].min..characteristics->output[0].max
range we should return -ERANGE.

Fixes: a436c2a447 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1595403506-8209-5-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:18:47 -07:00
Claudiu Beznea
3bf639a611 clk: at91: clk-sam9x60-pll: fix mul mask
According to datasheet mul mask is on bits 31..24.

Fixes: a436c2a447 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1595403506-8209-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:18:47 -07:00
Claudiu Beznea
83331bfcc0 clk: at91: clk-generated: check best_rate against ranges
Check best_rate against available clock ranges.

Fixes: df70aeef60 ("clk: at91: add generated clock driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1595403506-8209-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:18:47 -07:00
Claudiu Beznea
3a5c42b18a clk: at91: clk-generated: continue if __clk_determine_rate() returns error
__clk_determine_rate() may return error. Skip the current step
in case of error.

Fixes: 1a1a36d72e ("clk: at91: clk-generated: make gclk determine audio_pll rate")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1595403506-8209-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:18:47 -07:00
Ahmad Fatoum
153bc1c66a clk: at91: fix possible dead lock in new drivers
syscon_node_to_regmap() will make the created regmap get and enable the
first clock it can parse from the device tree. This clock is not needed to
access the registers and should not be enabled at that time.

Use device_node_to_regmap to resolve this as it looks up the regmap in
the same list but doesn't care about the clocks. This issue is detected
by lockdep when booting the sama5d3 with a device tree containing the
new clk bindings.

This fix already happened in 6956eb33ab ("clk: at91: fix possible
deadlock") for the drivers that had been migrated to the new clk binding
back then. This does the same for the new drivers as well.

Fixes: 01e2113de9 ("clk: at91: add sam9x60 pmc driver")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.kernel.org/r/20200703073236.23923-1-a.fatoum@pengutronix.de
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:18:42 -07:00
Mike Tipton
03111b1088 clk: Add support for enabling/disabling clocks from debugfs
For test and debug purposes, it's simple enough to enable or disable
clocks from shell. Add a new debugfs file 'clk_prepare_enable' that
calls clk_prepare_enable() when writing "1" and clk_disable_unprepare()
when writing "0".

This can have security implications, so only support it when the code
has been modified to #define CLOCK_ALLOW_WRITE_DEBUGFS.

Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Link: https://lore.kernel.org/r/20200630003024.6282-1-mdtipton@codeaurora.org
[sboyd@kernel.org: Reword commit text and remove comment update]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:03:58 -07:00
Rahul Tanwar
d310124cd9 clk: intel: Avoid unnecessary memset by improving code
memset can be avoided in a loop if the variables used are declared
inside the loop. Move such variables declaration inside the loop
to avoid memset.

Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Link: https://lore.kernel.org/r/26624b65d0e6b958c4765a406b9929d1a9ce1c2c.1594880946.git.rahul.tanwar@linux.intel.com
[sboyd@kernel.org: Drop NULL assignment that is overwritten]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 01:58:15 -07:00
Rahul Tanwar
c9e28fe649 clk: intel: Improve locking in the driver
Remove/reduce unnecessary spin locking of the code.

Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Link: https://lore.kernel.org/r/79c0f5f9f5bc512a7e2b5f3c91f6341f28b5854c.1594880946.git.rahul.tanwar@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 01:55:18 -07:00
Rahul Tanwar
8529fc0aaa clk: intel: Use devm_clk_hw_register() instead of clk_hw_register()
To ensure that clks are unregistered in case of any failure, use
devm_clk_hw_register() instead of clk_hw_register().

Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Link: https://lore.kernel.org/r/7ef7009b4e9f986fd6dfbf487c0e85de68a4ba9b.1594880946.git.rahul.tanwar@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 01:55:18 -07:00
Lori Hikichi
9f7d5042a6 clk: iproc: round clock rate to the closest
Change from 'DIV_ROUND_UP' to 'DIV_ROUND_CLOSEST' when calculating the
clock divisor in the iProc ASIU clock driver to allow to get to the
closest clock rate.

Fixes: 5fe225c105 ("clk: iproc: add initial common clock support")
Signed-off-by: Lori Hikichi <lhikichi@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Link: https://lore.kernel.org/r/20200612225212.124301-1-ray.jui@broadcom.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 01:54:18 -07:00
Jonathan Marek
28f0769c77 clk: qcom: Add graphics clock controller driver for SM8250
Add support for the graphics clock controller found on SM8250
based devices.

This is initially copied from the downstream kernel, but has
been modified to more closely match the upstream sc7180 driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-12-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 01:51:32 -07:00
Jonathan Marek
0cef71f2cc clk: qcom: Add graphics clock controller driver for SM8150
Add support for the graphics clock controller found on SM8150
based devices.

This is initially copied from the downstream kernel, but has
been modified to more closely match the upstream sc7180 driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-11-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 01:51:29 -07:00
Jonathan Marek
0638226dd0 clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers
All gpucc drivers need this, so move it to common code instead of
duplicating it in every gpucc driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-10-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 01:51:26 -07:00
Jonathan Marek
3f6b250625 clk: qcom: gcc: remove unnecessary vco_table from SM8150
The fixed alpha pll ops only use it for clamping in round_rate, which is
unnecessary. This is consistent with SM8250 GCC not using vco_table.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-6-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 01:51:14 -07:00
Jonathan Marek
d28b503c24 clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll
Lucid PCAL_DONE is different from trion.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-5-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 01:51:11 -07:00
Jonathan Marek
0b01489475 clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid
Fixed ops were already identical, this adds support for non-fixed ops by
sharing between trion and lucid.

This also changes the names for trion ops to be consistent with the rest.

Note LUCID_PCAL_DONE is renamed to TRION_PCAL_DONE because it is wrong for
lucid, LUCID_PCAL_DONE should be BIT(27). Next patch will address this.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-4-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 01:51:06 -07:00
Jonathan Marek
c8b9002f44 clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL
0x44 isn't a register offset, it is the value that goes into CAL_L_VAL.

Fixes: 548a909597 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-3-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 01:51:02 -07:00
Jonathan Marek
667f39b59b clk: qcom: gcc: fix sm8150 GPU and NPU clocks
Fix the parents and set BRANCH_HALT_SKIP. From the downstream driver it
should be a 500us delay and not skip, however this matches what was done
for other clocks that had 500us delay in downstream.

Fixes: f73a4230d5 ("clk: qcom: gcc: Add GPU and NPU clocks for SM8150")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-2-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 01:50:50 -07:00
Luca Ceresoli
3bca66b08e clk: vc5: use a dedicated struct to describe the output drivers
Reusing the generic struct vc5_hw_data for all blocks is handy. However it
implies we allocate space the div_int and div_frc fields even for the
output drivers where they are unused, and the clk_output_cfg0 and
clk_output_cfg0_mask fields for all components even though they are used
only for the output drivers.

Use a dedicated struct for the output drivers so that each block uses
exactly the fields it needs, not more.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20200723072603.1795-1-luca@lucaceresoli.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-23 15:34:21 -07:00
Adam Ford
faf29338f3 clk: vc5: Add memory check to prevent oops
When getting the names of the child nodes, kasprintf is used to
allocate memory which is used to create the string for the node
name.  Unfortunately, there is no memory check to determine
if this allocation fails, it may cause an error when trying
to get child node name.

This patch will check if the memory allocation fails, and returns
and -ENOMEM error instead of blindly moving on.

Fixes: 260249f929 ("clk: vc5: Enable addition output configurations of the Versaclock")

Suggested-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20200716122620.4538-1-aford173@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-22 18:47:57 -07:00
Colin Ian King
8200597fb1 clk: vc5: fix use of memory after it has been kfree'd
There are a several places where printing an error message of
init.name occurs after init.name has been kfree'd. Also the failure
message is duplicated each time in the code. Fix this by adding
a registration error failure path for these cases, moving the
duplicated error messages to one common point and kfree'ing init.name
only after it has been used.

Changes also shrink the object code size by 171 bytes (x86-64, gcc 9.3):

Before:
   text	   data	    bss	    dec	    hex	filename
  21057	   3960	     64	  25081	   61f9	drivers/clk/clk-versaclock5.o

After:
   text	   data	    bss	    dec	    hex	filename
  20886	   3960	     64	  24910	   614e	drivers/clk/clk-versaclock5.o

Addresses-Coverity: ("Use after free")
Fixes: f491276a51 ("clk: vc5: Allow Versaclock driver to support multiple instances")

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20200625132736.88832-1-colin.king@canonical.com
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
[sboyd@kernel.org: Drop stray newline]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-22 18:46:24 -07:00
Alex Bee
ef990bcad5 clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks
Since the loopbacktest clock is not exported and is not touched in the
driver, it has to be added to rk3188_critical_clocks to be protected from
being disabled and in order to get the emac working.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20200722161820.5316-1-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-07-22 20:05:19 +02:00
Cristian Ciocaltea
9fb961da91 clk: actions: Add Actions S500 SoC Reset Management Unit support
Add Reset Management Unit (RMU) support for Actions Semi S500 SoC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/3fba2e6f0edfac97cb8c6ce60f95c24852578eac.1593788312.git.cristian.ciocaltea@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-21 01:50:47 -07:00
Cristian Ciocaltea
b81e88dead clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC
Add support for the missing APB, DMAC and GPIO clocks in the Actions
Semi S500 SoC clock driver.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Link: https://lore.kernel.org/r/87964ae012e513597b8b4c7be2e7ac332a70087a.1593788312.git.cristian.ciocaltea@gmail.com
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-21 01:50:46 -07:00
Cristian Ciocaltea
f47ee279d2 clk: actions: Fix h_clk for Actions S500 SoC
The h_clk clock in the Actions Semi S500 SoC clock driver has an
invalid parent. Replace with the correct one.

Fixes: ed6b4795ec ("clk: actions: Add clock driver for S500 SoC")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/c57e7ebabfa970014f073b92fe95b47d3e5a70b1.1593788312.git.cristian.ciocaltea@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-21 01:50:46 -07:00
Stephen Boyd
63e95849a7 Merge branch 'clk-imx' into clk-next
* clk-imx:
  clk: imx: vf610: add CAAM clock
  clk: imx8mp: add mu root clk
2020-07-21 01:03:16 -07:00
Stephen Boyd
b396b3d206 Merge branch 'clk-amlogic' into clk-next
* clk-amlogic:
  clk: meson: meson8b: add the vclk2_en gate clock
  clk: meson: meson8b: add the vclk_en gate clock
  clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
  clk: meson: g12a: Add support for NNA CLK source clocks
  dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
2020-07-21 01:01:11 -07:00
Stephen Boyd
fca1484576 Merge branch 'clk-renesas' into clk-next
* clk-renesas:
  clk: renesas: cpg-mssr: Add r8a774e1 support
  dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1
  clk: renesas: Add r8a774e1 CPG Core Clock Definitions
  dt-bindings: power: Add r8a774e1 SYSC power domain definitions
2020-07-21 00:57:38 -07:00
Stephen Boyd
73d6bd7acb Merge branch 'clk-qcom' into clk-next
* clk-qcom:
  clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845
  ipq806x: gcc: add support for child probe
  clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static
  clk: qcom: ipq8074: Add correct index for PCIe clocks
2020-07-21 00:55:21 -07:00
Taniya Das
9c3df2b199 clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845
The display gpll0 branch clock inside GCC needs to always be enabled.
Otherwise the AHB clk (disp_cc_mdss_ahb_clk_src) for the display clk
controller (dispcc) will stop clocking while sourcing from gpll0 when
this branch inside GCC is turned off during unused clk disabling. We can
never turn this branch off because the AHB clk for the display subsystem
is needed to read/write any registers inside the display subsystem
including clk related ones. This makes this branch a really easy way to
turn off AHB access to the display subsystem and cause all sorts of
mayhem. Let's just make the clk ops keep the clk enabled forever and
ignore any attempts to disable this clk so that dispcc accesses keep
working.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reported-by: Evan Green <evgreen@chromium.org>
Link: https://lore.kernel.org/r/1594796050-14511-1-git-send-email-tdas@codeaurora.org
Fixes: 17269568f7 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180")
Fixes: 06391eddb6 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
[sboyd@kernel.org: Fill out commit text more]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-21 00:44:11 -07:00
Ansuel Smith
5ce728fa78 ipq806x: gcc: add support for child probe
Add support for child probing needed for tsens driver that share the
same regs of gcc for this platform.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Link: https://lore.kernel.org/r/20200716022817.30439-2-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-21 00:10:21 -07:00
Wei Yongjun
8607fa1691 clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static
The sparse tool complains as follows:

drivers/clk/qcom/clk-cpu-8996.c:341:19: warning:
 symbol 'cpu_msm8996_clks' was not declared. Should it be static?

This variable is not used outside of clk-cpu-8996.c, so this commit
marks it static.

Fixes: 03e342dc45 ("clk: qcom: Add CPU clock driver for msm8996")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Link: https://lore.kernel.org/r/20200714142155.35085-1-weiyongjun1@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-20 17:40:18 -07:00
Kees Cook
3f649ab728 treewide: Remove uninitialized_var() usage
Using uninitialized_var() is dangerous as it papers over real bugs[1]
(or can in the future), and suppresses unrelated compiler warnings
(e.g. "unused variable"). If the compiler thinks it is uninitialized,
either simply initialize the variable or make compiler changes.

In preparation for removing[2] the[3] macro[4], remove all remaining
needless uses with the following script:

git grep '\buninitialized_var\b' | cut -d: -f1 | sort -u | \
	xargs perl -pi -e \
		's/\buninitialized_var\(([^\)]+)\)/\1/g;
		 s:\s*/\* (GCC be quiet|to make compiler happy) \*/$::g;'

drivers/video/fbdev/riva/riva_hw.c was manually tweaked to avoid
pathological white-space.

No outstanding warnings were found building allmodconfig with GCC 9.3.0
for x86_64, i386, arm64, arm, powerpc, powerpc64le, s390x, mips, sparc64,
alpha, and m68k.

[1] https://lore.kernel.org/lkml/20200603174714.192027-1-glider@google.com/
[2] https://lore.kernel.org/lkml/CA+55aFw+Vbj0i=1TGqCR5vQkCzWJ0QxK6CernOU6eedsudAixw@mail.gmail.com/
[3] https://lore.kernel.org/lkml/CA+55aFwgbgqhbp1fkxvRKEpzyR5J8n1vKT1VZdz9knmPuXhOeg@mail.gmail.com/
[4] https://lore.kernel.org/lkml/CA+55aFz2500WfbKXAx8s67wrm9=yVJu65TpLgN_ybYNv0VEOKA@mail.gmail.com/

Reviewed-by: Leon Romanovsky <leonro@mellanox.com> # drivers/infiniband and mlx4/mlx5
Acked-by: Jason Gunthorpe <jgg@mellanox.com> # IB
Acked-by: Kalle Valo <kvalo@codeaurora.org> # wireless drivers
Reviewed-by: Chao Yu <yuchao0@huawei.com> # erofs
Signed-off-by: Kees Cook <keescook@chromium.org>
2020-07-16 12:35:15 -07:00
Kees Cook
fec61ff40b clk: spear: Remove uninitialized_var() usage
Using uninitialized_var() is dangerous as it papers over real bugs[1]
(or can in the future), and suppresses unrelated compiler warnings (e.g.
"unused variable"). If the compiler thinks it is uninitialized, either
simply initialize the variable or make compiler changes. As a precursor
to removing[2] this[3] macro[4], initialize "i" to zero. The compiler
warning was not a false positive, since clk_pll_set_rate()'s call to
clk_pll_round_rate_index() will always fail (since "prate" is NULL), so
"i" was never being initialized.

[1] https://lore.kernel.org/lkml/20200603174714.192027-1-glider@google.com/
[2] https://lore.kernel.org/lkml/CA+55aFw+Vbj0i=1TGqCR5vQkCzWJ0QxK6CernOU6eedsudAixw@mail.gmail.com/
[3] https://lore.kernel.org/lkml/CA+55aFwgbgqhbp1fkxvRKEpzyR5J8n1vKT1VZdz9knmPuXhOeg@mail.gmail.com/
[4] https://lore.kernel.org/lkml/CA+55aFz2500WfbKXAx8s67wrm9=yVJu65TpLgN_ybYNv0VEOKA@mail.gmail.com/

Fixes: 7d4998f71b ("clk: SPEAr: Vco-pll: Fix compilation warning")
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
2020-07-16 12:32:26 -07:00
Kees Cook
14dd1c3af6 clk: st: Remove uninitialized_var() usage
Using uninitialized_var() is dangerous as it papers over real bugs[1]
(or can in the future), and suppresses unrelated compiler warnings (e.g.
"unused variable"). If the compiler thinks it is uninitialized, either
simply initialize the variable or make compiler changes. As a precursor
to removing[2] this[3] macro[4], just remove this variable since it was
actually unused:

drivers/clk/st/clkgen-fsyn.c: In function ‘quadfs_set_rate’:
drivers/clk/st/clkgen-fsyn.c:793:6: warning: unused variable ‘i’ [-Wunused-variable]
  793 |  int i;
      |      ^

[1] https://lore.kernel.org/lkml/20200603174714.192027-1-glider@google.com/
[2] https://lore.kernel.org/lkml/CA+55aFw+Vbj0i=1TGqCR5vQkCzWJ0QxK6CernOU6eedsudAixw@mail.gmail.com/
[3] https://lore.kernel.org/lkml/CA+55aFwgbgqhbp1fkxvRKEpzyR5J8n1vKT1VZdz9knmPuXhOeg@mail.gmail.com/
[4] https://lore.kernel.org/lkml/CA+55aFz2500WfbKXAx8s67wrm9=yVJu65TpLgN_ybYNv0VEOKA@mail.gmail.com/

Fixes: 5f7aa9071e ("clk: st: Support for QUADFS inside ClockGenB/C/D/E/F")
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
2020-07-16 12:32:25 -07:00
Linus Torvalds
f8456690ba A couple build fixes for issues exposed this merge window and a fix for
the eMMC clk on AST2600 SoCs that fixes the rate that is calculated by
 the clk framework.
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux into master

Pull clk fixes from Stephen Boyd:
 "A couple build fixes for issues exposed this merge window and a fix
  for the eMMC clk on AST2600 SoCs that fixes the rate that is
  calculated by the clk framework"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: Specify IOMEM dependency for HSDK pll driver
  clk: AST2600: Add mux for EMMC clock
  clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER
2020-07-15 19:00:12 -07:00
Sudeep Holla
fcd2e0deae clk: scmi: Fix min and max rate when registering clocks with discrete rates
Currently we are not initializing the scmi clock with discrete rates
correctly. We fetch the min_rate and max_rate value only for clocks with
ranges and ignore the ones with discrete rates. This will lead to wrong
initialization of rate range when clock supports discrete rate.

Fix this by using the first and the last rate in the sorted list of the
discrete clock rates while registering the clock.

Link: https://lore.kernel.org/r/20200709081705.46084-2-sudeep.holla@arm.com
Fixes: 6d6a1d82ea ("clk: add support for clocks provided by SCMI")
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reported-and-tested-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-07-13 09:40:21 +01:00
Marian-Cristian Rotariu
c8a53fa1d2 clk: renesas: cpg-mssr: Add r8a774e1 support
Add support for the RZ/G2H (R8A774E1) SoC to the Renesas Clock
Pulse Generator / Module Standby and Software Reset driver.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594138692-16816-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
[geert: Mark RWDT critical, cfr. commit f23f1101ad ("clk: renesas: rcar-gen3: Mark RWDT clocks as critical")]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-07-13 10:36:33 +02:00
Stephen Boyd
5c09ea8bf3 Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: Specify IOMEM dependency for HSDK pll driver
  clk: AST2600: Add mux for EMMC clock
  clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER
2020-07-11 09:28:18 -07:00
David Gow
1e7468bd9d clk: Specify IOMEM dependency for HSDK pll driver
The HSDK pll driver uses the devm_ioremap_resource function, but does
not specify a dependency on IOMEM in Kconfig. This causes a build
failure on architectures without IOMEM, for example, UML (notably with
make allyesconfig).

Fix this by making CONFIG_CLK_HSDK depend on CONFIG_IOMEM.

Signed-off-by: David Gow <davidgow@google.com>
Link: https://lore.kernel.org/r/20200630043214.1080961-1-davidgow@google.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11 09:28:10 -07:00
Stephen Boyd
d93649dc52 Merge branch 'clk-kconfig' into clk-next
* clk-kconfig:
  clk: Drop duplicate selection in Kconfig
2020-07-11 09:28:04 -07:00
Stephen Boyd
96310398fc Merge branch 'clk-qcom' into clk-next
* clk-qcom:
  clk: qcom: smd: Add support for MSM8992/4 rpm clocks
  clk: qcom: ipq8074: Add missing clocks for pcie
  dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe
2020-07-11 09:27:58 -07:00
Andy Shevchenko
b545b9c393 clk: Drop duplicate selection in Kconfig
There is no need to select RATIONAL in individual drivers,
since common clock symbol does it already.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200614115140.41262-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11 09:24:40 -07:00
Konrad Dybcio
b429784499 clk: qcom: smd: Add support for MSM8992/4 rpm clocks
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8992,
MSM8994 (and APQ variants) for clients to vote on.

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200623230018.303776-1-konradybcio@gmail.com
[sboyd@kernel.org: Fixed up binding numbers]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11 09:19:24 -07:00
Eddie James
c2407ab3bd clk: AST2600: Add mux for EMMC clock
The EMMC clock can be derived from either the HPLL or the MPLL. Register
a clock mux so that the rate is calculated correctly based upon the
parent.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20200709195706.12741-2-eajames@linux.ibm.com
Acked-by: Joel Stanley <joel@jms.id.au>
Fixes: d3d04f6c33 ("clk: Add support for AST2600 SoC")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11 09:15:33 -07:00
Sivaprakash Murugesan
f0cfcf1ade clk: qcom: ipq8074: Add missing clocks for pcie
Add missing clocks and resets for pcie port0 of ipq8074 devices.

Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1593940680-2363-5-git-send-email-sivaprak@codeaurora.org
[sboyd@kernel.org: Make freq table static const]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11 09:12:36 -07:00
Nathan Chancellor
8e3709d7e3 clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER
When building arm32 allmodconfig:

ld.lld: error: undefined symbol: ap_cp_unique_name
>>> referenced by ap-cpu-clk.c
>>>               clk/mvebu/ap-cpu-clk.o:(ap_cpu_clock_probe) in archive drivers/built-in.a

ap_cp_unique_name is only compiled into the kernel image when
CONFIG_ARMADA_AP_CP_HELPER is selected (as it is not user selectable).
However, CONFIG_ARMADA_AP_CPU_CLK does not select it.

This has been a problem since the driver was added to the kernel but it
was not built before commit c318ea261749 ("cpufreq: ap806: fix cpufreq
driver needs ap cpu clk") so it was never noticed.

Fixes: f756e362d9 ("clk: mvebu: add CPU clock driver for Armada 7K/8K")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Link: https://lore.kernel.org/r/20200701201128.2448427-1-natechancellor@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11 09:07:06 -07:00
Stephen Boyd
df5b333e0a Merge branch 'clk-renesas' into clk-next
* clk-renesas:
  clk: renesas: rzg2: Mark RWDT clocks as critical
  clk: renesas: rcar-gen3: Mark RWDT clocks as critical
  clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot
  dt-bindings: clock: renesas: cpg: Convert to json-schema
2020-07-10 17:19:34 -07:00
Stephen Boyd
2a05eaa752 Merge branch 'clk-https' into clk-next
* clk-https:
  Replace HTTP links with HTTPS ones: Common CLK framework
2020-07-10 17:15:50 -07:00
Alexander A. Klimov
5f1d8970d4 Replace HTTP links with HTTPS ones: Common CLK framework
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.

Deterministic algorithm:
For each file:
  If not .svg:
    For each line:
      If doesn't contain `\bxmlns\b`:
        For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
          If both the HTTP and HTTPS versions
          return 200 OK and serve the same content:
            Replace HTTP with HTTPS.

Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Link: https://lore.kernel.org/r/20200703175114.15027-1-grandmaster@al2klimov.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-10 17:15:34 -07:00
Stephen Boyd
d39fc26556 Merge branch 'clk-qcom' into clk-next
- Enable CPU clks on Qualcomm MSM8996 SoCs

* clk-qcom:
  clk: qcom: Add CPU clock driver for msm8996
  dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996
  soc: qcom: Separate kryo l2 accessors from PMU driver
  clk: qcom: Fix return value check in apss_ipq6018_probe()
2020-07-10 17:14:55 -07:00
Loic Poulain
03e342dc45 clk: qcom: Add CPU clock driver for msm8996
Each of the CPU clusters (Power and Perf) on msm8996 are
clocked via 2 PLLs, a primary and alternate. There are also
2 Mux'es, a primary and secondary all connected together
as shown below

                             +-------+
              XO             |       |
          +------------------>0      |
                             |       |
                   PLL/2     | SMUX  +----+
                     +------->1      |    |
                     |       |       |    |
                     |       +-------+    |    +-------+
                     |                    +---->0      |
                     |                         |       |
+---------------+    |             +----------->1      | CPU clk
|Primary PLL    +----+ PLL_EARLY   |           |       +------>
|               +------+-----------+    +------>2 PMUX |
+---------------+      |                |      |       |
                       |   +------+     |   +-->3      |
                       +--^+  ACD +-----+   |  +-------+
+---------------+          +------+         |
|Alt PLL        |                           |
|               +---------------------------+
+---------------+         PLL_EARLY

The primary PLL is what drives the CPU clk, except for times
when we are reprogramming the PLL itself (for rate changes) when
we temporarily switch to an alternate PLL. A subsequent patch adds
support to switch between primary and alternate PLL during rate
changes.

The primary PLL operates on a single VCO range, between 600MHz
and 3GHz. However the CPUs do support OPPs with frequencies
between 300MHz and 600MHz. In order to support running the CPUs
at those frequencies we end up having to lock the PLL at twice
the rate and drive the CPU clk via the PLL/2 output and SMUX.

So for frequencies above 600MHz we follow the following path
 Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
and for frequencies between 300MHz and 600MHz we follow
 Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk

ACD stands for Adaptive Clock Distribution and is used to
detect voltage droops.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Rajendra Nayak: Initial RFC - https://lkml.org/lkml/2016/9/29/84

Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
Ilia Lin:  - reworked clock registering
           - Added clock-tree diagram
           - non-builtin support
           - clock notifier on rate change
           - https://lkml.org/lkml/2018/5/24/123

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Loic Poulain: - fixed driver remove / clk deregistering
              - Removed useless memory barriers
              - devm usage when possible
              - Fixed Kconfig depends

Link: https://lore.kernel.org/r/1593766185-16346-3-git-send-email-loic.poulain@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-10 17:09:20 -07:00
Martin Blumenstingl
2568528f55 clk: meson: meson8b: add the vclk2_en gate clock
HHI_VIID_CLK_CNTL[19] is not part of the public S805 datasheet. However,
the GXBB driver defines this bit as a gate called "vclk2" and in the
3.10 kernel GPL code dump the following line can found:
  WRITE_LCD_CBUS_REG_BITS(HHI_VIID_CLK_CNTL, 0, 19, 1); //disable vclk2_en

Add this gate clock to the Meson8/Meson8b/Meson8m2 clock controller to
complete the VCLK2 clock tree.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200629203904.2989007-3-martin.blumenstingl@googlemail.com
2020-07-09 11:37:44 +02:00
Martin Blumenstingl
e653b41131 clk: meson: meson8b: add the vclk_en gate clock
HHI_VID_CLK_CNTL[19] is documented as CLK_EN0. This description is the
same in the public S912 datasheet and the GXBB driver calls this gate
"vclk". Add this gate clock to the Meson8/Meson8b/Meson8m2 clock
controller because it's needed to make the video output work.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200629203904.2989007-2-martin.blumenstingl@googlemail.com
2020-07-09 11:37:43 +02:00
Robin Murphy
465931e708 clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328"
This reverts commit 82f4b67f01.

According to a subsequent revert in the vendor kernel, the original
change was based on unclear documentation and was in fact incorrect.

Emprically, my board's HS200 eMMC at 200MHZ apparently gets lucky with a
phase where this had no impact, but limiting max-frequency to 150MHz to
match the nominal capability of the I/O pins made it virtually unusable,
constantly throwing errors and retuning. With this revert, it starts
behaving perfectly at 150MHz too.

Fixes: 82f4b67f01 ("clk: rockchip: fix wrong mmc sample phase shift for rk3328")
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://lore.kernel.org/r/c80eb52e34c03f817586b6b7912fbd4e31be9079.1589475794.git.robin.murphy@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-07-08 16:22:10 +02:00
Heiko Stuebner
0a7f99aad2 clk: rockchip: use separate compatibles for rk3288w-cru
Commit 1627f68363 ("clk: rockchip: Handle clock tree for rk3288w variant")
added the check for rk3288w-specific clock-tree changes but in turn would
require a double-compatible due to re-using the main rockchip,rk3288-cru
compatible as entry point.

The binding change actually describes the compatibles as one or the other
so adapt the code accordingly and add a real second entry-point for the
clock controller.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # rock-pi-n8
Link: https://lore.kernel.org/r/20200703154948.260369-1-heiko@sntech.de
2020-07-05 12:18:29 +02:00
Wei Yongjun
dbb988b4e7 clk: qcom: Fix return value check in apss_ipq6018_probe()
In case of error, the function dev_get_regmap() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.

Fixes: 5e77b4ef1b ("clk: qcom: Add ipq6018 apss clock controller")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Link: https://lore.kernel.org/r/20200628023055.50608-1-weiyongjun1@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-29 14:15:34 -07:00
Stephen Boyd
12ef3933b4 Merge branch 'clk-bcm' into clk-next
- Make defines for bcm63xx-gate clks to use in DT
 - Support gate clks on BCM6318 SoCs
 - Add HDMI clks for BCM2711 SoCs
 - Support BCM2711 SoC firmware clks

* clk-bcm: (42 commits)
  clk: bcm: dvp: Add missing module informations
  clk: bcm: rpi: Remove the quirks for the CPU clock
  clk: bcm2835: Don't cache the PLLB rate
  clk: bcm2835: Allow custom CCF flags for the PLLs
  Revert "clk: bcm2835: remove pllb"
  clk: bcm: rpi: Give firmware clocks a name
  clk: bcm: rpi: Discover the firmware clocks
  clk: bcm: rpi: Add an enum for the firmware clocks
  clk: bcm: rpi: Add DT provider for the clocks
  clk: bcm: rpi: Make the PLLB registration function return a clk_hw
  clk: bcm: rpi: Split pllb clock hooks
  clk: bcm: rpi: Rename is_prepared function
  clk: bcm: rpi: Pass the clocks data to the firmware function
  clk: bcm: rpi: Add clock id to data
  clk: bcm: rpi: Create a data structure for the clocks
  clk: bcm: rpi: Use CCF boundaries instead of rolling our own
  clk: bcm: rpi: Make sure the clkdev lookup is removed
  clk: bcm: rpi: Switch to clk_hw_register_clkdev
  clk: bcm: rpi: Remove pllb_arm_lookup global pointer
  clk: bcm: rpi: Make sure pllb_arm is removed
  ...
2020-06-26 11:58:51 -07:00
Maxime Ripard
eb46f547a2 clk: bcm: dvp: Add missing module informations
The driver for the DVP controller in the BCM2711 was missing the MODULE_*
macros resulting in a modpost warning at compilation.

Fixes: 1bc9597271 ("clk: bcm: Add BCM2711 DVP driver")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200626112513.90816-1-maxime@cerno.tech
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-26 11:58:21 -07:00
Vincent Chen
d0a5fdf4cc
clk: sifive: allocate sufficient memory for struct __prci_data
The (struct __prci_data).hw_clks.hws is an array with dynamic elements.
Using struct_size(pd, hw_clks.hws, ARRAY_SIZE(__prci_init_clocks))
instead of sizeof(*pd) to get the correct memory size of
struct __prci_data for sifive/fu540-prci. After applying this
modifications, the kernel runs smoothly with CONFIG_SLAB_FREELIST_RANDOM
enabled on the HiFive unleashed board.

Fixes: 30b8e27e3b ("clk: sifive: add a driver for the SiFive FU540 PRCI IP block")
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-06-25 15:04:13 -07:00
Martin Blumenstingl
d4db5721f3 clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't
know the relation between this clock and RGMII Ethernet. It turns out
that fclk_div2 is used as "timing adjustment clock" to generate the RX
delay on the MAC side - which was enabled by u-boot on Odriod-C1. When
using the RX delay on the PHY side or not using a RX delay at all then
this clock can be disabled.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200620161422.24114-1-martin.blumenstingl@googlemail.com
2020-06-24 12:14:30 +02:00
Stephen Boyd
7aae3c161e Merge branch 'clk-vc5' into clk-next
* clk-vc5:
  clk: vc5: Enable addition output configurations of the Versaclock
  dt: Add additional option bindings for IDT VersaClock
  clk: vc5: Allow Versaclock driver to support multiple instances
2020-06-23 12:12:43 -07:00
Andrey Smirnov
018e430834 clk: imx: vf610: add CAAM clock
According to Vybrid Security RM, CCM_CCGR11[CG176] can be used to gate
CAAM ipg clock.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-imx@nxp.com
Tested-by: Chris Healy <cphealy@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-06-23 15:10:05 +08:00
Peng Fan
94ae59ac5d clk: imx8mp: add mu root clk
Add mu root clk for mu mailbox usage.

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-06-23 15:10:05 +08:00
Adam Ford
260249f929 clk: vc5: Enable addition output configurations of the Versaclock
The existing driver is expecting the Versaclock to be pre-programmed,
and only sets the output frequency.  Unfortunately, not all devices
are pre-programmed, and the Versaclock chip has more options beyond
just the frequency.

This patch enables the following additional features:

   - Programmable voltage: 1.8V, 2.5V, or 3.3V​
   - Slew Percentage of normal: 85%, 90%, or 100%
   - Output Type: LVPECL, CMOS, HCSL, or LVDS

Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20200603154329.31579-3-aford173@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22 19:04:58 -07:00
Adam Ford
f491276a51 clk: vc5: Allow Versaclock driver to support multiple instances
Currently, the Versaclock driver is only expecting one instance and
uses hard-coded names for the various clock names.  Unfortunately,
this is a problem when there is more than one instance of the driver,
because the subsequent instantiations of the driver use the identical
name.  Each clock after the fist fails to load, because the clock
subsystem cannot handle two clocks with identical name.

This patch removes the hard-coded name arrays and uses kasprintf to
assign clock names based on names of their respective node and parent
node which gives each clock a unique identifying name.

For a verasaclock node with a name like:
   versaclock5: versaclock_som@6a

The updated clock names would appear like:
    versaclock_som.mux
       versaclock_som.out0_sel_i2cb
       versaclock_som.pfd
          versaclock_som.pll
             versaclock_som.fod3
                versaclock_som.out4
             versaclock_som.fod2
                versaclock_som.out3
             versaclock_som.fod1
                versaclock_som.out2
             versaclock_som.fod0
                versaclock_som.out1

Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20200603154329.31579-1-aford173@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22 19:04:58 -07:00
Stephen Boyd
ef01ab612b Merge branch 'clk-qcom' into clk-next
- Enable CPU clks on Qualcomm IPQ6018 SoCs

* clk-qcom:
  clk: qcom: smd: Add support for MSM8936 rpm clocks
  dt-bindings: clock: rpmcc: Document MSM8936 compatible
  clk: qcom: smd: Add support for SDM660 rpm clocks
  clk: qcom: Add ipq6018 apss clock controller
  clk: qcom: Add DT bindings for ipq6018 apss clock controller
  clk: qcom: Add ipq apss pll driver
  dt-bindings: clock: add ipq6018 a53 pll compatible
2020-06-22 19:02:18 -07:00
Vincent Knecht
59390282b7 clk: qcom: smd: Add support for MSM8936 rpm clocks
Add missing definition of rpm clk for msm8936 soc (also used by msm8939)

Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
Link: https://lore.kernel.org/r/20200613072745.1249003-2-vincent.knecht@mailoo.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22 19:01:25 -07:00
Ulrich Hecht
52bc5ea6ed clk: renesas: rzg2: Mark RWDT clocks as critical
Ensures RWDT remains alert throughout the boot process if enabled.

This patch applies the change to the following SoCs: r8a774a1,
r8a774b1 and r8a774c0.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20200616162626.27944-4-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-22 16:54:32 +02:00
Ulrich Hecht
f23f1101ad clk: renesas: rcar-gen3: Mark RWDT clocks as critical
Ensures RWDT remains alert throughout the boot process if enabled.

This patch applies the change to the following SoCs: r8a77950, r8a77951,
r8a77960, r8a77961, r8a77965, r8a77970, r8a77980, r8a77990 and r8a77995.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20200616162626.27944-3-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-22 16:53:49 +02:00
Ulrich Hecht
ed4a11807d clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot
This allows us to add the RWDT clock to the list of critical clocks without
keeping it enabled needlessly if not used.

Changing the semantics of crit_mod_clks in this way is safe for the current
user (INTC-AP) because it is never off at boot time.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20200616162626.27944-2-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-06-22 16:53:40 +02:00
Konrad Dybcio
b608013ac5 clk: qcom: smd: Add support for SDM660 rpm clocks
Add rpm smd clocks, PMIC and bus clocks which are required on
SDM630/660 (and APQ variants) for clients to vote on.

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200622090252.36568-1-konradybcio@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22 02:11:38 -07:00
Stephen Boyd
9ebc0617d6 Merge branch 'clk-doc' into clk-next
* clk-doc:
  clk: add function documentation for clk_hw_round_rate()
2020-06-22 02:09:43 -07:00
Sarang Mairal
e8c849c2a8 clk: add function documentation for clk_hw_round_rate()
Information about usage and prerequisites for this API.

Signed-off-by: Sarang Mairal <sarangmairal@gmail.com>
Link: https://lore.kernel.org/r/20200611021941.786-2-sarangmairal@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22 02:04:15 -07:00
Sivaprakash Murugesan
5e77b4ef1b clk: qcom: Add ipq6018 apss clock controller
The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL
and xo which are connected to a mux and enable block.

Add support for the mux and enable block which feeds the CPU on ipq6018
devices.

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1592800092-20533-5-git-send-email-sivaprak@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22 00:21:59 -07:00
Sivaprakash Murugesan
ecd2bacfbb clk: qcom: Add ipq apss pll driver
The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL.
Add support for the apss pll found on ipq based devices which can
support CPU frequencies above 1Ghz.

Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1592800092-20533-3-git-send-email-sivaprak@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22 00:21:59 -07:00
Dinh Nguyen
44a7f3e822 clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
Preliminary documentation documented the mpu_l2ram_clk, but since then,
the mpu_l2ram_clk is no longer documented. It's now referred to as
mpu_ccu_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20200616202417.14376-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19 19:27:33 -07:00
Dinh Nguyen
6f3bcf56f8 clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main
clock that is feeding the NAND IP and correct it's parent to be the
l4_mp_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20200616202417.14376-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19 19:27:33 -07:00
Maxime Ripard
56643d9ad2 clk: bcm: rpi: Remove the quirks for the CPU clock
The CPU clock has had so far a bunch of quirks to expose the clock tree
properly, but since we reverted to exposing them through the MMIO driver,
we can remove that code from the firmware driver.

Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/acdf820c2f78a25dd7480a0c018b8b387acd013e.1592210452.git-series.maxime@cerno.tech
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19 17:21:18 -07:00
Maxime Ripard
0d46fafc03 clk: bcm2835: Don't cache the PLLB rate
The PLLB rate will be changed through the firmware clocks drivers and will
change behind this drivers' back, so we don't want to cache the rate.

Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/9864daba2f584ed49aee5ed1d2f4d48507c58197.1592210452.git-series.maxime@cerno.tech
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19 17:21:18 -07:00