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7233 Commits

Author SHA1 Message Date
Lee Jones
4151737120 clk: rockchip: Demote non-conformant kernel-doc headers in main clock code
Fixes the following W=1 kernel build warning(s):

 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'name' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'parent_names' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'num_parents' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'base' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'muxdiv_offset' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'mux_shift' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'mux_width' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'mux_flags' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_offset' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_shift' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_width' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_flags' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'div_table' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'gate_offset' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'gate_shift' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'gate_flags' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'flags' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:45: warning: Function parameter or member 'lock' not described in 'rockchip_clk_register_branch'
 drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'hw' not described in 'rockchip_fractional_approximation'
 drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'rate' not described in 'rockchip_fractional_approximation'
 drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'parent_rate' not described in 'rockchip_fractional_approximation'
 drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'm' not described in 'rockchip_fractional_approximation'
 drivers/clk/rockchip/clk.c:180: warning: Function parameter or member 'n' not described in 'rockchip_fractional_approximation'

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Xing Zheng <zhengxing@rock-chips.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210120093040.1719407-2-lee.jones@linaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-26 00:24:04 +01:00
Linus Torvalds
8653b778e4 The core framework got some nice improvements this time around. We gained the
ability to get struct clk pointers from a struct clk_hw so that clk providers
 can consume the clks they provide, if they need to do something like that. This
 has been a long missing part of the clk provider API that will help us move
 away from exposing a struct clk pointer in the struct clk_hw. Tracepoints are
 added for the clk_set_rate() "range" functions, similar to the tracepoints we
 already have for clk_set_rate() and we added a column to debugfs to help
 developers understand the hardware enable state of clks in case firmware or
 bootloader state is different than what is expected. Overall the core changes
 are mostly improving the clk driver writing experience.
 
 At the driver level, we have the usual collection of driver updates and new
 drivers for new SoCs. This time around the Qualcomm folks introduced a good
 handful of clk drivers for various parts of three or four SoCs. The SiFive
 folks added a new clk driver for their FU740 SoCs, coming in second on the
 diffstat and then Atmel AT91 and Amlogic SoCs had lots of work done after that
 for various new features. One last thing to note in the driver area is that the
 i.MX driver has gained a new binding to support SCU clks after being on the
 list for many months. It uses a two cell binding which is sort of rare in clk
 DT bindings. Beyond that we have the usual set of driver fixes and tweaks that
 come from more testing and finding out that some configuration was wrong or
 that a driver could support being built as a module.
 
 Core:
  - Add some trace points for clk_set_rate() "range" functions
  - Add hardware enable information to clk_summary debugfs
  - Replace clk-provider.h with of_clk.h when possible
  - Add devm variant of clk_notifier_register()
  - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw
 
 New Drivers:
  - Bindings for Canaan K210 SoC clks
  - Support for SiFive FU740 PRCI
  - Camera clks on Qualcomm SC7180 SoCs
  - GCC and RPMh clks on Qualcomm SDX55 SoCs
  - RPMh clks on Qualcomm SM8350 SoCs
  - LPASS clks on Qualcomm SM8250 SoCs
 
 Updates:
  - DVFS support for AT91 clk driver
  - Update git repo branch for Renesas clock drivers
  - Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U
  - Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E
  - Stop using __raw_*() I/O accessors in Renesas clk drivers
  - One more conversion of DT bindings to json-schema
  - Make i.MX clk-gate2 driver more flexible
  - New two cell binding for i.MX SCU clks
  - Drop of_match_ptr() in i.MX8 clk drivers
  - Add arch dependencies for Rockchip clk drivers
  - Fix i2s on Rockchip rk3066
  - Add MIPI DSI clks on Amlogic axg and g12 SoCs
  - Support modular builds of Amlogic clk drivers
  - Fix an Amlogic Video PLL clock dependency
  - Samsung Kconfig dependencies updates for better compile test coverage
  - Refactoring of the Samsung PLL clocks driver
  - Small Tegra driver cleanups
  - Minor fixes to Ingenic and VC5 clk drivers
  - Cleanup patches to remove unused variables and plug memory leaks
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The core framework got some nice improvements this time around. We
  gained the ability to get struct clk pointers from a struct clk_hw so
  that clk providers can consume the clks they provide, if they need to
  do something like that. This has been a long missing part of the clk
  provider API that will help us move away from exposing a struct clk
  pointer in the struct clk_hw. Tracepoints are added for the
  clk_set_rate() "range" functions, similar to the tracepoints we
  already have for clk_set_rate() and we added a column to debugfs to
  help developers understand the hardware enable state of clks in case
  firmware or bootloader state is different than what is expected.
  Overall the core changes are mostly improving the clk driver writing
  experience.

  At the driver level, we have the usual collection of driver updates
  and new drivers for new SoCs. This time around the Qualcomm folks
  introduced a good handful of clk drivers for various parts of three or
  four SoCs. The SiFive folks added a new clk driver for their FU740
  SoCs, coming in second on the diffstat and then Atmel AT91 and Amlogic
  SoCs had lots of work done after that for various new features. One
  last thing to note in the driver area is that the i.MX driver has
  gained a new binding to support SCU clks after being on the list for
  many months. It uses a two cell binding which is sort of rare in clk
  DT bindings. Beyond that we have the usual set of driver fixes and
  tweaks that come from more testing and finding out that some
  configuration was wrong or that a driver could support being built as
  a module.

  Summary:

  Core:
   - Add some trace points for clk_set_rate() "range" functions
   - Add hardware enable information to clk_summary debugfs
   - Replace clk-provider.h with of_clk.h when possible
   - Add devm variant of clk_notifier_register()
   - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw

  New Drivers:
   - Bindings for Canaan K210 SoC clks
   - Support for SiFive FU740 PRCI
   - Camera clks on Qualcomm SC7180 SoCs
   - GCC and RPMh clks on Qualcomm SDX55 SoCs
   - RPMh clks on Qualcomm SM8350 SoCs
   - LPASS clks on Qualcomm SM8250 SoCs

  Updates:
   - DVFS support for AT91 clk driver
   - Update git repo branch for Renesas clock drivers
   - Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U
   - Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E
   - Stop using __raw_*() I/O accessors in Renesas clk drivers
   - One more conversion of DT bindings to json-schema
   - Make i.MX clk-gate2 driver more flexible
   - New two cell binding for i.MX SCU clks
   - Drop of_match_ptr() in i.MX8 clk drivers
   - Add arch dependencies for Rockchip clk drivers
   - Fix i2s on Rockchip rk3066
   - Add MIPI DSI clks on Amlogic axg and g12 SoCs
   - Support modular builds of Amlogic clk drivers
   - Fix an Amlogic Video PLL clock dependency
   - Samsung Kconfig dependencies updates for better compile test coverage
   - Refactoring of the Samsung PLL clocks driver
   - Small Tegra driver cleanups
   - Minor fixes to Ingenic and VC5 clk drivers
   - Cleanup patches to remove unused variables and plug memory leaks"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits)
  dt-binding: clock: Document canaan,k210-clk bindings
  dt-bindings: Add Canaan vendor prefix
  clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"
  clk: ingenic: Fix divider calculation with div tables
  clk: sunxi-ng: Make sure divider tables have sentinel
  clk: s2mps11: Fix a resource leak in error handling paths in the probe function
  clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
  clk: si5351: Wait for bit clear after PLL reset
  clk: at91: sam9x60: remove atmel,osc-bypass support
  clk: at91: sama7g5: register cpu clock
  clk: at91: clk-master: re-factor master clock
  clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
  clk: at91: sama7g5: decrease lower limit for MCK0 rate
  clk: at91: sama7g5: remove mck0 from parent list of other clocks
  clk: at91: clk-sam9x60-pll: allow runtime changes for pll
  clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
  clk: at91: clk-master: add 5th divisor for mck master
  clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
  dt-bindings: clock: at91: add sama7g5 pll defines
  clk: at91: sama7g5: fix compilation error
  ...
2020-12-21 10:39:37 -08:00
Stephen Boyd
abe7e32f1d Merge branches 'clk-ingenic', 'clk-vc5', 'clk-cleanup', 'clk-canaan' and 'clk-marvell' into clk-next
- Bindings for Canaan K210 SoC clks

* clk-ingenic:
  clk: ingenic: Fix divider calculation with div tables

* clk-vc5:
  clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"

* clk-cleanup:
  clk: sunxi-ng: Make sure divider tables have sentinel
  clk: s2mps11: Fix a resource leak in error handling paths in the probe function
  clk: bcm: dvp: Add MODULE_DEVICE_TABLE()
  clk: bcm: dvp: drop a variable that is assigned to only

* clk-canaan:
  dt-binding: clock: Document canaan,k210-clk bindings
  dt-bindings: Add Canaan vendor prefix

* clk-marvell:
  clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
2020-12-20 17:18:05 -08:00
Stephen Boyd
b53a1603b4 Merge branches 'clk-ti', 'clk-analog', 'clk-trace', 'clk-at91' and 'clk-silabs' into clk-next
- Add some trace points for clk_set_rate() "range" functions
 - DVFS support for AT91 clk driver

* clk-ti:
  clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs
  clk: ti: Fix memleak in ti_fapll_synth_setup

* clk-analog:
  clk: axi-clkgen: move the OF table at the bottom of the file
  clk: axi-clkgen: wrap limits in a struct and keep copy on the state object
  dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format

* clk-trace:
  clk: Trace clk_set_rate() "range" functions

* clk-at91:
  clk: at91: sam9x60: remove atmel,osc-bypass support
  clk: at91: sama7g5: register cpu clock
  clk: at91: clk-master: re-factor master clock
  clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
  clk: at91: sama7g5: decrease lower limit for MCK0 rate
  clk: at91: sama7g5: remove mck0 from parent list of other clocks
  clk: at91: clk-sam9x60-pll: allow runtime changes for pll
  clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
  clk: at91: clk-master: add 5th divisor for mck master
  clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
  dt-bindings: clock: at91: add sama7g5 pll defines
  clk: at91: sama7g5: fix compilation error

* clk-silabs:
  clk: si5351: Wait for bit clear after PLL reset
2020-12-20 17:17:51 -08:00
Stephen Boyd
699eda2814 Merge branches 'clk-tegra', 'clk-imx', 'clk-sifive', 'clk-mediatek' and 'clk-summary' into clk-next
- Support for SiFive FU740 PRCI
 - Add hardware enable information to clk_summary debugfs

* clk-tegra:
  clk: tegra: Fix duplicated SE clock entry
  clk: tegra: bpmp: Clamp clock rates on requests
  clk: tegra: Do not return 0 on failure

* clk-imx: (24 commits)
  clk: imx: scu: remove the calling of device_is_bound
  clk: imx: scu: Make pd_np with static keyword
  clk: imx8mq: drop of_match_ptr from of_device_id table
  clk: imx8mp: drop of_match_ptr from of_device_id table
  clk: imx8mn: drop of_match_ptr from of_device_id table
  clk: imx8mm: drop of_match_ptr from of_device_id table
  clk: imx: gate2: Remove unused variable ret
  clk: imx: gate2: Add locking in is_enabled op
  clk: imx: gate2: Add cgr_mask for more flexible number of control bits
  clk: imx: gate2: Check if clock is enabled against cgr_val
  clk: imx: gate2: Keep the register writing in on place
  clk: imx: gate2: Remove the IMX_CLK_GATE2_SINGLE_BIT special case
  clk: imx: scu: fix build break when compiled as modules
  clk: imx: remove redundant assignment to pointer np
  clk: imx: remove unneeded semicolon
  clk: imx: lpcg: add suspend/resume support
  clk: imx: clk-imx8qxp-lpcg: add runtime pm support
  clk: imx: lpcg: allow lpcg clk to take device pointer
  clk: imx: imx8qxp-lpcg: add parsing clocks from device tree
  clk: imx: scu: add suspend/resume support
  ...

* clk-sifive:
  clk: sifive: Add clock enable and disable ops
  clk: sifive: Fix the wrong bit field shift
  clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
  clk: sifive: Use common name for prci configuration
  clk: sifive: Extract prci core to common base
  dt-bindings: fu740: prci: add YAML documentation for the FU740 PRCI

* clk-mediatek:
  clk: mediatek: Make mtk_clk_register_mux() a static function

* clk-summary:
  clk: Add hardware-enable column to clk summary
2020-12-20 17:17:37 -08:00
Stephen Boyd
d240d4c205 Merge branches 'clk-amlogic', 'clk-rockchip', 'clk-of', 'clk-freescale' and 'clk-unused' into clk-next
- Replace clk-provider.h with of_clk.h when possible

* clk-amlogic:
  clk: meson: g12a: add MIPI DSI Host Pixel Clock
  dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings
  clk: meson: enable building as modules
  clk: meson: Kconfig: fix dependency for G12A
  clk: meson: axg: add MIPI DSI Host clock
  clk: meson: axg: add Video Clocks
  dt-bindings: clk: axg-clkc: add MIPI DSI Host clock binding
  dt-bindings: clk: axg-clkc: add Video Clocks

* clk-rockchip:
  clk: rockchip: fix i2s gate bits on rk3066 and rk3188
  clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks
  clk: rockchip: Remove redundant null check before clk_prepare_enable
  clk: rockchip: Add appropriate arch dependencies

* clk-of:
  xtensa: Replace <linux/clk-provider.h> by <linux/of_clk.h>
  sh: boards: Replace <linux/clk-provider.h> by <linux/of_clk.h>

* clk-freescale:
  clk: fsl-flexspi: new driver
  dt-bindings: clock: document the fsl-flexspi-clk device
  clk: divider: add devm_clk_hw_register_divider_table()
  clk: qoriq: provide constants for the type
  clk: fsl-sai: use devm_clk_hw_register_composite_pdata()
  clk: composite: add devm_clk_hw_register_composite_pdata()
  clk: fsl-sai: fix memory leak
  clk: qoriq: Add platform dependencies

* clk-unused:
  clk: scpi: mark scpi_clk_match as maybe unused
  clk: pwm: drop of_match_ptr from of_device_id table
2020-12-20 17:17:25 -08:00
Stephen Boyd
23cae54f52 Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', 'clk-renesas' and 'clk-samsung' into clk-next
- Camera clks on Qualcomm SC7180 SoCs
 - GCC and RPMh clks on Qualcomm SDX55 SoCs
 - RPMh clks on Qualcomm SM8350 SoCs
 - LPASS clks on Qualcomm SM8250 SoCs
 - Add devm variant of clk_notifier_register()
 - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw

* clk-doc:
  clk: fix a kernel-doc markup

* clk-qcom: (27 commits)
  clk: qcom: rpmh: add support for SM8350 rpmh clocks
  dt-bindings: clock: Add RPMHCC bindings for SM8350
  clk: qcom: lpasscc: Introduce pm autosuspend for SC7180
  clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2
  clk: qcom: gcc-sc7180: Use floor ops for sdcc clks
  clk: qcom: Add GDSC support for SDX55 GCC
  dt-bindings: clock: Add GDSC in SDX55 GCC
  clk: qcom: Add support for SDX55 RPMh clocks
  dt-bindings: clock: Introduce RPMHCC bindings for SDX55
  clk: qcom: Add SDX55 GCC support
  dt-bindings: clock: Add SDX55 GCC clock bindings
  clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic"
  clk: qcom: rpmh: Add CE clock on sdm845.
  dt-bindings: clock: Add entry for crypto engine RPMH clock resource
  clk: qcom: dispcc-sm8250: handle MMCX power domain
  clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones
  clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init()
  clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocks
  clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks
  dt-bindings: clock: Add support for LPASS Always ON Controller
  ...

* clk-simplify:
  clk: remove unneeded dead-store initialization

* clk-hw:
  clk: meson: g12: use devm variant to register notifiers
  clk: add devm variant of clk_notifier_register
  clk: meson: g12: drop use of __clk_lookup()
  clk: add api to get clk consumer from clk_hw
  clk: avoid devm_clk_release name clash

* clk-renesas:
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema
  clk: renesas: sh73a0: Stop using __raw_*() I/O accessors
  clk: renesas: r8a774c0: Add RPC clocks
  clk: renesas: r8a779a0: Fix R and OSC clocks
  clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv
  clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get()
  clk: renesas: r8a774b1: Add RPC clocks
  clk: renesas: r8a774a1: Add RPC clocks
  clk: renesas: r8a779a0: Add VIN clocks
  clk: renesas: r8a779a0: Add CSI4[0-3] clocks
  MAINTAINERS: Update git repo for Renesas clock drivers
  clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static
  clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI

* clk-samsung:
  clk: samsung: Prevent potential endless loop in the PLL ops
  clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
2020-12-20 17:17:01 -08:00
Geert Uytterhoeven
4b003f5fca clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"
Commit 45c940184b ("dt-bindings: clk: versaclock5: convert to
yaml") accidentally changed "idt,voltage-microvolts" to
"idt,voltage-microvolt" in the DT bindings, while the driver still used
the former.

Update the driver to match the bindings, as
Documentation/devicetree/bindings/property-units.txt actually recommends
using "microvolt".

Fixes: 260249f929 ("clk: vc5: Enable addition output configurations of the Versaclock")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201218125253.3815567-1-geert+renesas@glider.be
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 16:08:51 -08:00
Paul Cercueil
11a163f2c7 clk: ingenic: Fix divider calculation with div tables
The previous code assumed that a higher hardware value always resulted
in a bigger divider, which is correct for the regular clocks, but is
an invalid assumption when a divider table is provided for the clock.

Perfect example of this is the PLL0_HALF clock, which applies a /2
divider with the hardware value 0, and a /1 divider otherwise.

Fixes: a9fa2893fc ("clk: ingenic: Add support for divider tables")
Cc: <stable@vger.kernel.org> # 5.2
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 16:04:58 -08:00
Jernej Skrabec
48f68de00c clk: sunxi-ng: Make sure divider tables have sentinel
Two clock divider tables are missing sentinel at the end. Effect of that
is that clock framework reads past the last entry. Fix that with adding
sentinel at the end.

Issue was discovered with KASan.

Fixes: 0577e4853b ("clk: sunxi-ng: Add H3 clocks")
Fixes: c6a0637460 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Link: https://lore.kernel.org/r/20201202203817.438713-1-jernej.skrabec@siol.net
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 15:54:02 -08:00
Christophe JAILLET
d2d94fc567 clk: s2mps11: Fix a resource leak in error handling paths in the probe function
Some resource should be released in the error handling path of the probe
function, as already done in the remove function.

The remove function was fixed in commit bf416bd457 ("clk: s2mps11: Add
missing of_node_put and of_clk_del_provider")

Fixes: 7cc560dea4 ("clk: s2mps11: Add support for s2mps11")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/20201212122818.86195-1-christophe.jaillet@wanadoo.fr
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 15:53:31 -08:00
Terry Zhou
6f37689cf6 clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
There is an error in the current code that the XTAL MODE
pin was set to NB MPP1_31 which should be NB MPP1_9.
The latch register of NB MPP1_9 has different offset of 0x8.

Signed-off-by: Terry Zhou <bjzhou@marvell.com>
[pali: Fix pin name in commit message]
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 7ea8250406 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20201106100039.11385-1-pali@kernel.org
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 15:51:18 -08:00
Sascha Hauer
5142cbcea3 clk: si5351: Wait for bit clear after PLL reset
Documentation states that SI5351_PLL_RESET_B and SI5351_PLL_RESET_A bits
are self clearing bits, so wait until they are cleared before
continuing.
This fixes a case when the clock doesn't come up properly after a PLL
reset. It worked properly when the frequency was below 900MHz, but with
900MHz it only works when we are waiting for the bit to clear.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20201130091033.1687-1-s.hauer@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 15:49:54 -08:00
Alexandre Belloni
01324f9e88 clk: at91: sam9x60: remove atmel,osc-bypass support
The sam9x60 doesn't have the MOSCXTBY bit to enable the crystal oscillator
bypass.

Fixes: 01e2113de9 ("clk: at91: add sam9x60 pmc driver")
Reported-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20201202125816.168618-1-alexandre.belloni@bootlin.com
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 15:33:00 -08:00
Claudiu Beznea
91f3bf0d53 clk: at91: sama7g5: register cpu clock
Register CPU clock as being the master clock prescaler. This would
be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
frequencies supported by SAMA7G5 could be directly received from
CPUPLL + master clock prescaler and the extra divider would do no work in
case it would be enabled.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:56 -08:00
Claudiu Beznea
7a110b9107 clk: at91: clk-master: re-factor master clock
Re-factor master clock driver by splitting it into 2 clocks: prescaller
and divider clocks. Based on registered clock flags the prescaler's rate
could be changed at runtime. This is necessary for platforms supporting
DVFS (e.g. SAMA7G5) where master clock could be changed at run-time.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:56 -08:00
Claudiu Beznea
120d5d8b46 clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:56 -08:00
Claudiu Beznea
f803858af8 clk: at91: sama7g5: decrease lower limit for MCK0 rate
On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
also changed by DVFS to avoid over/under clocking of MCK0 consumers.
The lower limit is changed to be able to set MCK0 accordingly by
DVFS.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:56 -08:00
Claudiu Beznea
4011f03ee4 clk: at91: sama7g5: remove mck0 from parent list of other clocks
MCK0 is changed at runtime by DVFS. Due to this, since not all IPs
are glitch free aware at MCK0 changes, remove MCK0 from parent list
of other clocks (e.g. generic clock, programmable/system clock, MCKX).

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-8-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:56 -08:00
Claudiu Beznea
8dc4af8bef clk: at91: clk-sam9x60-pll: allow runtime changes for pll
Allow runtime frequency changes for PLLs registered with proper flags.
This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:55 -08:00
Eugen Hristev
0bb4623f13 clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:55 -08:00
Eugen Hristev
e26b3006ff clk: at91: clk-master: add 5th divisor for mck master
clk-master can have 5 divisors with a field width of 3 bits
on some products.

Change the mask and number of divisors accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-5-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:55 -08:00
Eugen Hristev
83d0028773 clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
from phandle in DT.

Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[claudiu.beznea@microchip.com: adapt commit message, add CPU PLL]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:55 -08:00
Eugen Hristev
3d86ee17d4 dt-bindings: clock: at91: add sama7g5 pll defines
Add SAMA7G5 specific PLL defines to be referenced in a phandle as a
PMC_TYPE_CORE clock.

Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:55 -08:00
Claudiu Beznea
91274497c7 clk: at91: sama7g5: fix compilation error
pmc_data_allocate() has been changed. pmc_data_free() was removed.
Adapt the code taking this into consideration. With this the programmable
clocks were also saved in sama7g5_pmc so that they could be later
referenced.

Fixes: cb783bbbcf ("clk: at91: sama7g5: add clock support for sama7g5")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:50:55 -08:00
Nicolas Saenz Julienne
be439cc4c4 clk: bcm: dvp: Add MODULE_DEVICE_TABLE()
Add MODULE_DEVICE_TABLE() so as to be able to use the driver as a
module. More precisely, for the driver to be loaded automatically at
boot.

Fixes: 1bc9597271 ("clk: bcm: Add BCM2711 DVP driver")
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Link: https://lore.kernel.org/r/20201202103518.21889-1-nsaenzjulienne@suse.de
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:48:29 -08:00
Uwe Kleine-König
c82cf05190 clk: bcm: dvp: drop a variable that is assigned to only
The third parameter to devm_platform_get_and_ioremap_resource() is used
only to provide the used resource. As this variable isn't used
afterwards, switch to the function devm_platform_ioremap_resource()
which doesn't provide this output parameter.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20201120132121.2678997-1-u.kleine-koenig@pengutronix.de
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-19 11:45:47 -08:00
Maxime Ripard
03813d9b7d clk: Trace clk_set_rate() "range" functions
The clk_set_rate "range" functions don't have any tracepoints even
though it might be useful. Add some.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20201207105050.2096917-1-maxime@cerno.tech
[sboyd@kernel.org: Reword commit text]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:54:31 -08:00
Alexandru Ardelean
16214f97f4 clk: axi-clkgen: move the OF table at the bottom of the file
The change is mostly cosmetic. No functional changes.
Since the driver now uses of_device_get_match_data() to obtain some driver
specific info, there is no need to define the OF table before the probe
function.

Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20201203074037.26940-2-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:52:54 -08:00
Alexandru Ardelean
ac1ee86a9c clk: axi-clkgen: wrap limits in a struct and keep copy on the state object
Up until the these limits were global/hard-coded, since they are typically
limits of the fabric.

However, since this is an FPGA generated clock, this may run on setups
where one clock is on a fabric, and another one synthesized on another
fabric connected via PCIe (or some other inter-connect, and then these
limits need to be adjusted for each instance of the AXI CLKGEN.

This change wraps the current constants in 'axi_clkgen_limits' struct and
the 'axi_clkgen' instance keeps a copy of these limits, which is
initialized at probe from the default limits.

The limits are stored on the device-tree OF table, so that we can adjust
them via the compatible string.

Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:52:54 -08:00
David Shah
66cc7af381 clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs
Having the ABE DPLL ref and bypass muxes set to different inputs was
causing the DPLL not to lock when TIMER8 was used, as it is in the Pyra
for the backlight.

This patch fixes this by setting abe_dpll_bypass_clk_mux to sys_32k_ck
in omap5xxx_dt_clk_init.

A similar patch may also be needed for OMAP44xx which has similar code
in omap4xxx_dt_clk_init, but I have not added this as I have no hardware
to test on.

Signed-off-by: David Shah <dave@ds0.me>
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Link: https://lore.kernel.org/r/1d3abe2512054866cc2ea7b2592238f4fa06502a.1607253531.git.hns@goldelico.com
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:47:01 -08:00
Zhang Qilong
8c6239f6e9 clk: ti: Fix memleak in ti_fapll_synth_setup
If clk_register fails, we should goto free branch
before function returns to prevent memleak.

Fixes: 163152cbbe ("clk: ti: Add support for FAPLL on dm816x")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
Link: https://lore.kernel.org/r/20201113131623.2098222-1-zhangqilong3@huawei.com
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:46:37 -08:00
Dmitry Osipenko
bf6d43d723 clk: Add hardware-enable column to clk summary
Add "hardware enable" column to the clk summary in order to show actual
hardware enable-state of all clocks. The possible states are "Y/N/?",
where question mark means that state is unknown, i.e. clock isn't a
mux and clk-driver doesn't support is_enabled() callback for this clock.

In conjunction with clk_ignore_unused, this tells us what unused clocks
are left enabled after bootloader. This is also a useful aid for
debugging interactions with firmware which changes clock states without
notifying kernel.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201115203432.13934-1-digetx@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 01:43:32 -08:00
Weiyi Lu
2aeff9d8c8 clk: mediatek: Make mtk_clk_register_mux() a static function
mtk_clk_register_mux() should be a static function

Fixes: a3ae549917 ("clk: mediatek: Add new clkmux register API")
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Link: https://lore.kernel.org/r/1605256192-31307-1-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-17 00:41:54 -08:00
Linus Torvalds
accefff5b5 ARM: SoC updates for OMAP GenPD
These are additional updates for the power domain support on OMAP,
 moving to an implementation based on device tree information instead of
 SoC specific code. This is the latest step in the ongoing process for
 moving code out of arch/arm/mach-omap2.
 
 I kept this separate from the other driver changes since it touches
 code in multiple areas.
 
 There is one conflict in the dra7.dts file, which adds another node
 in a different branch. Watch out for adding the trailing '};'
 both times.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-soc-omap-genpd-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC OMAP GenPD updates from Arnd Bergmann:
 "These are additional updates for the power domain support on OMAP,
  moving to an implementation based on device tree information instead
  of SoC specific code. This is the latest step in the ongoing process
  for moving code out of arch/arm/mach-omap2.

  I kept this separate from the other driver changes since it touches
  code in multiple areas"

* tag 'arm-soc-omap-genpd-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (51 commits)
  ARM: OMAP2+: Fix am4 only build after genpd changes
  ARM: dts: Configure power domain for omap5 dss
  ARM: dts: omap5: add remaining PRM instances
  soc: ti: omap-prm: omap5: add genpd support for remaining PRM instances
  ARM: OMAP2+: Drop legacy platform data for dra7 gpmc
  ARM: dts: Configure interconnect target module for dra7 iva
  ARM: dts: dra7: add remaining PRM instances
  soc: ti: omap-prm: dra7: add genpd support for remaining PRM instances
  clk: ti: dra7: Drop idlest polling from IVA clkctrl clocks
  ARM: OMAP2+: Drop legacy platform data for omap4 gpmc
  ARM: OMAP2+: Drop legacy platform data for omap4 iva
  ARM: dts: Configure power domain for omap4 dsp
  ARM: dts: Configure power domain for omap4 dss
  ARM: dts: omap4: add remaining PRM instances
  soc: ti: omap-prm: omap4: add genpd support for remaining PRM instances
  clk: ti: omap4: Drop idlest polling from IVA clkctrl clocks
  ARM: OMAP2+: Drop legacy remaining legacy platform data for am4
  ARM: dts: Use simple-pm-bus for genpd for am4 l3
  ARM: dts: Move am4 l3 noc to a separate node
  ARM: dts: Use simple-pm-bus for genpd for am4 l4_per
  ...
2020-12-16 16:53:54 -08:00
Linus Torvalds
48c1c40ab4 ARM: SoC drivers for v5.11
There are a couple of subsystems maintained by other people that
 merge their drivers through the SoC tree, those changes include:
 
  - The SCMI firmware framework gains support for sensor notifications
    and for controlling voltage domains.
 
  - A large update for the Tegra memory controller driver, integrating
    it better with the interconnect framework
 
  - The memory controller subsystem gains support for Mediatek MT8192
 
  - The reset controller framework gains support for sharing pulsed
    resets
 
 For Soc specific drivers in drivers/soc, the main changes are
 
  - The Allwinner/sunxi MBUS gets a rework for the way it handles
    dma_map_ops and offsets between physical and dma address spaces.
 
  - An errata fix plus some cleanups for Freescale Layerscape SoCs
 
  - A cleanup for renesas drivers regarding MMIO accesses.
 
  - New SoC specific drivers for Mediatek MT8192 and MT8183 power domains
 
  - New SoC specific drivers for Aspeed AST2600 LPC bus control
    and SoC identification.
 
  - Core Power Domain support for Qualcomm MSM8916, MSM8939, SDM660
    and SDX55.
 
  - A rework of the TI AM33xx 'genpd' power domain support to use
    information from DT instead of platform data
 
  - Support for TI AM64x SoCs
 
  - Allow building some Amlogic drivers as modules instead of built-in
 
 Finally, there are numerous cleanups and smaller bug fixes for
 Mediatek, Tegra, Samsung, Qualcomm, TI OMAP, Amlogic, Rockchips,
 Renesas, and Xilinx SoCs.
 
 There is a trivial conflict in the cedrus driver, with two branches
 adding the same CEDRUS_CAPABILITY_H265_DEC flag, and another trivial
 remove/remove conflict in linux/dma-mapping.h.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-soc-drivers-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "There are a couple of subsystems maintained by other people that merge
  their drivers through the SoC tree, those changes include:

   - The SCMI firmware framework gains support for sensor notifications
     and for controlling voltage domains.

   - A large update for the Tegra memory controller driver, integrating
     it better with the interconnect framework

   - The memory controller subsystem gains support for Mediatek MT8192

   - The reset controller framework gains support for sharing pulsed
     resets

  For Soc specific drivers in drivers/soc, the main changes are

   - The Allwinner/sunxi MBUS gets a rework for the way it handles
     dma_map_ops and offsets between physical and dma address spaces.

   - An errata fix plus some cleanups for Freescale Layerscape SoCs

   - A cleanup for renesas drivers regarding MMIO accesses.

   - New SoC specific drivers for Mediatek MT8192 and MT8183 power
     domains

   - New SoC specific drivers for Aspeed AST2600 LPC bus control and SoC
     identification.

   - Core Power Domain support for Qualcomm MSM8916, MSM8939, SDM660 and
     SDX55.

   - A rework of the TI AM33xx 'genpd' power domain support to use
     information from DT instead of platform data

   - Support for TI AM64x SoCs

   - Allow building some Amlogic drivers as modules instead of built-in

  Finally, there are numerous cleanups and smaller bug fixes for
  Mediatek, Tegra, Samsung, Qualcomm, TI OMAP, Amlogic, Rockchips,
  Renesas, and Xilinx SoCs"

* tag 'arm-soc-drivers-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (222 commits)
  soc: mediatek: mmsys: Specify HAS_IOMEM dependency for MTK_MMSYS
  firmware: xilinx: Properly align function parameter
  firmware: xilinx: Add a blank line after function declaration
  firmware: xilinx: Remove additional newline
  firmware: xilinx: Fix kernel-doc warnings
  firmware: xlnx-zynqmp: fix compilation warning
  soc: xilinx: vcu: add missing register NUM_CORE
  soc: xilinx: vcu: use vcu-settings syscon registers
  dt-bindings: soc: xlnx: extract xlnx, vcu-settings to separate binding
  soc: xilinx: vcu: drop useless success message
  clk: samsung: mark PM functions as __maybe_unused
  soc: samsung: exynos-chipid: initialize later - with arch_initcall
  soc: samsung: exynos-chipid: order list of SoCs by name
  memory: jz4780_nemc: Fix potential NULL dereference in jz4780_nemc_probe()
  memory: ti-emif-sram: only build for ARMv7
  memory: tegra30: Support interconnect framework
  memory: tegra20: Support hardware versioning and clean up OPP table initialization
  dt-bindings: memory: tegra20-emc: Document opp-supported-hw property
  soc: rockchip: io-domain: Fix error return code in rockchip_iodomain_probe()
  reset-controller: ti: force the write operation when assert or deassert
  ...
2020-12-16 16:38:41 -08:00
Pragnesh Patel
732374a0b4 clk: sifive: Add clock enable and disable ops
Add new functions "sifive_prci_clock_enable(), sifive_prci_clock_disable()
and sifive_clk_is_enabled()" to enable or disable the PRCI clock

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Zong Li <zong.li@sifive.com>
Link: https://lore.kernel.org/r/20201209094916.17383-6-zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-16 12:23:13 -08:00
Zong Li
263ac39085 clk: sifive: Fix the wrong bit field shift
The clk enable bit should be 31 instead of 24.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reported-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Link: https://lore.kernel.org/r/20201209094916.17383-5-zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-16 12:23:12 -08:00
Zong Li
efc91ae43c clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
Add driver code for the SiFive FU740 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU740 device and
implements SoC-level clock tree controls and dividers.

The link of unmatched as follow, and the U740-C000 manual would
be present in the same page as soon.
https://www.sifive.com/boards/hifive-unmatched

This driver contains bug fixes and contributions from
Henry Styles <hes@sifive.com>
Erik Danie <erik.danie@sifive.com>
Pragnesh Patel <pragnesh.patel@sifive.com>

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: Henry Styles <hes@sifive.com>
Cc: Erik Danie <erik.danie@sifive.com>
Cc: Pragnesh Patel <pragnesh.patel@sifive.com>
Link: https://lore.kernel.org/r/20201209094916.17383-4-zong.li@sifive.com
[sboyd@kernel.org: Include header to silence sparse]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-16 12:22:59 -08:00
Zong Li
28108fc8a0 clk: sifive: Use common name for prci configuration
Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
patch is prepared for fu740 support.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Link: https://lore.kernel.org/r/20201209094916.17383-3-zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-16 12:22:59 -08:00
Zong Li
c816e1ddf2 clk: sifive: Extract prci core to common base
Extract common core of prci driver to an independent file, it could
allow other chips to reuse it. Separate SoCs-dependent code 'fu540'
from prci core, then we can easily add 'fu740' later.

Almost these changes are code movement. The different is adding the
private data for each SoC use, so it needs to get match data in probe
callback function, then use the data for initialization.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Link: https://lore.kernel.org/r/20201209094916.17383-2-zong.li@sifive.com
[sboyd@kernel.org: Include header to silence sparse]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-16 12:22:39 -08:00
Linus Torvalds
b4ec805464 Power management updates for 5.11-rc1
- Use local_clock() instead of jiffies in the cpufreq statistics to
    improve accuracy (Viresh Kumar).
 
  - Fix up OPP usage in the cpufreq-dt and qcom-cpufreq-nvmem cpufreq
    drivers (Viresh Kumar).
 
  - Clean up the cpufreq core, the intel_pstate driver and the
    schedutil cpufreq governor (Rafael Wysocki).
 
  - Fix up error code paths in the sti-cpufreq and mediatek cpufreq
    drivers (Yangtao Li, Qinglang Miao).
 
  - Fix cpufreq_online() to return error codes instead of success (0)
    in all cases when it fails (Wang ShaoBo).
 
  - Add mt8167 support to the mediatek cpufreq driver and blacklist
    mt8516 in the cpufreq-dt-platdev driver (Fabien Parent).
 
  - Modify the tegra194 cpufreq driver to always return values from
    the frequency table as the current frequency and clean up that
    driver (Sumit Gupta, Jon Hunter).
 
  - Modify the arm_scmi cpufreq driver to allow it to discover the
    power scale present in the performance protocol and provide this
    information to the Energy Model (Lukasz Luba).
 
  - Add missing MODULE_DEVICE_TABLE to several cpufreq drivers (Pali
    Rohár).
 
  - Clean up the CPPC cpufreq driver (Ionela Voinescu).
 
  - Fix NVMEM_IMX_OCOTP dependency in the imx cpufreq driver (Arnd
    Bergmann).
 
  - Rework the poling interval selection for the polling state in
    cpuidle (Mel Gorman).
 
  - Enable suspend-to-idle for PSCI OSI mode in the PSCI cpuidle
    driver (Ulf Hansson).
 
  - Modify the OPP framework to support empty (node-less) OPP tables
    in DT for passing dependency information (Nicola Mazzucato).
 
  - Fix potential lockdep issue in the OPP core and clean up the OPP
    core (Viresh Kumar).
 
  - Modify dev_pm_opp_put_regulators() to accept a NULL argument and
    update its users accordingly (Viresh Kumar).
 
  - Add frequency changes tracepoint to devfreq (Matthias Kaehlcke).
 
  - Add support for governor feature flags to devfreq, make devfreq
    sysfs file permissions depend on the governor and clean up the
    devfreq core (Chanwoo Choi).
 
  - Clean up the tegra20 devfreq driver and deprecate it to allow
    another driver based on EMC_STAT to be used instead of it (Dmitry
    Osipenko).
 
  - Add interconnect support to the tegra30 devfreq driver, allow it
    to take the interconnect and OPP information from DT and clean it
    up ((Dmitry Osipenko).
 
  - Add interconnect support to the exynos-bus devfreq driver along
    with interconnect properties documentation (Sylwester Nawrocki).
 
  - Add suport for AMD Fam17h and Fam19h processors to the RAPL power
    capping driver (Victor Ding, Kim Phillips).
 
  - Fix handling of overly long constraint names in the powercap
    framework (Lukasz Luba).
 
  - Fix the wakeup configuration handling for bridges in the ACPI
    device power management core (Rafael Wysocki).
 
  - Add support for using an abstract scale for power units in the
    Energy Model (EM) and document it (Lukasz Luba).
 
  - Add em_cpu_energy() micro-optimization to the EM (Pavankumar
    Kondeti).
 
  - Modify the generic power domains (genpd) framwework to support
    suspend-to-idle (Ulf Hansson).
 
  - Fix creation of debugfs nodes in genpd (Thierry Strudel).
 
  - Clean up genpd (Lina Iyer).
 
  - Clean up the core system-wide suspend code and make it print
    driver flags for devices with debug enabled (Alex Shi, Patrice
    Chotard, Chen Yu).
 
  - Modify the ACPI system reboot code to make it prepare for system
    power off to avoid confusing the platform firmware (Kai-Heng Feng).
 
  - Update the pm-graph (multiple changes, mostly usability-related)
    and cpupower (online and offline CPU information support) PM
    utilities (Todd Brandt, Brahadambal Srinivasan).
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Merge tag 'pm-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

Pull power management updates from Rafael Wysocki:
 "These update cpufreq (core and drivers), cpuidle (polling state
  implementation and the PSCI driver), the OPP (operating performance
  points) framework, devfreq (core and drivers), the power capping RAPL
  (Running Average Power Limit) driver, the Energy Model support, the
  generic power domains (genpd) framework, the ACPI device power
  management, the core system-wide suspend code and power management
  utilities.

  Specifics:

   - Use local_clock() instead of jiffies in the cpufreq statistics to
     improve accuracy (Viresh Kumar).

   - Fix up OPP usage in the cpufreq-dt and qcom-cpufreq-nvmem cpufreq
     drivers (Viresh Kumar).

   - Clean up the cpufreq core, the intel_pstate driver and the
     schedutil cpufreq governor (Rafael Wysocki).

   - Fix up error code paths in the sti-cpufreq and mediatek cpufreq
     drivers (Yangtao Li, Qinglang Miao).

   - Fix cpufreq_online() to return error codes instead of success (0)
     in all cases when it fails (Wang ShaoBo).

   - Add mt8167 support to the mediatek cpufreq driver and blacklist
     mt8516 in the cpufreq-dt-platdev driver (Fabien Parent).

   - Modify the tegra194 cpufreq driver to always return values from the
     frequency table as the current frequency and clean up that driver
     (Sumit Gupta, Jon Hunter).

   - Modify the arm_scmi cpufreq driver to allow it to discover the
     power scale present in the performance protocol and provide this
     information to the Energy Model (Lukasz Luba).

   - Add missing MODULE_DEVICE_TABLE to several cpufreq drivers (Pali
     Rohár).

   - Clean up the CPPC cpufreq driver (Ionela Voinescu).

   - Fix NVMEM_IMX_OCOTP dependency in the imx cpufreq driver (Arnd
     Bergmann).

   - Rework the poling interval selection for the polling state in
     cpuidle (Mel Gorman).

   - Enable suspend-to-idle for PSCI OSI mode in the PSCI cpuidle driver
     (Ulf Hansson).

   - Modify the OPP framework to support empty (node-less) OPP tables in
     DT for passing dependency information (Nicola Mazzucato).

   - Fix potential lockdep issue in the OPP core and clean up the OPP
     core (Viresh Kumar).

   - Modify dev_pm_opp_put_regulators() to accept a NULL argument and
     update its users accordingly (Viresh Kumar).

   - Add frequency changes tracepoint to devfreq (Matthias Kaehlcke).

   - Add support for governor feature flags to devfreq, make devfreq
     sysfs file permissions depend on the governor and clean up the
     devfreq core (Chanwoo Choi).

   - Clean up the tegra20 devfreq driver and deprecate it to allow
     another driver based on EMC_STAT to be used instead of it (Dmitry
     Osipenko).

   - Add interconnect support to the tegra30 devfreq driver, allow it to
     take the interconnect and OPP information from DT and clean it up
     (Dmitry Osipenko).

   - Add interconnect support to the exynos-bus devfreq driver along
     with interconnect properties documentation (Sylwester Nawrocki).

   - Add suport for AMD Fam17h and Fam19h processors to the RAPL power
     capping driver (Victor Ding, Kim Phillips).

   - Fix handling of overly long constraint names in the powercap
     framework (Lukasz Luba).

   - Fix the wakeup configuration handling for bridges in the ACPI
     device power management core (Rafael Wysocki).

   - Add support for using an abstract scale for power units in the
     Energy Model (EM) and document it (Lukasz Luba).

   - Add em_cpu_energy() micro-optimization to the EM (Pavankumar
     Kondeti).

   - Modify the generic power domains (genpd) framwework to support
     suspend-to-idle (Ulf Hansson).

   - Fix creation of debugfs nodes in genpd (Thierry Strudel).

   - Clean up genpd (Lina Iyer).

   - Clean up the core system-wide suspend code and make it print driver
     flags for devices with debug enabled (Alex Shi, Patrice Chotard,
     Chen Yu).

   - Modify the ACPI system reboot code to make it prepare for system
     power off to avoid confusing the platform firmware (Kai-Heng Feng).

   - Update the pm-graph (multiple changes, mostly usability-related)
     and cpupower (online and offline CPU information support) PM
     utilities (Todd Brandt, Brahadambal Srinivasan)"

* tag 'pm-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (86 commits)
  cpufreq: Fix cpufreq_online() return value on errors
  cpufreq: Fix up several kerneldoc comments
  cpufreq: stats: Use local_clock() instead of jiffies
  cpufreq: schedutil: Simplify sugov_update_next_freq()
  cpufreq: intel_pstate: Simplify intel_cpufreq_update_pstate()
  PM: domains: create debugfs nodes when adding power domains
  opp: of: Allow empty opp-table with opp-shared
  dt-bindings: opp: Allow empty OPP tables
  media: venus: dev_pm_opp_put_*() accepts NULL argument
  drm/panfrost: dev_pm_opp_put_*() accepts NULL argument
  drm/lima: dev_pm_opp_put_*() accepts NULL argument
  PM / devfreq: exynos: dev_pm_opp_put_*() accepts NULL argument
  cpufreq: qcom-cpufreq-nvmem: dev_pm_opp_put_*() accepts NULL argument
  cpufreq: dt: dev_pm_opp_put_regulators() accepts NULL argument
  opp: Allow dev_pm_opp_put_*() APIs to accept NULL opp_table
  opp: Don't create an OPP table from dev_pm_opp_get_opp_table()
  cpufreq: dt: Don't (ab)use dev_pm_opp_get_opp_table() to create OPP table
  opp: Reduce the size of critical section in _opp_kref_release()
  PM / EM: Micro optimization in em_cpu_energy
  cpufreq: arm_scmi: Discover the power scale in performance protocol
  ...
2020-12-15 16:30:31 -08:00
Rafael J. Wysocki
d3569c149d Update devfreq for 5.11
Detailed description for this pull request:
 
 1. Update devfreq core
 - Add new devfreq_frequency tracepoint to show the frequency change
 information.
 
 - Add governor feature flag. The devfreq governor is able to
 have the specific flag in order to contain the non-common feature.
 For example, if governor contains the 'immutable' feature, don't allow
 user to change the governor via sysfs.
 
 - Add governor sysfs attribute flag for each sysfs file. Prior to that
 devfreq subsystem show the all sysfs files regardless of governor type.
 But, some sysfs fils are not supported on the specific devfreq governor.
 In order to show the only supported sysfs files according to the governor,
 clarify the access permission of sysfs attributes according to governor.
 When adding the devfreq governor, can specify the available attribute
 information by using DEVFREQ_GOV_ATTR_* constant variable. The user can
 read or write the sysfs attributes in accordance to the specified attributes.
 
 - Clean-up the code to remove the duplicate code for the devfreq tracepoint
 and to remove redundant governor_name field from struct devfreq
 
 2. Update exynos-bus.c devfreq driver
 - Add interconnect API support for the Samsung Exynos Bus Frequency driver
 of exynos-bus.c. Complementing the devfreq driver with an interconnect
 functionality allows to ensure the QoS requirements of devices accessing
 the system memory (e.g. video processing devices) are fulfilled
 and allows to avoid issues like the DMA underrun.
 
 3. Update tegra devfreq driver
 - Add interconnect support and OPP interface for tegra30-devfreq.c.
 Also, it is to guarantee the QoS requirement of some devices like
 display controller.
 
 - Move tegra20-devfreq.c from drivers/devfreq/ into driver/memory/tegra/
 in order to use the more proper monitoring feature such as EMC_STAT
 which is based in driver/memory/tegra/.
 
 - Separate the configuration information for different SoC on
 tegra30-devfrqe.c. The tegra30-devfreq.c had been supported both
 tegra30-actmon and tegra124-actmon devices. In order to use
 the more correct configuration data, separate them.
 
 - Use dev_err_probe() to handle the deferred probe error on tegra30-devfreq.c.
 
 4. Pull the request of 'Tegra SoC and clock controller changes for v5.11'
 sent by Krzysztof Kozlowski <krzk@kernel.org> in order to prevent the
 build error.
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Merge tag 'devfreq-next-for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux

Pull devfreq updates for 5.11 from Chanwoo Choi:

 1. Update devfreq core

  - Add new devfreq_frequency tracepoint to show the frequency change
    information.

  - Add governor feature flag. The devfreq governor is able to set the
    specific flag in order to support a non-common feature. For
    example, if the governor supports the 'immutable' feature, don't
    allow user space to change the governor via sysfs.

  - Add governor sysfs attribute flag for each sysfs file. Prior to that
    the devfreq subsystem allowed all of the sysfs files to be accessed
    regardless of the governor type. But some sysfs fils are not
    supported by specific devfreq governors. In order to only allow the
    sysfs files supported by the governor to be accessed, clarify the
    access permissions of sysfs attributes according to the governor.
    When adding the devfreq governor, specify the available attribute
    information by using DEVFREQ_GOV_ATTR_* symbols. The user can read
    or write the sysfs attributes in accordance to the specified
    access permissions.

  - Clean-up the code to reduce duplication for the devfreq tracepoint
    and to remove redundant governor_name field from struct devfreq.

 2. Update exynos-bus.c devfreq driver

  - Add interconnect API support to the Samsung Exynos Bus Frequency
    driver, exynos-bus.c. Complementing the devfreq driver with
    interconnect functionality allows to ensure that the QoS
    requirements regarding devices accessing the system memory (e.g.
    video processing devices) will be met and allows to avoid issues
    like DMA underrun.

 3. Update tegra devfreq driver

  - Add interconnect support and OPP interface to tegra30-devfreq.c.
    Also, it is to guarantee the QoS requirement of some devices like
    the display controller.

  - Move tegra20-devfreq.c from drivers/devfreq/ into drivers/memory/tegra/
    in order to use the more proper monitoring feature such as EMC_STAT
    which is located in drivers/memory/tegra/.

  - Separate the configuration information for different SoCs in
    tegra30-devfrqe.c. The tegra30-devfreq.c had been supporting both
    tegra30-actmon and tegra124-actmon devices. In order to use the
    more correct configuration data, separate them.

  - Use dev_err_probe() to handle the deferred probe error in
    tegra30-devfreq.c.

 4. Pull the request of 'Tegra SoC and clock controller changes for
    v5.11' sent by Krzysztof Kozlowski <krzk@kernel.org> in order to
    avoid a build error."

* tag 'devfreq-next-for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux:
  PM / devfreq: tegra30: Separate configurations per-SoC generation
  PM / devfreq: tegra30: Support interconnect and OPPs from device-tree
  PM / devfreq: tegra20: Deprecate in a favor of emc-stat based driver
  PM / devfreq: exynos-bus: Add registration of interconnect child device
  dt-bindings: devfreq: Add documentation for the interconnect properties
  soc/tegra: fuse: Add stub for tegra_sku_info
  soc/tegra: fuse: Export tegra_read_ram_code()
  clk: tegra: Export Tegra20 EMC kernel symbols
  PM / devfreq: tegra30: Silence deferred probe error
  PM / devfreq: tegra20: Relax Kconfig dependency
  PM / devfreq: tegra20: Silence deferred probe error
  PM / devfreq: Remove redundant governor_name from struct devfreq
  PM / devfreq: Add governor attribute flag for specifc sysfs nodes
  PM / devfreq: Add governor feature flag
  PM / devfreq: Add tracepoint for frequency changes
  PM / devfreq: Unify frequency change to devfreq_update_target func
  trace: events: devfreq: Use fixed indentation size to improve readability
2020-12-11 19:40:00 +01:00
Dmitry Osipenko
5bf5861d6e clk: tegra: Fix duplicated SE clock entry
The periph_clks[] array contains duplicated entry for Security Engine
clock which was meant to be defined for T210, but it wasn't added
properly. This patch corrects the T210 SE entry and fixes the following
error message on T114/T124: "Tegra clk 127: register failed with -17".

Fixes: dc37fec483 ("clk: tegra: periph: Add new periph clks and muxes for Tegra210")
Tested-by Nicolas Chauvet <kwizart@gmail.com>
Reported-by Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20201025224212.7790-1-digetx@gmail.com
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:51:59 -08:00
Vinod Koul
f7b36cc19e clk: qcom: rpmh: add support for SM8350 rpmh clocks
This adds the RPMH clocks present in SM8350 SoC

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20201208064702.3654324-3-vkoul@kernel.org
[sboyd@kernel.org: Move sdx55 to the right place]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:47:11 -08:00
Taniya Das
ce8c195e65 clk: qcom: lpasscc: Introduce pm autosuspend for SC7180
The LPASSCC driver's suspend/resume is invoked multiple number of times
and thus allow the device to autosuspend for 500ms.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1605890417-721-1-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:29:21 -08:00
Douglas Anderson
043577518f clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2
50 MHz is an incredibly common clock rate for SD cards to run at.
It's "high speed" mode in SD (not very fast these days, but it used to
be) or:
  #define HIGH_SPEED_MAX_DTR	50000000

If we don't support this then older "high speed" cards can only run at
25 MHz or at half their normal speed.  There doesn't seem to be any
reason to skip this clock rate, so add it.

Fixes: 17269568f7 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20201210102234.2.I26dcc0cee374f5571d9929c9985f463773167e68@changeid
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:27:30 -08:00
Douglas Anderson
6d37a8d192 clk: qcom: gcc-sc7180: Use floor ops for sdcc clks
I would repeat the same commit message that was in commit 5e4b7e82d4
("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems
silly to do so when you could just go read that commit.

NOTE: this is actually extra terrible because we're missing the 50 MHz
rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add
50 MHz clock rate for SDC2")).  That means then when you run an older
SD card it'll try to clock it at 100 MHz when it's only specced to run
at 50 MHz max.  As you can probably guess that doesn't work super
well.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Fixes: 17269568f7 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180")
Link: https://lore.kernel.org/r/20201210102234.1.I096779f219625148900fc984dd0084ed1ba87c7f@changeid
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:27:30 -08:00
Krzysztof Kozlowski
975d25cbb5 clk: scpi: mark scpi_clk_match as maybe unused
The scpi_clk_match (struct of_device_id) is referenced only with
CONFIG_OF builds thus mark it as __maybe_unused:

    drivers/clk/clk-scpi.c:132:34: warning:
        ‘scpi_clk_match’ defined but not used [-Wunused-const-variable=]

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20201103162435.13689-8-krzk@kernel.org
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:24:40 -08:00
Krzysztof Kozlowski
967069aa4d clk: pwm: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always
used and the of_match_ptr does not have any sense (this also allows ACPI
matching via PRP0001, even though it might be not relevant here).  This
fixes compile warning (!CONFIG_OF && !CONFIG_MODULES):

    drivers/clk/clk-pwm.c:139:34: warning:
        ‘clk_pwm_dt_ids’ defined but not used [-Wunused-const-variable=]

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20201103162435.13689-1-krzk@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10 12:24:18 -08:00