2
0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-24 21:24:00 +08:00
Commit Graph

34 Commits

Author SHA1 Message Date
Stephen Boyd
f61990f3c5 clk: hisilicon: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Tested-by: Leo Yan <leo.yan@linaro.org>
Cc: Bintian Wang <bintian.wang@huawei.com>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-02 17:43:32 -08:00
Javier Martinez Canillas
90c53547fc clk: Remove unneeded semicolons
There are cleary typo errors so can be removed.

Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Acked-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-17 11:15:14 -07:00
Leo Yan
9f42a89da6 clk: Hi6220: separately build stub clock driver
The previous code, kernel builds Hi6220's common clock driver and stub
clock driver together. Stub clock driver has introduced the dependency
with CONFIG_MAILBOX, so kernel will not build Hi6220's common clock
driver due ARM64's defconfig have not enabled CONFIG_MAILBOX by default.

So separately build stub clock driver and common clock driver for
Hi6220; and only let stub clock driver has the dependency with
CONFIG_MAILBOX.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-03 10:44:55 -07:00
Leo Yan
c1628a2c41 clk: Hi6220: add stub clock driver
On Hi6220, there have some clocks which can use mailbox channel to send
messages to power controller to change frequency; this includes CPU, GPU
and DDR clocks.

For dynamic frequency scaling, firstly need write the frequency value to
SRAM region, and then send message to mailbox to trigger power controller
to handle this requirement. This driver will use syscon APIs to pass SRAM
memory region and use common mailbox APIs for channels accessing.

This init driver will support cpu frequency change firstly.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:49:10 -07:00
Leo Yan
1fb6dd9da6 clk: hisi: refine parameter checking for init
*of_iomap()* will check the device node pointer, and if the pointer is
NULL it will return error code. So refine clock's init flow by checking
the device node with this simple way; and polish a little for the print
out message.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-03 14:44:53 -07:00
Stephen Boyd
9cfad9bc47 Merge branch 'cleanup-clk-h-includes' into clk-next
* cleanup-clk-h-includes: (62 commits)
  clk: Remove clk.h from clk-provider.h
  clk: h8300: Remove clk.h and clkdev.h includes
  clk: at91: Include clk.h and slab.h
  clk: ti: Switch clk-provider.h include to clk.h
  clk: pistachio: Include clk.h
  clk: ingenic: Include clk.h
  clk: si570: Include clk.h
  clk: moxart: Include clk.h
  clk: cdce925: Include clk.h
  clk: Include clk.h in clk.c
  clk: zynq: Include clk.h
  clk: ti: Include clk.h
  clk: sunxi: Include clk.h and remove unused clkdev.h includes
  clk: st: Include clk.h
  clk: qcom: Include clk.h
  clk: highbank: Include clk.h
  clk: bcm: Include clk.h
  clk: versatile: Remove clk.h and clkdev.h includes
  clk: ux500: Remove clk.h and clkdev.h includes
  clk: tegra: Properly include clk.h
  ...
2015-07-28 11:59:09 -07:00
Boris Brezillon
57d866e606 clk: fix some determine_rate implementations
Some determine_rate implementations are not returning an error
when they failed to adapt the rate according to the rate request.
Fix them so that they return an error instead of silently
returning 0.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Tony Lindgren <tony@atomide.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: "Emilio López" <emilio@elopez.com.ar>
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Tero Kristo <t-kristo@ti.com>
CC: Peter De Schrijver <pdeschrijver@nvidia.com>
CC: Prashant Gaikwad <pgaikwad@nvidia.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-omap@vger.kernel.org
CC: linux-mips@linux-mips.org
CC: linux-tegra@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-27 18:13:32 -07:00
Boris Brezillon
0817b62cc0 clk: change clk_ops' ->determine_rate() prototype
Clock rates are stored in an unsigned long field, but ->determine_rate()
(which returns a rounded rate from a requested one) returns a long
value (errors are reported using negative error codes), which can lead
to long overflow if the clock rate exceed 2Ghz.

Change ->determine_rate() prototype to return 0 or an error code, and pass
a pointer to a clk_rate_request structure containing the expected target
rate and the rate constraints imposed by clk users.

The clk_rate_request structure might be extended in the future to contain
other kind of constraints like the rounding policy, the maximum clock
inaccuracy or other things that are not yet supported by the CCF
(power consumption constraints ?).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Tony Lindgren <tony@atomide.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: "Emilio López" <emilio@elopez.com.ar>
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
CC: Peter De Schrijver <pdeschrijver@nvidia.com>
CC: Prashant Gaikwad <pgaikwad@nvidia.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-omap@vger.kernel.org
CC: linux-mips@linux-mips.org
CC: linux-tegra@vger.kernel.org
[sboyd@codeaurora.org: Fix parent dereference problem in
__clk_determine_rate()]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate
clocks without parents or a rate determining op]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-27 18:12:01 -07:00
Stephen Boyd
593438e44c clk: hisilicon: Remove clk.h include
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Remove the include here because this is a
provider driver. Also drop the clkdev.h include in files that
aren't using it.

Cc: Bintian Wang <bintian.wang@huawei.com>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20 10:53:06 -07:00
Uwe Kleine-König
4a1caed3d0 clk: make several parent names const
Since commit 2893c37946 ("clk: make strings in parent name arrays
const") the name of parent clocks can be const. So add more const in
several clock drivers.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-04 14:27:06 -07:00
Michael Turquette
ae8d4048fa Merge branch 'clk-next-hi6220' into clk-next
Conflicts:
	drivers/clk/Kconfig
2015-06-03 15:22:03 -07:00
Bintian Wang
72ea48610d clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Bintian Wang <bintian.wang@huawei.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Tested-by: Will Deacon <will.deacon@arm.com>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-06-03 15:12:25 -07:00
Bintian Wang
463cfb2c9b clk: hisilicon: Remove __init for marking function prototypes
__init markings on function prototypes are useless, so remove
them.

Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Bintian Wang <bintian.wang@huawei.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-06-03 09:33:49 -07:00
Stephen Boyd
4a77f817b3 clk: hix5hd2: Silence sparse warnings
drivers/clk/hisilicon/clk-hix5hd2.c:255:13: warning: symbol 'hix5hd2_clk_register_complex' was not declared. Should it be static?

Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-14 17:11:21 -07:00
Uwe Kleine-König
692d8328e8 clk: don't use __initconst for non-const arrays
The statement

	static const char *name[];

defines a modifiable array of pointers to constant chars. That is

	*name[0] = 'f';

is forbidden, but

	name[0] = "f";

is not. So marking an array that is defined as above with __initconst is
wrong. Either an additional const must be added such that the whole
definition reads:

	static const char *const name[] __initconst;

or where this is not possible __initdata must be used.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-04-12 17:18:27 -07:00
Tomeu Vizoso
1c8e600440 clk: Add rate constraints to clocks
Adds a way for clock consumers to set maximum and minimum rates. This
can be used for thermal drivers to set minimum rates, or by misc.
drivers to set maximum rates to assure a minimum performance level.

Changes the signature of the determine_rate callback by adding the
parameters min_rate and max_rate.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[sboyd@codeaurora.org: set req_rate in __clk_init]
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate
                        migrated clk-private.h changes to clk.c]
2015-02-02 14:23:42 -08:00
Tomeu Vizoso
646cafc6aa clk: Change clk_ops->determine_rate to return a clk_hw as the best parent
This is in preparation for clock providers to not have to deal with struct clk.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-03 16:21:37 -08:00
Bintian Wang
7f615dd43c clk: hi3620: Move const initdata into correct code section
Use __initconst instead of __initdata for constant init data.

Signed-off-by: Bintian Wang <bintian.wang@huawei.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-19 16:56:31 -08:00
Wei Yan
45bcf9c6f2 clk: hix5hd2: add I2C clocks
hix5hd2 add I2C clocks (I2C0~i2C5)

Signed-off-by: Wei Yan <sledge.yanwei@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-09-28 10:27:09 +08:00
Guoxiong Yan
1463fba39c clk: hix5hd2: add watchdog0 clocks
hix5hd2 add watchdog0 clocks

Signed-off-by: Guoxiong Yan <yanguoxiong@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-09-28 10:27:04 +08:00
Jiancheng Xue
cc855dd999 clk: hix5hd2: add sd clk
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-09-28 10:27:01 +08:00
Zhangfei Gao
20e0755859 clk: hix5hd2: add complex clk
Support clk of sata, usb and ethernet

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-09-28 10:26:49 +08:00
Zhangfei Gao
5efaf09021 clk: hisi: add clk-hix5hd2.c
Signed-off-by: Haifeng Yan <haifeng.yan@linaro.org>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-05-12 11:30:32 +08:00
Zhangfei Gao
8b9dcb6cb7 clk: hisi: add hisi_clk_register_gate
Add hisi_clk_register_gate register clk gate table

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-05-12 11:30:18 +08:00
Zhangfei Gao
156342a1e5 clk: hisi: use clk_register_mux_table in hisi_clk_register_mux
Platform hix5hd2 use mux table, so use clk_register_mux_table instead

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-05-12 11:30:05 +08:00
Zhangfei Gao
c115b13b85 clk: hisilicon: fix warning from smatch
drivers/clk/hisilicon/clk-hi3620.c:338
mmc_clk_delay() warn: always true condition '(para >= 0) => (0-u32max >= 0)'

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20 19:05:39 -07:00
Mike Turquette
7876114798 updating clock drivers for Hisilicon
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJTKUozAAoJELXbXY/c+iv2BxQP/RR9EpIQ+JpNlE4ib2cGlKt4
 x+9nlCN/rZzKNUDE5fJm5knOksR1Jlv7xD4Gtz81i0hMXRz13qu5kQHftnIVyOUX
 0bkMsEnuRKY2DuPV+1FbC1hi7jnfOxqHAWWl7Sk+bTqhQeH+ZWMk8V+vRbib2SKk
 ilr3XZStCd7kxoGBxJuCV389boQESvS46juPTl1fe9UZUjL1l9MnozyVAjgvF4Le
 N0iG8FNyoX2Sj1Mm8Qg4OIrVRryRzNv5Q8uSPbEY7Qzx0fl0y+fZ/1AlzQXnrwBo
 MJd32fLPnpE1wQB4z4vpI0bNSYfC6KjbP6JY2cBBWYBN/7HJnCXtzgtTGgMZh+8Y
 1LXoD4WxOQ18M3QWuiCtAoOqi9it920n7gzbfIu0zpiMwKOvQOZX1+npEkbBC6AP
 +em5cFGsBmtjQ5kARywtLTTkE3MDJIAlht7px53mdoxP0fCR3moRx4hsMbji+9Y4
 /bEG64JYLQN8GjAYLdVtb1JLTnUux6dgerxuciFFthV2mqXqEF59rMR/aVZE5LF1
 V+uZdxNoJI+Gn1dkFXbSQHqAMgEaqX8FaElRannrLUkUPVNLT+wTFFaGy7zGKWt8
 RLSKzg7+LROkxgXIRdJw/mR7TPHILaFrYkvx4XFYP+dle7VNwRSPKb46jQhYQAIG
 NjVgl2hBb6fMGEPrSUFx
 =GNi8
 -----END PGP SIGNATURE-----

Merge tag 'clk-hisi' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilcon

updating clock drivers for Hisilicon
2014-03-19 12:54:03 -07:00
Haojian Zhuang
75af25f581 clk: hisi: remove static variable
Remove the static variable. So these common clock register helper could
be used in more SoCs.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19 15:31:27 +08:00
Haojian Zhuang
d3e6573c48 clk: hip04: add clock driver
Now only fixed rate clocks are appended into the clock driver.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19 15:23:53 +08:00
Haojian Zhuang
16d1c8991c clk: hisi: assign missing clk to table
The fixed rate and fixed factor clock isn't registered to clk table.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19 15:23:32 +08:00
Zhangfei Gao
62ac983b61 clk: hisilicon: add hi3620_mmc_clks
Suggest by Arnd: abstract mmc tuning as clock behavior,
also because different soc have different tuning method and registers.
hi3620_mmc_clks is added to handle mmc clock specifically on hi3620.

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26 16:03:56 -08:00
Haojian Zhuang
ea010e5188 clk: hi3620: add gate clock flag
Add missing CLK_SET_RATE_PARENT flag for gate clock.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2013-12-11 16:42:23 +08:00
Haojian Zhuang
5e39edd485 clk: hi3620: fix wrong flags on divider
The flags on dividers should be CLK_DIVIDER_HIWORD_MASK, not
CLK_MUX_HIWORD_MASK.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2013-12-11 16:42:11 +08:00
Haojian Zhuang
0aa0c95f74 clk: hisilicon: add common clock support
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is
used to support the clock gate that enable/disable/status registers
are seperated.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2013-12-04 18:36:45 +08:00