This patch fixes simple typos in Exynos5433 clocks driver. The SoC name
was referred a few times as '5443' instead of '5433'.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Default clock configuration applied by the bootloader for TM2 and TM2e
boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure
such configuration for those boards with 'assigned-clock-*' properties,
parameters for those two additional rates are needed.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
to setup initial clock configuration for display subsystem in device tree
in order to avoid dependency on the configuration left by the bootloader.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
In order to achieve all the rates asked by the GPU, we might need to change
the parent frequency.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The divider_get_val function that is used in our determine_rate callback
doesn't try to change the parent rate at all, while clk_divider_bestdiv,
used in divider_round_rate, does.
If we have a single parent, call divider_round_rate.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Add optional support for the Reset Control feature of the Renesas Clock
Pulse Generator / Module Standby and Software Reset module on R-Car
Gen2, R-Car Gen3, and RZ/G1 SoCs.
This allows to reset SoC devices using the Reset Controller API.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
The spinlock is used to protect Read-Modify-Write register accesses,
which won't be limited to SMSTPCR register accesses.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
The Renesas CPG/MSSR driver is already in active use for RZ/G1 since
commits c0b2d75d2a ("clk: renesas: cpg-mssr: Add R8A7743 support")
and 9127d54bb8 ("clk: renesas: cpg-mssr: Add R8A7745 support").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
As the function header of cpg_mstp_clock_register() is split in an
unusual way, "git diff" gets confused when changes to the body of
the function are made, and attributes them to the wrong function.
Reformat the function header to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
The BayTrail and CherryTrail platforms provide platform clocks
through their Power Management Controller (PMC).
The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a
frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail
and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks
are available for general system use, where appropriate, and each
have Control & Frequency register fields associated with them.
Port from legacy by Pierre Bossart, integration in clock framework
by Irina Tirdea
Signed-off-by: Irina Tirdea <irina.tirdea@intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Fix Makefile for x86 support, dependency on CONFIG_COMMON_CLK
was not explicit
Fixes: 701190fd74 ('clk: x86: add support for Lynxpoint LPSS clocks')
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
In clock driver initialize phase the spinlock is missed to assignment
to struct clkgate_separated, finally there have no locking to protect
exclusive accessing for clock registers.
This bug introduces the console has no output after enable coresight
driver on 96boards Hikey; this is because console using UART3, which
has shared the same register with coresight clock enabling bit. After
applied this patch it can assign lock properly to protect exclusive
accessing, and console can work well after enabled coresight modules.
Fixes: 0aa0c95f74 ("clk: hisilicon: add common clock support")
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk-ux500:
clk: ux500: Convert ABx500 clocks to use OF probing
clk: ux500: Add device tree bindings for ABx500 clocks
clk: ux500: move AB8500 sysclk over to PRCMU clk driver
These clocks have been broken for a long time unfortunately, a
hurdle of misc problems made them stop working at some point
breaking USB and audio on Ux500.
The platform as such and all "regular" clocks are migrated to
OF/device tree, so let's migrate also this driver.
With this patch and the corresponding DTS fixes, and a bunch
of probe deferral fixes, audio starts working again on Ux500.
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The AB8500 sysclk is just another PRCMU-controlled clock, there
is no reason why it should be in the ABx500-controlled part of
the clock implementation. Doing this and the corresponding device
tree changes makes USB work on the Ux500 again.
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The MT8135 is a 32-bit SoC, so only propose it on ARM architecture,
not ARM64.
Signed-off-by: Jean Delvare <jdelvare@suse.de>
Fixes: 234d511d8c ("clk: mediatek: Add hardware dependency")
Cc: Andreas Färber <afaerber@suse.de>
Acked-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
If I say "no" to "Clock driver for Mediatek MT2701", I don't want to
be asked individually about each sub-driver. No means no.
Additionally, this driver shouldn't be proposed at all on non-mediatek
builds, unless build-testing.
Signed-off-by: Jean Delvare <jdelvare@suse.de>
Fixes: e986211827 ("clk: mediatek: Add MT2701 clock support")
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Cc: Shunli Wang <shunli.wang@mediatek.com>
Cc: Erin Lo <erin.lo@mediatek.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Currently the divider selection logic blindly divides the parent_rate
by the clk rate and gives the divider value for the divider clocks
which do not have the CLK_SET_RATE_PARENT flag set. Add the clk divider
table parsing to get the closest divider available in the table
provided via Device tree.
The code is pretty much taken from: drivers/clk/clk-divider.c.
and used here to fix up the best divider selection logic.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Once a gdsc is brought in and out of HW control, there is a
power down and up cycle which can take upto 1us. Polling on
the gdsc status immediately after the hw control enable/disable
can mislead software/firmware to belive the gdsc is already either on
or off, while its yet to complete the power cycle.
To avoid this add a 1us delay post a enable/disable of HW control
mode.
Also after the HW control mode is disabled, poll on the status to
check gdsc status reflects its 'on' before force disabling it
in software.
Reported-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Reviewed-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Tested-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Fixes: 904bb4f5c7 ("clk: qcom: gdsc: Add support for gdscs with HW control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
During meson8b clock probe, clk81 register address is fixed twice.
First using the meson8b_clk_gates array, then by directly changing
meson8b_clk81 register.
As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base.
Fixed by just removing the second fixup.
Fixes: e31a1900c1 ("meson: clk: Add support for clock gates")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch enables clocks for STM32F746 boards.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Do not let the entire probe function fail even if some clocks fail
to register. Let's continue with succeeded clocks. This will give
the system more chances to boot and allow us to investigate the
cause of the failure.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same
silicon, and all share the same clocks.
However, they're not packaged in the same way, and therefore not all the
controllers are actually available on all these SoCs.
Introduce a clock controller driver for all these SoCs with different
compatibles to take that into account.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Some clocks have a global pre-divider that applies to all their parents.
Since it might also apply to clocks that have a single parent, this is
merged in the ccu_common structure, unlike the other pre-divider settings
that are tied to a specific index, and thus a specific parent.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Some multipliers have a maximum rate that is lower than what the register
width allows to. Add a field in the multiplier structure to allow CCU
driver to set that maximum.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The previous code was always taking 1 as the minimum in it's round_rate
function, ignoring entirely what was set as minimum in the clock
definition.
Make sure that's not the case anymore.
Fixes: 2beaa601c8 ("clk: sunxi-ng: Implement minimum for multipliers")
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The factors we've seen so far all had an offset of one. However, on the
earlier Allwinner SoCs, some factors could have no offset at all, meaning
that the value computed to reach the rate we want to use was the one we had
to program in the registers.
Implement an additional field for the factors that can have such an offset
(linears, not based on a power of two) to specify that offset.
This offset is not linked to the extremums that can be specified in those
structures too. The minimum and maximum are representing the range of
values we can use to try to compute the best rate. The offset comes later
on when we want to set the best value in the registers.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Some clocks on the earlier SoCs such as the video PLLs are multipliers with
fractional settings.
Support those cases.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
INTC-SYS is the module clock for the GIC. Accessing the GIC while it is
disabled causes:
Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
Currently, the GIC-400 driver cannot enable its module clock for several
reasons:
- It does not use a platform device, so Runtime PM is not an option,
- gic_of_init() runs before any clocks are registered, so it cannot
enable the clock explicitly,
- gic_of_init() cannot return -EPROBE_DEFER, as IRQCHIP_DECLARE()
doesn't support deferred probing.
Hence we have to keep on relying on the boot loader for enabling the
module clock.
To prevent the module clock from being disabled when the CCF core thinks
it is unused, and thus causing a system lock-up, add a check to the MSTP
clock driver and enable CLK_IS_CRITICAL. This will make sure the module
clock is never disabled.
This is a hard dependency for describing the INTC-SYS clock in DT on
R-Mobile APE6 and R-Car Gen2.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
When the Renesas CPG/MSSR driver was introduced, it was anticipated that
critical clocks would be handled through a new CLK_ENABLE_HAND_OFF flag
soon. However, CLK_ENABLE_HAND_OFF never made it upstream.
Instead, commit 32b9b10961 ("clk: Allow clocks to be marked as
CRITICAL") introduced CLK_IS_CRITICAL, a flag with slightly differing
semantics. Still, it can be used to prevent e.g. the GIC module clock
from being turned off, until the GIC-400 driver has full support for
Runtime PM.
Hence migrate the Renesas CPG/MSSR driver from CLK_ENABLE_HAND_OFF to
CLK_IS_CRITICAL.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
NIU clocks are related to the interconnect and it's important to other blocks.
Since we don't have a driver to handle it, we should always enable it to avoid
casually close.
Make all of them critical,so that we don't have to each clock on its own
once things break.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
[dropped the matching CLK_IGNORE_UNUSED flags]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reference the newly added vip clock-ids in the clock-tree.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
caused some of these clocks to turn off when they were always left
on before.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABCAAGBQJYgpUWAAoJEK0CiJfG5JUlebAP/j7R14isXPjOPSn3L+YWRISa
ChJP6pROSAGZz7e8ULTMpI8KVbQHVvBQbH0gX22mFFsXnd4aqh9lFRYK2rBRdwcJ
IKNpfHeSJ27XtBHWDqUSHlz18GuU7oHdldclQ1iKP8g8jpDuMEv3EDej3p7ylk6Q
aPh1zsLC2IGA4QBoQcOqlWQpsuT1546D37uQX+j4Wdmd+J48D0aEGeIDQuQyKBh6
kAdeAydzItYMeI0yegMppNIEDw5fhdYYqixlS2uwwEOHzsNsJNvR7EwmvRiS+9eO
Y6Mit+ixY2PLx7n0dbxCRAXbUcV/NciWr4PH34JR4AwFMrgMkpk0DhcuFFOWjdoa
JT5+/rUm+f6s7/dPi3q/M0W0uB2iTtKNNm1KkmhcJPlv3nYpsu1fKe9WhnLD2h0X
/OogaDfbfxKG3vLTmY9Q8N1yeUU7UscoFKX/DzuWE4iZdJoTzeKwBHitP5pgqbOj
xvUusBhVkAr/d5sIldIp/EG5V0ChELpLcbixOv/F0AMPFsMQBIgr3dYUixbCrGtC
yf5LBOjLYMCcwqrcplHazs7oB5NRKAui00kMaVsReBqWmtPcHGM3qE3585CoiFCE
Mnx+4XO2/idvV/QIR+//1npbjbiLyBDhBSTrFLroyvRTWrt+qd9YE16N5ghZv5GH
IHa5IzOcR66n5EH3E5BX
=0KLk
-----END PGP SIGNATURE-----
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fix from Stephen Boyd:
"One fix for Samsung Exynos524x SoCs where recent IOMMU patches have
caused some of these clocks to turn off when they were always left on
before"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk/samsung: exynos542x: mark some clocks as critical
Add the OCOTP so that this hardware block can be used.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This proved incredibly useful during debugging of the DSI driver, to
see if our clocks were running at rate we requested. Let's leave it
here for the next person interacting with clocks on the platform (and
so that hopefully we can just hook it up to debugfs some day).
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The DSI pixel clocks are muxed from clocks generated in the analog phy
by the DSI driver. In order to set them as parents, we need to do the
same name lookup dance on them as we do for our root oscillator.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Our core PLLs are intended to be configured once and left alone. With
the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would
change PLLD just to get closer to the requested DSI clock, thus
changing PLLD_PER, the UART and ethernet PHY clock rates downstream of
it, and breaking ethernet.
We *do* want PLLH to change so that PLLH_AUX can be exactly the value
we want, though. Thus, we need to have a per-divider policy of
whether to pass rate changes up.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These
chips have two clock inputs, XTAL or CLK, which are muxed into single
PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip
while the 5P49V5923 requires external XTAL.
The PLL feeds two fractional dividers. Each fractional divider feeds
output mux, which allows selecting between clock from the fractional
divider itself or from output mux on output N-1. In case of output
mux 0, the output N-1 is instead connected to the output from the mux
feeding the PLL.
The driver thus far supports only the 5P49V5923 and 5P49V5933, while
it should be easily extensible to the whole 5P49V59xx family of chips
as they are all pretty similar.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
controlled through the General Register Files, support for the rk3328
clock-controller (including a new pll-type) and the usual clock ids and
some fixes.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlh+vFMQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgf7TCACncJmYlvYp+aZEgBlEcyCTulHNSyRZHVPd
c4zBsgZmgxqmgrxe8YsW6DcfPP96MtL/C/fIupxTphxxfAS5HQx2KCeVpOrfffk7
lJ1CPyCP5GdjaZ98hKVuMpKVkQu1u26DTNWSy62hbSQQndbpP0NbGsIJJUFia1vm
JX0POVYt0xSo6GnbVRcKN/5b9k0HJNG9aejL8u/uA3+yr8diiKzYrtnaFzai5kvE
3LgXIDGPUZVfwZ2vrJfDCYqNlij/tF2yLIhEDDoMSl00WolJfmnMKOg1Lt0DzuMz
OQY6ZIexTV1CCV+9BjXMVCLth7DH7K3EztQsvyJtr90wrfYs+4Vd
=4WOJ
-----END PGP SIGNATURE-----
Merge tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull Rockchip clk updates from Heiko Stuebner:
A new clock-type for the 1-2 muxes per soc that are for whatever reason
controlled through the General Register Files, support for the rk3328
clock-controller (including a new pll-type) and the usual clock ids and
some fixes.
* tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
dt-bindings: clk: add rockchip,grf property for RK3399
clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188
clk: rockchip: use rk3288 isp_in clock ids
clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188
clk: rockchip: add rk3288 isp_in clock ids
clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER
clk: rockchip: add clock controller for rk3328
dt-bindings: add bindings for rk3328 clock controller
clk: rockchip: add dt-binding header for rk3328
clk: rockchip: add new pll-type for rk3328
clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288
clk: rockchip: add a clock-type for muxes based in the grf
- addition of the CPU clock configuration data for Exynos4412
Prime SoC variant,
- removal of driver for deprecated Exynos4415 SoC,
- switching from the syscore to regular system sleep PM ops
in the audio subsystem clocks controller driver,
- updates of the definitions of some "Network On Chip" related
clocks.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJYgPcFAAoJEE1bIKeAnHqLt9EP/0e5ljfUQRiczFvPVfUZeZb0
cn3HZrLBk+aDxDIBKpWSSUY0RraK6hjZYpwizRQyYBH7XFQY4aWxk2mtg+B5mPBT
OH02tjrFeQ+BG13BzYbMKg86jFrDqQEjlpMU6PHrILrQoRqoNBomlJXpC8Jw5Oqb
c79QxCsX8f94cbTgE3FHlF2ZHr8Wo4FKP2eWkdVBty1XvRvvZ1qE9IX6/wsqn1o7
WCoJpKq7UjX1U9gBeHZzFRgzpKjsSoSha7yW/CkxP6b0TksQUmGi81asFxdslqi3
xiK0PlsXB2R7TKNLNhU4hGcV7lvQFJaPOdWshvnQ7nFz9dlFjZkSGUTvLGYLH2+j
43nHnHqEP6avNYo5cBR27Wc2ZaARMXq7AMJvZHC2/DuhtaO70wKfFVib1nFe40pX
UBP5dxOy7C2taRxSr3QSmviuBwZYBmDWioE3SQE/IdM6z3WpN37kNrNw1OrMctji
MFCyIfeKlUpLJVZRcdKKxvem0QTPN5/cWote5ibNO+x0O9RWkXSrdBtnoioc5oL7
30TtZlGbKG9VsRRjxYhuul/lpTZvyewg5PP9T5xGmeXOF69SlPuZwOu26D3E2Lej
AiTMellqH7vjX2uNSQ4lQExzOj8psJ0Mq7hj5lRavsPn8m50PAHMfq+YHncii32I
E1HZF4sh7MYozX/2Els3
=mSQz
-----END PGP SIGNATURE-----
Merge tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull Samsung clk updates from Sylwester Nawrocki:
- addition of the CPU clock configuration data for Exynos4412
Prime SoC variant,
- removal of driver for deprecated Exynos4415 SoC,
- switching from the syscore to regular system sleep PM ops
in the audio subsystem clocks controller driver,
- updates of the definitions of some "Network On Chip" related
clocks.
* tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: Remove Exynos4415 driver (SoC not supported anymore)
clk: samsung: exynos-audss: Replace syscore PM with platform device PM
clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical
clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
The LDB mux/gate layout has been fixed on QuadPlus, so there is no need
to restrict the LDB mux changes on this hardware, as the erratum
preventing this from working properly is gone.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks
about CSI, are different, which makes it to need a new CCU driver.
Add such a new driver for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Export HDMI clock from internal to dt-bindings.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5.
Reported-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Tested-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The audio DAI needs to set the clock rates of the ac-dig clock.
To make it possible, the parent PLL audio clock rates should
also be changed. This is possible via "CLK_SET_RATE_PARENT" flag.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
1. Fixes for initial audio clocks configuration.
2. Enable sound on Odroid-X board.
3. Enable DMA for UART modules on Exynos5 SoCs.
4. Add CPU OPPs for Exynos4412 Prime (newer version of Exynos4412). This pulls
necessary change in the clocks.
5. Remove Exynos4212. We do not have any mainline boards with it. This will
simplify few bits later.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJYeOsYAAoJEME3ZuaGi4PXuSMP/RFjn4liQ4qG/uE5j6+7HDSF
PC/1yBYyo0xzg8oaEJVz7Ay6ydqNqBAMhPfdJzWk1lzN+zQc2MwLynH1fNNJTWSY
6YtBhNzx5sgs1IRtqG8RvSpj67OlE6i98YJL64j4VjNdhcTrRBPSbm2TDeu82uzh
VY3RDsXkTeWNwiHRuDXRqZ3VLfZ/xGjuT7Ym0cEMjPeuETNHs6jYVfi5e1d1c631
Ln2MJj0dpLbf+eUqkvLjv45LIHr6DmQHhuHlfwNu9iY6EmDtS+m9BKBxMvGrWzSp
5fy/3MpQo6+DD0GocnbsQpqylKmI5sXX9ly0A4F2ZWMRkoULVHv/5UrP7V9puHyO
Rd6i9RrpPDzAm81KRorFbwJnl2uJlomR5yWSISWQ51p6HXP1mFi+78YacUgCgNM0
TDCXhuGp1ZbJmBtq1Eae3C6Ku9GEtq9WLNkphWzeqUc4miZRwQ9NGBtZhbbgoFOl
XvANJAfVcS6PDJyadKlD/bktz8cyNO+H3jMPzlFRqaGW/E0yX8BbG01kjJhmR2dZ
qAMJtWT55PPNBss/ml67qezEYBXw9xwyo9d0vPnTWE0XvCL/p++Q+BEojKB8zYuE
4NJrj01CjZmpa8Ej3zpi6MLbVaKto5TjNTe981jzyAUpGlt2fiAuGmn85lTP2a0c
4LKCFLMZ8HGDMRL1WTkl
=w/rg
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Samsung DeviceTree update for v4.11:
1. Fixes for initial audio clocks configuration.
2. Enable sound on Odroid-X board.
3. Enable DMA for UART modules on Exynos5 SoCs.
4. Add CPU OPPs for Exynos4412 Prime (newer version of Exynos4412). This pulls
necessary change in the clocks.
5. Remove Exynos4212. We do not have any mainline boards with it. This will
simplify few bits later.
* tag 'samsung-dt-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: remove Exynos4212 support (dead code)
ARM: dts: exynos: Add CPU OPPs for Exynos4412 Prime
clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
ARM: dts: exynos: Enable DMA support for UART modules on Exynos5 SoCs
ARM: dts: exynos: Cleanup Odroid-X2 and enable sound on Odroid-X
ARM: dts: exynos: Fix initial audio clocks configuration on Exynos4 boards
ARM: dts: exynos: Correct clocks for Exynos4 I2S module
Signed-off-by: Olof Johansson <olof@lixom.net>
Support for Exynos4415 is going away because there are no internal nor
external users.
Since commit 46dcf0ff0d ("ARM: dts: exynos: Remove exynos4415.dtsi"),
the platform cannot be instantiated so remove also the drivers.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Kukjin Kim <kgene@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Add the newly added clock ids to the clock entries of the rk3066/rk3188
clock driver. We won't be needing them in the kernel for a bit yet
but as they're used in the new u-boot ddr setup code/dts we should make
sure the clock ids stay identical and do not differ.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reference the newly added isp clock-ids in the clock-tree.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The failure path in the newly added function tries to free an
uninitialized pointer:
drivers/clk/clk-stm32f4.c: In function 'stm32f4_rcc_init':
drivers/clk/clk-stm32f4.c:1106:4: error: 'gate' may be used uninitialized in this function [-Werror=maybe-uninitialized]
I'm adding an initialization to NULL here to make the kfree()
succeed, and I'm also rearranging the cleanup so that the
same kfree() is used for any error path, making the function
slightly more robust against newly introduced bugs in the
error handling.
Fixes: daf2d117cb ("clk: stm32f4: Add lcd-tft clock")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The CDCE925 is a member of the CDCE(L)9xx programmable clock generator
family. There are also CDCE913, CDCE937, CDCE949 which have different
number of PLLs and outputs.
The clk-cdce925 driver supports only CDCE925 in the family. This adds
support for the CDCE913, CDCE937, CDCE949, too.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: Mike Looijmans <mike.looijmans@topic.nl>
Cc: Michael Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add definition of EBI2 clock used by MDM9615 NAND controller.
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-soc@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
[sboyd@codeaurora.org: ebi2_clk halt bit is 24 not 23]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This include was needed to suppress build error when this driver
was initially merged because <linux/regmap.h> did not include
<linux/delay.h> at that time. (developers' headache across
sub-systems)
The root cause has been fixed by commit adf08d481b ("regmap:
include <linux/delay.h> from include/linux/regmap.h"), so this
line can be dropped now.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit adjusts the list of possible "Sample At Reset" values that
define the CPU clock frequency of the AP806 (part of Marvell Armada
7K/8K) to the values that have been validated with the production
chip. Earlier values were preliminary.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add clock drivers for hi3660 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
[sboyd@codeaurora.org: Simplify probe with function pointer]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Some parent clocks of the Exynos542x clock blocks, which have separate
power domains (like DISP, MFC, MSC, GSC, FSYS and G2D) must be always
enabled to access any register related to power management unit or devices
connected to it. For the time being, until a proper solution based on
runtime PM is applied, mark those clocks as critical (instead of ignore
unused or even no flags) to prevent disabling them.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> [Exynos5800 Peach Pi Chromebook]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
EPROBE_DEFER is not an error, hence printing an error message like
clk: couldn't get clock 0 for /soc/display@feb00000
may confuse the user.
Suppress error messages in case of probe deferral to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Currently we add the virtual cpufreq device unconditionally even when
the SCPI DVFS clock provider node is disabled. This will cause cpufreq
driver to throw errors when it gets initailised on boot/modprobe and
also when the CPUs are hot-plugged back in.
This patch fixes the issue by adding the virtual cpufreq device only if
the SCPI DVFS clock provider is available and registered.
Fixes: 9490f01e24 ("clk: scpi: add support for cpufreq virtual device")
Reported-by: Michał Zegan <webczat_200@poczta.onet.pl>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Tested-by: Michał Zegan <webczat_200@poczta.onet.pl>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add support to use reset control framework for resetting MSS
with hexagon v56 1.5.0.
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The audio related clock support is missing from the existing zx296718
clock driver. Let's add it, so that the upstream ZX SPDIF driver can
work for HDMI audio support.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
[sboyd@codeaurora.org: Staticize some more structures]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Instead of using panic, we should give an error message and return error
code when of_clk_add_hw_provider() call fails.
Since we have error prompt for failures, the "init over" pr_info output
isn't really necessary but becomes a debug noise. So let's clean it up
along the way.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The delay here is not in atomic context and does not seem critical with
respect to precision, but usleep_range(min,max) with min==max results in
giving the timer subsystem no room to optimize uncritical delays. Fix
this by setting the range to 2000,3000 us.
Fixes: commit f05259a6ff ("clk: wm831x: Add initial WM831x clock driver")
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
On vf610, PLL1 and PLL2 have registers to configure fractional part of
frequency multiplier.
This patch adds support for these registers.
This fixes "fast system clock" issue on boards where bootloader sets
fractional multiplier for PLL1.
Suggested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
CC: Chris Healy <cphealy@gmail.com>
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
turn all the clks on and another fix for stm32f4 SoCs where we have multiple
drivers attaching to the same DT node.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABCAAGBQJYb9ZVAAoJEK0CiJfG5JUlO2UQANIrI8mPjzrneEa0tCTNg2sj
ZL8tIAJ8xs3I4Mwnr7NTHVSWTlsuetKVrxck4/Oq5wGbeoFcnpFALWB+kwH2yIVX
GTrwIiv0NRFM5RFjve1jx7vpSxUu7VbU3bV1Ym3fhjD/Eo3qhAskJmp8lsAWVmKt
1hVqcUFfxn613qsmJxUoIj6o5ZWY8XUoloZaO/nz3zBwQpcy+1Fje+/VjE2xdVuH
Rh0RyTek3Pbt2hWZpyWUIzxWWNRneFL7ks1JFx+eInX/TerMKDFXBe7Op4fy3B4g
0Ko1ZGoLf8ufICSbNVEQa3O0/cdCfVR/qEg4V0zO48aWsLQJVdT4mzsINTCeBBz+
Vj18gaCShB8Q5tmgEbHQBKtysgV9EqJUjs7l6f41RVS0MHUC/V9Mnmgg26w1BAkG
JChNsdFIaFAvMgHpprhER+a7LA81bJBj//k7LfFrJKJlWZoDLLtKsp8dKEgA2VjN
el89fsk3acZSQLNTNbKBDEVEiCRhHQV5oXFESfHRVHZAYRNxSaCoC/yNeYfL+6ip
lCv8GVIH5Uqkz8w2PqAIKzBxoyP1dUih0k6xvjCBKyIcJix/2QriOU13ZdBMp2tL
7wni0M4yJceueY5v3BxwxzVDGN36WCc+ivzjrRDhjZDoK8joAtdTvpL5K2YkQzFz
tZokD8QMNLdfMGJMXyyG
=5ciP
-----END PGP SIGNATURE-----
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"One fix for a broken driver on Renesas RZ/A1 SoCs with bootloaders
that don't turn all the clks on and another fix for stm32f4 SoCs where
we have multiple drivers attaching to the same DT node"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method
clk: renesas: mstp: Support 8-bit registers for r7s72100
When we used to defer setting the "grf" member to
rockchip_clk_get_grf() it was important to init the "grf" member to an
error value in rockchip_clk_init(). With recent changes, we now set
"grf" right in rockchip_clk_init() (two lines below the place where we
initted it). That makes the old init useless. Get rid of it.
Fixes: 6f339dc271 ("clk: rockchip: lookup General Register Files in rockchip_clk_init")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the clock tree definition for the new rk3328 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
As the SPDIF was rarely documented on the earlier Allwinner SoCs
it was assumed that it had a similar clock register to the one
described in the H3 User Manual.
However this is not the case and it looks to shares the same setup
as the I2S clock registers.
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
be changeable by changing the rate of PLL_CPUX.
Add CLK_SET_RATE_PARENT flag to this clock.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
When adjusting PLL_CPUX on A33, the PLL is temporarily driven too high,
and the system hangs.
Add a notifier to avoid this situation by temporarily switching to a
known stable 24 MHz oscillator.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
When adjusting PLL_CPUX on H3, the PLL is temporarily driven
too high, and the system becomes unstable (oopses or hangs).
Add a notifier to avoid this situation by temporarily switching
to a known stable 24 MHz oscillator.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Tested-by: Lutz Sammer <johns98@gmx.net>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The rk3328's pll and clock are similar with rk3036's,
it different with pll_mode_mask, the rk3328 soc
pll mode only one bit(rk3036 soc have two bits)
so these should be independent and separate from
the series of rk3328s.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
With the newly introduced clk type for muxes in the grf we now can
describe some missing clocks, like the aclk_vcodec that selects between
aclk_vdpu and aclk_vepu based on a bit set in the general register files.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the general register
files. Add a clock-type that can control these as well, so that we
don't need to work around them being absent.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Exynos AUDSS clock driver has been already converted to platform driver,
so remove the dependency on the syscore ops - the last remaining
non-platform driver feature. Platform device's system sleep PM provides
all needed infrastructure for replacing syscore-based PM, so do it now.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
The ACLK_BUS0/1/2 are used for NoC (Network on Chip). If NoC's clocks are
disabled, the system halt happens. Following clocks must be always enabled:
- CLK_ACLK_BUS0_400 : NoC's bus clock for PERIC/PERIS/FSYS/MSCL,
- CLK_ACLK_BUS1_400 : NoC's bus clock for MFC/HEVC/G3D,
- CLK_ACLK_BUS2_400 : NoC's bus clock for GSCL/DISP/G2D/CAM0/CAM1/ISP.
This patch also adds the CLK_SET_RATE_PARENT flag to the CLK_SCLK_JPEG_MSCL
because this clock should be used for bus frequency scaling. This clock need
to be changed on the fly with CLK_SET_RATE_PARENT flag.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Add cpu clock configuration data for Exynos4412 Prime SoC
(it supports additional PLL rates & CPU frequencies).
Based on Hardkernel's kernel for ODROID-X2/U2/U3 boards.
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
The current driver code gives the crash or gets hang while switching
the CPU frequency some time. The APSS CPU Clock divider is not glitch
free so it the APPS clock need to be switched for stable clock during
the change.
This patch adds the frequency change notifier for APSS CPU clock. It
changes the parent of this clock to stable PLL FEPLL500 for
PRE_RATE_CHANGE event. This event will be generated before actual
clock set operations. The clock set operation will again change its
corresponding parent by getting the same from frequency table.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
[sboyd@codeaurora.org: Indent less in probe]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Clock and reset controller use same compatible strings (same IP).
Since commit 989eafd0b6 ("clk: core: Avoid double initialization of
clocks") the OF core flags clock controllers registered with the
CLK_OF_DECLARE() macro as OF_POPULATED, so platform devices with the same
compatible string will not be registered.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The RZ/A1 is different than the other Renesas SOCs because the MSTP
registers are 8-bit instead of 32-bit and if you try writing values as
32-bit nothing happens...meaning this driver never worked for r7s72100.
Fixes: b6face404f ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or
from pll-sai-p.
The SDIO clock could be also derived from 48Mhz or from sys clock.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch introduces SAI clocks for stm32f4 socs.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch introduces I2S clock for stm32f4 soc.
The I2S clock could be derived from an external clock or from pll-i2s
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch introduces lcd-tft clock for stm32f4 soc.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds post dividers of I2S & SAI PLLs.
These dividers are managed by a dedicated register (RCC_DCKCFGR).
The PLL should be off before a set rate.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch introduces PLL_I2S and PLL_SAI.
Vco clock of these PLLs can be modify by DT (only n multiplicator,
m divider is still fixed by the boot-loader).
Each PLL has 3 dividers. PLL should be off when we modify the rate.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@codeaurora.org: Mark stm32f4_pll_div_ops static]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This adds all RPM based clocks for msm8974, except cxo and
gfx3d_clk_src.
Tested-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
