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4 Commits

Author SHA1 Message Date
Jean-Christophe PLAGNIOL-VILLARD
bd737fea4e ARM: at91: sam9g45: shutdown ddr1 too when rebooting
Like we are doing on DDR0 we need to cleanly shutdown DDR1 if it is
used before rebooting.
If DDR1 is not initialized, we check it and avoid dereferencing its address.
Even by adding two more instructions, we are able to complete the procedure
within a single cache line.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-09-30 09:58:44 -07:00
Jean-Christophe PLAGNIOL-VILLARD
f0995d089e arm: at91: move reset controller header to arm/arm/mach-at91
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
2012-11-06 20:30:48 +08:00
Jean-Christophe PLAGNIOL-VILLARD
f363c407b4 ARM: at91: make sdram/ddr register base soc independent
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2012-02-23 14:57:56 +01:00
Jean-Christophe PLAGNIOL-VILLARD
14f991a730 ARM: at91: Fix at91sam9g45 and at91cap9 reset
As on the other sam9 we need to cleanly shutdown the DDRAM before rebooting.

On those SoC the SDRAM/DDRAM controller is different. So, the assembly code
ends up being not cleanly combined with previous at91sam9_alt_restart function.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2012-01-20 17:22:50 +01:00