Timers on Versatile Express mainboard are used as system clock/event
sources. Driver assumes that they are clocked with 1MHz signal.
Old V2M firmware apparently configured it by default, but on newer
boards one can observe that "sleep 1" command takes over 30 seconds
to finish, as the timers are fed with 32kHz instead...
This patch performs required magic and also removes code clearing
timer's control registers, as exactly the same operations are
performed by the timer driver few jiffies later.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix two section mismatch warnings in the platform SMP bringup code for
Realview and Versatile Express:
WARNING: arch/arm/mach-realview/built-in.o(.text+0x8ac): Section mismatch in reference from the function write_pen_release() to the variable .cpuinit.data:pen_release
The function write_pen_release() references
the variable __cpuinitdata pen_release.
This is often because write_pen_release lacks a __cpuinitdata
annotation or the annotation of pen_release is wrong.
WARNING: arch/arm/mach-vexpress/built-in.o(.text+0x7b4): Section mismatch in reference from the function write_pen_release() to the variable .cpuinit.data:pen_release
The function write_pen_release() references
the variable __cpuinitdata pen_release.
This is often because write_pen_release lacks a __cpuinitdata
annotation or the annotation of pen_release is wrong.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add a sched_clock() implementation to Versatile Express using the new
sched_clock() infrastructure for extending 32bit counters to full
64-bit nanoseconds.
Tested-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There is a subtle race in the CPU hotplug code, where a CPU which has
been offlined can online itself before being requested, which results
in things going astray on the next online/offline cycle.
What happens in the normal online/offline/online cycle is:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads -1
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
However, as the write of -1 of pen_release is not fully flushed back to
memory, and the checking of pen_release is done with caches disabled,
this allows CPU3 the opportunity to read the old value of pen_release:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads 3
starts boot
pen_release = -1
requests boot of CPU3
pen_release = 3
flush cache line
Fix this by grouping the write of pen_release along with its cache line
flushing code to ensure that any update to pen_release is always pushed
out to physical memory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
With "ARM: CPU hotplug: remove bug checks in platform_cpu_die()", we
now do not use hard_smp_processor_id(), we no longer need to read the
hardware processor ID. Remove the include providing this function.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
All platforms call trace_hardirqs_off() in their secondary startup code,
so move this into the core SMP code - it doesn't need to be in the
per-platform code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There is a certain amount of smp_prepare_cpus() which doesn't belong
in the platform support code - that is, code which is invariant to the
SMP implementation. Move this code into arch/arm/kernel/smp.c, and
add a platform_ prefix to the original function.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
scu_get_core_count() never returns zero cores, so we don't need to
check and correct if ncores is zero.
Tegra was missing the check against NR_CPUS, leading to a potential
bitfield overflow if this becomes the case.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Provide a standard get_irqnr_preamble assembler macro for platforms
to use, which retrieves the base address of the GIC CPU interface
from gic_cpu_base_addr. Allow platforms to override this by defining
HAVE_GET_IRQNR_PREAMBLE.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Every architecture using the GIC has a gic_cpu_base_addr pointer for
GIC 0 for their entry assembly code to use to decode the cause of the
current interrupt. Move this into the common GIC code.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
We don't need to re-pass the base address for the CPU interfaces to the
GIC for secondary CPUs, as it will never be different from the boot CPU
- and even if it was, we'd overwrite the boot CPU's base address.
Get rid of this argument, and rename to gic_secondary_init().
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Provide gic_init() which initializes the GIC distributor and current
CPU's GIC interface for the boot (or single) CPU.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Use the GIC demux code in asm/hardware/entry-macro-gic.S
on the Versatile Express subarchitecture.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This allows us to use smp_cross_call() to trigger a number of different
software generated interrupts, rather than combining them all on one
SGI. Recover the SGI number via do_IPI.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Directives such as .long and .word do not magically cause the
assembler location counter to become aligned in gas. As a
result, using these directives in code sections can result in
misaligned data words when building a Thumb-2 kernel
(CONFIG_THUMB2_KERNEL).
This is a Bad Thing, since the ABI permits the compiler to
assume that fundamental types of word size or above are word-
aligned when accessing them from C. If the data is not really
word-aligned, this can cause impaired performance and stray
alignment faults in some circumstances.
In general, the following rules should be applied when using
data word declaration directives inside code sections:
* .quad and .double:
.align 3
* .long, .word, .single, .float:
.align (or .align 2)
* .short:
No explicit alignment required, since Thumb-2
instructions are always 2 or 4 bytes in size.
immediately after an instruction.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
factorise some generic infrastructure to assist looking up struct clks
for the ARM & SH architecture.
as the code is identical at 99%
put the arch specific code for allocation as example in asm/clkdev.h
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
In commit bde28b84, I made the assumption that CONFIG_SMP is always set
for the quad-core ct-ca9x4 platform. As it turns out, people who aren't
using the SMP goodness are confronted with a build failure.
This patch fixes this issue by ensure that twd_base is only set if
local timers are being used (and therefore SMP support is configured).
Reported-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
From: Rob Herring <rob.herring@smooth-stone.com>
The timer-sp h/w used on versatile platforms can also be used for other
platforms, so move it to a common location.
Signed-off-by: Rob Herring <rob.herring@smooth-stone.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since we're now using addruart to establish the debug mapping, we can
remove the io_pg_offst and phys_io members of struct machine_desc.
The various declarations were removed using the following script:
grep -rl MACHINE_START arch/arm | xargs \
sed -i '/MACHINE_START/,/MACHINE_END/ { /\.\(phys_io\|io_pg_offst\)/d }'
[ Initial patch was from Jeremy Kerr, example script from Russell King ]
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Eric Miao <eric.miao at canonical.com>
Rather than checking the MMU status in every instance of addruart, do it
once in kernel/debug.S, and change the existing addruart macros to
return both physical and virtual addresses. The main debug code can then
select the appropriate address to use.
This will also allow us to retreive the address of a uart for the MMU
state that we're not current in.
Updated with fixes for OMAP from Jason Wang <jason77.wang@gmail.com>
and Tony Lindgren <tony@atomide.com>, and fix for versatile express from
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>.
Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Jason Wang <jason77.wang@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
WARNING: vmlinux.o(.text+0xbf30): Section mismatch in reference from the function v2m_timer_init() to the function .init.text:sp804_clocksource_init()
The function v2m_timer_init() references
the function __init sp804_clocksource_init().
This is often because v2m_timer_init lacks a __init
annotation or the annotation of sp804_clocksource_init is wrong.
WARNING: vmlinux.o(.text+0xbf3c): Section mismatch in reference from the function v2m_timer_init() to the function .init.text:sp804_clockevents_init()
The function v2m_timer_init() references
the function __init sp804_clockevents_init().
This is often because v2m_timer_init lacks a __init
annotation or the annotation of sp804_clockevents_init is wrong.
WARNING: vmlinux.o(.text+0xc524): Section mismatch in reference from the function ct_ca9x4_init() to the function .init.text:l2x0_init()
The function ct_ca9x4_init() references
the function __init l2x0_init().
This is often because ct_ca9x4_init lacks a __init
annotation or the annotation of l2x0_init is wrong.
WARNING: vmlinux.o(.text+0xc530): Section mismatch in reference from the function ct_ca9x4_init() to the function .init.text:clkdev_add_table()
The function ct_ca9x4_init() references
the function __init clkdev_add_table().
This is often because ct_ca9x4_init lacks a __init
annotation or the annotation of clkdev_add_table is wrong.
WARNING: vmlinux.o(.text+0xc578): Section mismatch in reference from the function ct_ca9x4_init() to the (unknown reference) .init.data:(unknown)
The function ct_ca9x4_init() references
the (unknown reference) __initdata (unknown).
This is often because ct_ca9x4_init lacks a __initdata
annotation or the annotation of (unknown) is wrong.
Fix these by making ct_ca9x4_init() and v2m_timer_init() both __init.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The PL310 on the ct-ca9x4 tile for the Versatile Express does not need
to add additional latency when accessing its cache RAMs. Unfortunately,
the boot monitor sets this up for an 8-cycle delay on reads and writes,
resulting in greatly reduced memory performance when the L2 cache is
enabled.
This patch sets the L2 RAM latencies to the correct value of 1 cycle
on the ct-ca9x4 tile before enabling the L2 cache.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: <stable@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (291 commits)
ARM: AMBA: Add pclk support to AMBA bus infrastructure
ARM: 6278/2: fix regression in RealView after the introduction of pclk
ARM: 6277/1: mach-shmobile: Allow users to select HZ, default to 128
ARM: 6276/1: mach-shmobile: remove duplicate NR_IRQS_LEGACY
ARM: 6246/1: mmci: support larger MMCIDATALENGTH register
ARM: 6245/1: mmci: enable hardware flow control on Ux500 variants
ARM: 6244/1: mmci: add variant data and default MCICLOCK support
ARM: 6243/1: mmci: pass power_mode to the translate_vdd callback
ARM: 6274/1: add global control registers definition header file for nuc900
mx2_camera: fix type of dma buffer virtual address pointer
mx2_camera: Add soc_camera support for i.MX25/i.MX27
arm/imx/gpio: add spinlock protection
ARM: Add support for the LPC32XX arch
ARM: LPC32XX: Arch config menu supoport and makefiles
ARM: LPC32XX: Phytec 3250 platform support
ARM: LPC32XX: Misc support functions
ARM: LPC32XX: Serial support code
ARM: LPC32XX: System suspend support
ARM: LPC32XX: GPIO, timer, and IRQ drivers
ARM: LPC32XX: Clock driver
...
The MMC card detection sense has become really confused with negations
at various levels, leading to some platforms not detecting inserted
cards. Fix this by converting everything to positive logic throughout,
thereby getting rid of these negations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add a dummy clk definition for the APB pclk signal on all platforms
using the AMBA bus infrastructure. This ensures that these platforms
continue to work when the core amba bus code controls the APB pclk.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds support for the Cortex-A9 local timers available when
using the CA9X4 daughterboard with the Versatile Express.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When not aligned, random bits could be written in the initial page table
by the __create_page_tables() function.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Implicit slab.h inclusion via percpu.h is about to go away. Make sure
gfp.h or slab.h is included as necessary.
Signed-off-by: Tejun Heo <tj@kernel.org>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
This patch updates the initialisation routines for the Realview boards
and the Versatile Express board [ca9x4 tile] so that they register their
PMU IRQs with the PMU framework in the Kernel.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
